From 1203acc8fd8ed8a1359e293b786b1396f87671fc Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Tue, 7 Oct 2025 12:01:06 +0200 Subject: [PATCH 1/8] Initial update for RA6M5 MCUs --- .../cmake/renesas/delays/ra6m5ag.cmake | 2 +- .../cmake/renesas/delays/ra6m5ah.cmake | 2 +- .../cmake/renesas/delays/ra6m5bf.cmake | 2 +- .../cmake/renesas/delays/ra6m5bg.cmake | 2 +- .../cmake/renesas/delays/ra6m5bh.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake | 2 +- ARM/gcc_clang/def/R7FA6M5AG2CBG.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AG2CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AG3CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AG3CFB.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AG3CFC.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AG3CFP.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH2CBG.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH2CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH3CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH3CFB.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH3CFC.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5AH3CFP.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF2CBG.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF2CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF3CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF3CFB.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF3CFC.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BF3CFP.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG2CBG.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG2CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG3CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG3CFB.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG3CFC.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BG3CFP.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH2CBG.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH2CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH3CBM.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH3CFB.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH3CFC.json | 1019 +++++ ARM/gcc_clang/def/R7FA6M5BH3CFP.json | 1019 +++++ ARM/gcc_clang/def/renesas/R7FA6M5AG2CBG/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AG2CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AG3CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AG3CFB/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AG3CFC/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AG3CFP/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH2CBG/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH2CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH3CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH3CFB/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH3CFC/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5AH3CFP/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF2CBG/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF2CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF3CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF3CFB/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF3CFC/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BF3CFP/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG2CBG/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG2CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG3CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG3CFB/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG3CFC/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BG3CFP/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH2CBG/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH2CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH3CBM/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH3CFB/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH3CFC/mcu.h | 80 +- ARM/gcc_clang/def/renesas/R7FA6M5BH3CFP/mcu.h | 80 +- .../r7fa6m5ag2cbg/interrupts_mcu.h | 21 +- .../r7fa6m5ag2cbm/interrupts_mcu.h | 21 +- .../r7fa6m5ag3cbm/interrupts_mcu.h | 21 +- .../r7fa6m5ag3cfb/interrupts_mcu.h | 21 +- .../r7fa6m5ag3cfc/interrupts_mcu.h | 21 +- .../r7fa6m5ag3cfp/interrupts_mcu.h | 21 +- .../r7fa6m5ah2cbg/interrupts_mcu.h | 21 +- .../r7fa6m5ah2cbm/interrupts_mcu.h | 21 +- .../r7fa6m5ah3cbm/interrupts_mcu.h | 21 +- .../r7fa6m5ah3cfb/interrupts_mcu.h | 21 +- .../r7fa6m5ah3cfc/interrupts_mcu.h | 21 +- .../r7fa6m5ah3cfp/interrupts_mcu.h | 21 +- .../r7fa6m5bf2cbg/interrupts_mcu.h | 21 +- .../r7fa6m5bf2cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bf3cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bf3cfb/interrupts_mcu.h | 21 +- .../r7fa6m5bf3cfc/interrupts_mcu.h | 21 +- .../r7fa6m5bf3cfp/interrupts_mcu.h | 21 +- .../r7fa6m5bg2cbg/interrupts_mcu.h | 21 +- .../r7fa6m5bg2cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bg3cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bg3cfb/interrupts_mcu.h | 21 +- .../r7fa6m5bg3cfc/interrupts_mcu.h | 21 +- .../r7fa6m5bg3cfp/interrupts_mcu.h | 21 +- .../r7fa6m5bh2cbg/interrupts_mcu.h | 21 +- .../r7fa6m5bh2cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bh3cbm/interrupts_mcu.h | 21 +- .../r7fa6m5bh3cfb/interrupts_mcu.h | 21 +- .../r7fa6m5bh3cfc/interrupts_mcu.h | 21 +- .../r7fa6m5bh3cfp/interrupts_mcu.h | 21 +- .../renesas/clang-llvm/r7fa6m5ag2cbg.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ag2cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ag3cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ag3cfb.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ag3cfc.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ag3cfp.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah2cbg.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah2cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah3cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah3cfb.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah3cfc.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5ah3cfp.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf2cbg.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf2cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf3cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf3cfb.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf3cfc.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bf3cfp.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg2cbg.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg2cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg3cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg3cfb.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg3cfc.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bg3cfp.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bh2cbg.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bh2cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bh3cbm.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bh3cfb.ld | 1553 ++++---- .../renesas/clang-llvm/r7fa6m5bh3cfc.ld | 1552 ++++---- .../renesas/clang-llvm/r7fa6m5bh3cfp.ld | 1553 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag2cbg.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag2cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag3cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag3cfb.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag3cfc.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ag3cfp.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah2cbg.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah2cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah3cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah3cfb.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah3cfc.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5ah3cfp.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf2cbg.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf2cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf3cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf3cfb.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf3cfc.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bf3cfp.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg2cbg.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg2cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg3cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg3cfb.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg3cfc.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bg3cfp.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh2cbg.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh2cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh3cbm.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh3cfb.ld | 1488 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh3cfc.ld | 1487 ++++---- .../gcc_arm_none_eabi/r7fa6m5bh3cfp.ld | 1488 ++++---- ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbg.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ag3cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfb.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfc.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfp.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbg.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah3cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfb.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfc.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfp.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbg.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf3cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfb.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfc.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfp.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbg.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg3cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfb.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfc.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfp.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbg.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh3cbm.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfb.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfc.c | 17 +- ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfp.c | 17 +- .../thirdparty/ra6m5ag/m-profile/armv8m_mpu.h | 421 +++ .../thirdparty/ra6m5ag/ra6m5_core_cm33.h | 3262 +++++++++++++++++ .../thirdparty/ra6m5ah/m-profile/armv8m_mpu.h | 421 +++ .../thirdparty/ra6m5ah/ra6m5_core_cm33.h | 3262 +++++++++++++++++ .../thirdparty/ra6m5bf/m-profile/armv8m_mpu.h | 421 +++ .../thirdparty/ra6m5bf/ra6m5_core_cm33.h | 3262 +++++++++++++++++ .../thirdparty/ra6m5bg/m-profile/armv8m_mpu.h | 421 +++ .../thirdparty/ra6m5bg/ra6m5_core_cm33.h | 3262 +++++++++++++++++ .../thirdparty/ra6m5bh/m-profile/armv8m_mpu.h | 421 +++ .../thirdparty/ra6m5bh/ra6m5_core_cm33.h | 3262 +++++++++++++++++ 200 files changed, 92765 insertions(+), 51008 deletions(-) create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/m-profile/armv8m_mpu.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/ra6m5_core_cm33.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/m-profile/armv8m_mpu.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/ra6m5_core_cm33.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/m-profile/armv8m_mpu.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/ra6m5_core_cm33.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/m-profile/armv8m_mpu.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/ra6m5_core_cm33.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/m-profile/armv8m_mpu.h create mode 100644 ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/ra6m5_core_cm33.h diff --git a/ARM/gcc_clang/cmake/renesas/delays/ra6m5ag.cmake b/ARM/gcc_clang/cmake/renesas/delays/ra6m5ag.cmake index d1e4e557a..f73404634 100644 --- a/ARM/gcc_clang/cmake/renesas/delays/ra6m5ag.cmake +++ b/ARM/gcc_clang/cmake/renesas/delays/ra6m5ag.cmake @@ -1,3 +1,3 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AG2CBG$|^R7FA6M5AG2CBM$|^R7FA6M5AG3CBM$|^R7FA6M5AG3CFB$|^R7FA6M5AG3CFC$|^R7FA6M5AG3CFP$") - list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/4)") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/9)") endif() diff --git a/ARM/gcc_clang/cmake/renesas/delays/ra6m5ah.cmake b/ARM/gcc_clang/cmake/renesas/delays/ra6m5ah.cmake index c2c2def83..8004054f2 100644 --- a/ARM/gcc_clang/cmake/renesas/delays/ra6m5ah.cmake +++ b/ARM/gcc_clang/cmake/renesas/delays/ra6m5ah.cmake @@ -1,3 +1,3 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AH2CBG$|^R7FA6M5AH2CBM$|^R7FA6M5AH3CBM$|^R7FA6M5AH3CFB$|^R7FA6M5AH3CFC$|^R7FA6M5AH3CFP$") - list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/4)") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/9)") endif() diff --git a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bf.cmake b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bf.cmake index 6e0fc20e7..3f4410b58 100644 --- a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bf.cmake +++ b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bf.cmake @@ -1,3 +1,3 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BF2CBG$|^R7FA6M5BF2CBM$|^R7FA6M5BF3CBM$|^R7FA6M5BF3CFB$|^R7FA6M5BF3CFC$|^R7FA6M5BF3CFP$") - list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/4)") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/9)") endif() diff --git a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bg.cmake b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bg.cmake index 2d738235c..7797f2449 100644 --- a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bg.cmake +++ b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bg.cmake @@ -1,3 +1,3 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BG2CBG$|^R7FA6M5BG2CBM$|^R7FA6M5BG3CBM$|^R7FA6M5BG3CFB$|^R7FA6M5BG3CFC$|^R7FA6M5BG3CFP$") - list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/4)") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/9)") endif() diff --git a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bh.cmake b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bh.cmake index 012f3aea8..eadab0cd4 100644 --- a/ARM/gcc_clang/cmake/renesas/delays/ra6m5bh.cmake +++ b/ARM/gcc_clang/cmake/renesas/delays/ra6m5bh.cmake @@ -1,3 +1,3 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BH2CBG$|^R7FA6M5BH2CBM$|^R7FA6M5BH3CBM$|^R7FA6M5BH3CFB$|^R7FA6M5BH3CFC$|^R7FA6M5BH3CFP$") - list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/4)") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/9)") endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake index 0e9438cb8..f34d323e8 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake @@ -1,7 +1,7 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AG2CBG$|^R7FA6M5AG2CBM$|^R7FA6M5AG3CBM$|^R7FA6M5AG3CFB$|^R7FA6M5AG3CFC$|^R7FA6M5AG3CFP$") set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) - list(APPEND local_list_include system/src/renesas/ra6m5ag/init_clock.c) + list(APPEND local_list_include system/src/${vendor}/ra6m5ag/init_clock.c) list(APPEND local_dir_install system/src/renesas/ra6m5ag/thirdparty/ra6m5ag) set(${thirdpartyInstall} ra6m5ag/thirdparty/ra6m5ag PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake index 2555efaab..e80f9b4b3 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake @@ -1,7 +1,7 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AH2CBG$|^R7FA6M5AH2CBM$|^R7FA6M5AH3CBM$|^R7FA6M5AH3CFB$|^R7FA6M5AH3CFC$|^R7FA6M5AH3CFP$") set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) - list(APPEND local_list_include system/src/renesas/ra6m5ah/init_clock.c) + list(APPEND local_list_include system/src/${vendor}/ra6m5ah/init_clock.c) list(APPEND local_dir_install system/src/renesas/ra6m5ah/thirdparty/ra6m5ah) set(${thirdpartyInstall} ra6m5ah/thirdparty/ra6m5ah PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake index 84e0df654..7b4c7e18d 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake @@ -1,7 +1,7 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BF2CBG$|^R7FA6M5BF2CBM$|^R7FA6M5BF3CBM$|^R7FA6M5BF3CFB$|^R7FA6M5BF3CFC$|^R7FA6M5BF3CFP$") set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) - list(APPEND local_list_include system/src/renesas/ra6m5bf/init_clock.c) + list(APPEND local_list_include system/src/${vendor}/ra6m5bf/init_clock.c) list(APPEND local_dir_install system/src/renesas/ra6m5bf/thirdparty/ra6m5bf) set(${thirdpartyInstall} ra6m5bf/thirdparty/ra6m5bf PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake index bff270cd0..587d09548 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake @@ -1,7 +1,7 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BG2CBG$|^R7FA6M5BG2CBM$|^R7FA6M5BG3CBM$|^R7FA6M5BG3CFB$|^R7FA6M5BG3CFC$|^R7FA6M5BG3CFP$") set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) - list(APPEND local_list_include system/src/renesas/ra6m5bg/init_clock.c) + list(APPEND local_list_include system/src/${vendor}/ra6m5bg/init_clock.c) list(APPEND local_dir_install system/src/renesas/ra6m5bg/thirdparty/ra6m5bg) set(${thirdpartyInstall} ra6m5bg/thirdparty/ra6m5bg PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake index 3a40ac746..b3790c992 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake @@ -1,7 +1,7 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BH2CBG$|^R7FA6M5BH2CBM$|^R7FA6M5BH3CBM$|^R7FA6M5BH3CFB$|^R7FA6M5BH3CFC$|^R7FA6M5BH3CFP$") set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) - list(APPEND local_list_include system/src/renesas/ra6m5bh/init_clock.c) + list(APPEND local_list_include system/src/${vendor}/ra6m5bh/init_clock.c) list(APPEND local_dir_install system/src/renesas/ra6m5bh/thirdparty/ra6m5bh) set(${thirdpartyInstall} ra6m5bh/thirdparty/ra6m5bh PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json index 6f0abca10..7a8a529c1 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": "PCKB", + "label": "Peripheral Module Clock B (PCLKB) Select", + "mask": "700", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100" + }, + { + "label": "x1/4", + "value": "200" + }, + { + "label": "x1/8", + "value": "300" + }, + { + "label": "x1/16", + "value": "400" + }, + { + "label": "x1/32", + "value": "500" + }, + { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": "6000" + } + ] + }, + { + "hidden": false, + "init": "20000", + "key": "BCK", + "label": "External Bus Clock (BCLK) Select", + "mask": "70000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000" + }, + { + "label": "x1/4", + "value": "20000" + }, + { + "label": "x1/8", + "value": "30000" + }, + { + "label": "x1/16", + "value": "40000" + }, + { + "label": "x1/32", + "value": "50000" + }, + { + "label": "x1/64", + "value": "60000" + } + ] + }, + { + "hidden": false, + "init": "2000000", + "key": "ICK", + "label": "System Clock (ICLK) Select", + "mask": "7000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000000" + }, + { + "label": "x1/4", + "value": "2000000" + }, + { + "label": "x1/8", + "value": "3000000" + }, + { + "label": "x1/16", + "value": "4000000" + }, + { + "label": "x1/32", + "value": "5000000" + }, + { + "label": "x1/64", + "value": "6000000" + } + ] + }, + { + "hidden": false, + "init": "20000000", + "key": "FCK", + "label": "FlashIF Clock (FCLK) Select", + "mask": "70000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000000" + }, + { + "label": "x1/4", + "value": "20000000" + }, + { + "label": "x1/8", + "value": "30000000" + }, + { + "label": "x1/16", + "value": "40000000" + }, + { + "label": "x1/32", + "value": "50000000" + }, + { + "label": "x1/64", + "value": "60000000" + } + ] + } + ], + "key": "SYSTEM_SCKDIVCR", + "unused": "88f88888" + }, + { + "address": "4001e026", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "CKSEL", + "label": "Clock Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator (MOSC)", + "value": "3" + }, + { + "label": "Sub-clock oscillator (SOSC)", + "value": "4" + }, + { + "label": "PLL", + "value": "5" + } + ] + } + ], + "key": "SYSTEM_SCKSCR", + "unused": "000000f8" + }, + { + "address": "4001e028", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PLIDIV", + "label": "PLL Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "/1", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PLSRCSEL", + "label": "PLL Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLLMUL", + "label": "PLL Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": 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"4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG2CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json index fdf4d2faf..3b378a1aa 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": "PCKB", + "label": "Peripheral Module Clock B (PCLKB) Select", + "mask": "700", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100" + }, + { + "label": "x1/4", + "value": "200" + }, + { + "label": "x1/8", + "value": "300" + }, + { + "label": "x1/16", + "value": "400" + }, + { + "label": "x1/32", + "value": "500" + }, + { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": "6000" + } + ] + }, + { + "hidden": false, + "init": "20000", + "key": "BCK", + "label": "External Bus Clock (BCLK) Select", + "mask": "70000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", 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"fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json index d0919fd21..cb8aeab52 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + 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"settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + 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MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": 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"default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": 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"settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] 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"delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CFP", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json index ae8cde703..ddf06eb1d 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + 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+ "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH2CBG", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json index 3ff431ddc..1c5bd28aa 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + 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us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": 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b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": "PCKB", + "label": "Peripheral Module Clock B (PCLKB) Select", + "mask": "700", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100" + }, + { + "label": "x1/4", + "value": "200" + }, + { + "label": "x1/8", + "value": "300" + }, + { + "label": "x1/16", + "value": "400" + }, + { + "label": "x1/32", + "value": "500" + }, + { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": 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false, + "init": "20000000", + "key": "FCK", + "label": "FlashIF Clock (FCLK) Select", + "mask": "70000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000000" + }, + { + "label": "x1/4", + "value": "20000000" + }, + { + "label": "x1/8", + "value": "30000000" + }, + { + "label": "x1/16", + "value": "40000000" + }, + { + "label": "x1/32", + "value": "50000000" + }, + { + "label": "x1/64", + "value": "60000000" + } + ] + } + ], + "key": "SYSTEM_SCKDIVCR", + "unused": "88f88888" + }, + { + "address": "4001e026", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "CKSEL", + "label": "Clock Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator (MOSC)", + "value": "3" + }, + { + "label": "Sub-clock oscillator (SOSC)", + "value": "4" + }, + { + "label": "PLL", + "value": "5" + } + ] + } + ], + "key": "SYSTEM_SCKSCR", + "unused": "000000f8" + }, + { + "address": "4001e028", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PLIDIV", + "label": "PLL Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "/1", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PLSRCSEL", + "label": "PLL Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLLMUL", + "label": "PLL Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": 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{ + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH3CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json index e6bc8eff8..04744e96c 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": 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100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", 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a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json index 8d3922dac..c4bd716be 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": "PCKB", + "label": "Peripheral Module Clock B (PCLKB) Select", + "mask": "700", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100" + }, + { + "label": "x1/4", + "value": "200" + }, + { + "label": "x1/8", + "value": "300" + }, + { + "label": "x1/16", + "value": "400" + }, + { + "label": "x1/32", + "value": "500" + }, + { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": "6000" + } + ] + }, + { + "hidden": false, + "init": "20000", + "key": "BCK", + "label": "External Bus Clock (BCLK) Select", + "mask": "70000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000" + }, + { + "label": "x1/4", + "value": "20000" + }, + { + "label": "x1/8", + "value": "30000" + }, + { + "label": "x1/16", + "value": "40000" + }, + { + "label": "x1/32", + "value": "50000" + }, + { + "label": "x1/64", + "value": "60000" + } + ] + }, + { + "hidden": false, + "init": "2000000", + "key": "ICK", + "label": "System Clock (ICLK) Select", + "mask": "7000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000000" + }, + { + "label": "x1/4", + "value": "2000000" + }, + { + "label": "x1/8", + "value": "3000000" + }, + { + "label": "x1/16", + "value": "4000000" + }, + { + "label": "x1/32", + "value": "5000000" + }, + { + "label": "x1/64", + "value": "6000000" + } + ] + }, + { + "hidden": false, + "init": "20000000", + "key": "FCK", + "label": "FlashIF Clock (FCLK) Select", + "mask": "70000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000000" + }, + { + "label": "x1/4", + "value": "20000000" + }, + { + "label": "x1/8", + "value": "30000000" + }, + { + "label": "x1/16", + "value": "40000000" + }, + { + "label": "x1/32", + "value": "50000000" + }, + { + "label": "x1/64", + "value": "60000000" + } + ] + } + ], + "key": "SYSTEM_SCKDIVCR", + "unused": "88f88888" + }, + { + "address": "4001e026", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "CKSEL", + "label": "Clock Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator (MOSC)", + "value": "3" + }, + { + "label": "Sub-clock oscillator (SOSC)", + "value": "4" + }, + { + "label": "PLL", + "value": "5" + } + ] + } + ], + "key": "SYSTEM_SCKSCR", + "unused": "000000f8" + }, + { + "address": "4001e028", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PLIDIV", + "label": "PLL Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "/1", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PLSRCSEL", + "label": "PLL Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLLMUL", + "label": "PLL Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF3CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json index 97c7319d5..79c83857a 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": 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b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + 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"value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG2CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json index b4301f61c..dccbb18ef 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + } + ] + }, + { + "hidden": false, + "init": "200", + "key": "PCKB", + "label": "Peripheral Module Clock B (PCLKB) Select", + "mask": "700", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "100" + }, + { + "label": "x1/4", + "value": "200" + }, + { + "label": "x1/8", + "value": "300" + }, + { + "label": "x1/16", + "value": "400" + }, + { + "label": "x1/32", + "value": "500" + }, + { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": "6000" + } + ] + }, + { + "hidden": false, + "init": "20000", + "key": "BCK", + "label": "External Bus Clock (BCLK) Select", + "mask": "70000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000" + }, + { + "label": "x1/4", + "value": "20000" + }, + { + "label": "x1/8", + "value": "30000" + }, + { + "label": "x1/16", + "value": "40000" + }, + { + "label": "x1/32", + "value": "50000" + }, + { + "label": "x1/64", + "value": "60000" + } + ] + }, + { + "hidden": false, + "init": "2000000", + "key": "ICK", + "label": "System Clock (ICLK) Select", + "mask": "7000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000000" + }, + { + "label": "x1/4", + "value": "2000000" + }, + { + "label": "x1/8", + "value": "3000000" + }, + { + "label": "x1/16", + "value": "4000000" + }, + { + "label": "x1/32", + "value": "5000000" + }, + { + "label": "x1/64", + "value": "6000000" + } + ] + }, + { + "hidden": false, + "init": "20000000", + "key": "FCK", + "label": "FlashIF Clock (FCLK) Select", + "mask": "70000000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000000" + }, + { + "label": "x1/4", + "value": "20000000" + }, + { + "label": "x1/8", + "value": "30000000" + }, + { + "label": "x1/16", + "value": "40000000" + }, + { + "label": "x1/32", + "value": "50000000" + }, + { + "label": "x1/64", + "value": "60000000" + } + ] + } + ], + "key": "SYSTEM_SCKDIVCR", + "unused": "88f88888" + }, + { + "address": "4001e026", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "CKSEL", + "label": "Clock Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "Main clock oscillator (MOSC)", + "value": "3" + }, + { + "label": "Sub-clock oscillator (SOSC)", + "value": "4" + }, + { + "label": "PLL", + "value": "5" + } + ] + } + ], + "key": "SYSTEM_SCKSCR", + "unused": "000000f8" + }, + { + "address": "4001e028", + "default": "1300", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "PLIDIV", + "label": "PLL Input Frequency Division Ratio Select", + "mask": "3", + "settings": [ + { + "label": "/1", + "value": "0" + }, + { + "label": "/2", + "value": "1" + }, + { + "label": "/3", + "value": "2" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "PLSRCSEL", + "label": "PLL Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLLMUL", + "label": "PLL Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG3CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json index 905cbea42..d2c72f36a 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": 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100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", 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a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json index c1257b3df..d37bc3b07 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + 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"LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH2CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json index 3317512b6..97752258b 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": 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+ { + "label": "x1/64", + "value": "600" + } + ] + }, + { + "hidden": false, + "init": "2000", + "key": "PCKA", + "label": "Peripheral Module Clock A (PCLKA) Select", + "mask": "7000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1000" + }, + { + "label": "x1/4", + "value": "2000" + }, + { + "label": "x1/8", + "value": "3000" + }, + { + "label": "x1/16", + "value": "4000" + }, + { + "label": "x1/32", + "value": "5000" + }, + { + "label": "x1/64", + "value": "6000" + } + ] + }, + { + "hidden": false, + "init": "20000", + "key": "BCK", + "label": "External Bus Clock (BCLK) Select", + "mask": "70000", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10000" + }, + { + "label": "x1/4", + "value": "20000" + }, + { + "label": "x1/8", + "value": "30000" + }, + { + "label": "x1/16", + "value": "40000" + }, + { + "label": "x1/32", + "value": "50000" + }, + { + "label": "x1/64", + "value": "60000" + } + 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"label": "PLL Clock Source Select", + "mask": "10", + "settings": [ + { + "label": "Main clock oscillator", + "value": "0" + }, + { + "label": "HOCO", + "value": "10" + } + ] + }, + { + "hidden": false, + "init": "1300", + "key": "PLLMUL", + "label": "PLL Frequency Multiplication Factor Select", + "mask": "3f00", + "settings": [ + { + "label": "x10.0", + "value": "1300" + }, + { + "label": "x10.5", + "value": "1400" + }, + { + "label": "x11.0", + "value": "1500" + }, + { + "label": "x11.5", + "value": "1600" + }, + { + "label": "x12.0", + "value": "1700" + }, + { + "label": "x12.5", + "value": "1800" + }, + { + "label": "x13.0", + "value": "1900" + }, + { + "label": "x13.5", + "value": "1a00" + }, + { + "label": "x14.0", + "value": "1b00" + }, + { + "label": "x14.5", + "value": "1c00" + }, + { + "label": "x15.0", + "value": "1d00" + }, + { + "label": "x15.5", + "value": "1e00" + }, + { + "label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + 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"settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CBM", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json index 96ac5ba44..a7517fe99 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + 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"delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CFB", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json index 1a8eacb8f..c4699fbfe 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json @@ -1,4 +1,1023 @@ { + "config_registers": [ + { + "address": "4001e020", + "default": "22022222", + "fields": [ + { + "hidden": false, + "init": "2", + "key": "PCKD", + "label": "Peripheral Module Clock D (PCLKD) Select", + "mask": "7", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "1" + }, + { + "label": "x1/4", + "value": "2" + }, + { + "label": "x1/8", + "value": "3" + }, + { + "label": "x1/16", + "value": "4" + }, + { + "label": "x1/32", + "value": "5" + }, + { + "label": "x1/64", + "value": "6" + } + ] + }, + { + "hidden": false, + "init": "20", + "key": "PCKC", + "label": "Peripheral Module Clock C (PCLKC) Select", + "mask": "70", + "settings": [ + { + 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"label": "x16.0", + "value": "1f00" + }, + { + "label": "x16.5", + "value": "2000" + }, + { + "label": "x17.0", + "value": "2100" + }, + { + "label": "x17.5", + "value": "2200" + }, + { + "label": "x18.0", + "value": "2300" + }, + { + "label": "x18.5", + "value": "2400" + }, + { + "label": "x19.0", + "value": "2500" + }, + { + "label": "x19.5", + "value": "2600" + }, + { + "label": "x20.0", + "value": "2700" + }, + { + "label": "x20.5", + "value": "2800" + }, + { + "label": "x21.0", + "value": "2900" + }, + { + "label": "x21.5", + "value": "2a00" + }, + { + "label": "x22.0", + "value": "2b00" + }, + { + "label": "x22.5", + "value": "2c00" + }, + { + "label": "x23.0", + "value": "2d00" + }, + { + "label": "x23.5", + "value": "2e00" + }, + { + "label": "x24.0", + "value": "2f00" + }, + { + "label": "x24.5", + "value": "3000" + }, + { + "label": "x25.0", + "value": "3100" + }, + { + "label": "x25.5", + "value": "3200" + }, + { + "label": "x26.0", + "value": "3300" + }, + { + "label": "x26.5", + "value": "3400" + }, + { + "label": "x27.0", + "value": "3500" + }, + { + "label": "x27.5", + "value": "3600" + }, + { + "label": "x28.0", + "value": "3700" + }, + { + "label": "x28.5", + "value": "3800" + }, + { + "label": "x29.0", + "value": "3900" + }, + { + "label": "x29.5", + "value": "3a00" + }, + { + "label": "x30.0", + "value": "3b00" + } + ] + } + ], + "key": "SYSTEM_PLLCCR", + "unused": "0000c0ec" + }, + { + "address": "4001e02a", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "PLLSTP", + "label": "PLL Stop Control", + "mask": "1", + "settings": [ + { + "label": "PLL is operating", + "value": "0" + }, + { + "label": "PLL is stopped.", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_PLLCR", + "unused": "000000fe" + }, + { + "address": "4001e032", + "default": "1", + "fields": [ + { + "hidden": false, + "init": "1", + "key": "MOSTP", + "label": "Main Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the main clock oscillator", + "value": "0" + }, + { + "label": "Stop the main clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e036", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCSTP", + "label": "HOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the HOCO clock ", + "value": "0" + }, + { + "label": "Stop the HOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_HOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e037", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "HCFRQ0", + "label": "HOCO Frequency Setting 0", + "mask": "3", + "settings": [ + { + "label": "16 MHz", + "value": "0" + }, + { + "label": "18 MHz", + "value": "1" + }, + { + "label": "20 MHz", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_HOCOCR2", + "unused": "000000fc" + }, + { + "address": "4001e038", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MCSTP", + "label": "MOCO Stop", + "mask": "1", + "settings": [ + { + "label": "MOCO clock is operating", + "value": "0" + }, + { + "label": "MOCO clock is stopped", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_MOCOCR", + "unused": "000000fe" + }, + { + "address": "4001e03e", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "CKOSEL", + "label": "Clock Out Source Select", + "mask": "7", + "settings": [ + { + "label": "HOCO (value after reset)", + "value": "0" + }, + { + "label": "MOCO", + "value": "1" + }, + { + "label": "LOCO", + "value": "2" + }, + { + "label": "MOSC", + "value": "3" + }, + { + "label": "SOSC", + "value": "4" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKODIV", + "label": "Clock Output Frequency Division Ratio", + "mask": "70", + "settings": [ + { + "label": "x1/1", + "value": "0" + }, + { + "label": "x1/2", + "value": "10" + }, + { + "label": "x1/4", + "value": "20" + }, + { + "label": "x1/8", + "value": "30" + }, + { + "label": "x1/16", + "value": "40" + }, + { + "label": "x1/32", + "value": "50" + }, + { + "label": "x1/64", + "value": "60" + }, + { + "label": "x1/128", + "value": "70" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "CKOEN", + "label": "Clock Out Enable", + "mask": "80", + "settings": [ + { + "label": "Disable clock out", + "value": "0" + }, + { + "label": "Enable clock out", + "value": "80" + } + ] + } + ], + "key": "SYSTEM_CKOCR", + "unused": "00000008" + }, + { + "address": "4001e0a0", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "OPCM", + "label": "Operating Power Control Mode Select", + "mask": "3", + "settings": [ + { + "label": "High-speed mode", + "value": "0" + }, + { + "label": "Low-speed mode", + "value": "3" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "OPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_OPCCR", + "unused": "000000ec" + }, + { + "address": "4001e0a2", + "default": "5", + "fields": [ + { + "hidden": false, + "init": "5", + "key": "MSTS", + "label": "Main Clock Oscillator Wait Time Setting", + "mask": "f", + "settings": [ + { + "label": "Wait time = 3 cycles (11.4 us)", + "value": "0" + }, + { + "label": "Wait time = 35 cycles (133.5 us)", + "value": "1" + }, + { + "label": "Wait time = 67 cycles (255.6 us)", + "value": "2" + }, + { + "label": "Wait time = 131 cycles (499.7 us)", + "value": "3" + }, + { + "label": "Wait time = 259 cycles (988.0 us)", + "value": "4" + }, + { + "label": "Wait time = 547 cycles (2086.6 us)", + "value": "5" + }, + { + "label": "Wait time = 1059 cycles (4039.8 us)", + "value": "6" + }, + { + "label": "Wait time = 2147 cycles (8190.2 us)", + "value": "7" + }, + { + "label": "Wait time = 4291 cycles (16368.9 us)", + "value": "8" + }, + { + "label": "Wait time = 8163 cycles (31139.4 us)", + "value": "9" + } + ] + } + ], + "key": "SYSTEM_MOSCWTCR", + "unused": "000000f0" + }, + { + "address": "4001e0aa", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOPCM", + "label": "Sub Operating Power Control Mode Select", + "mask": "1", + "settings": [ + { + "label": "Other than Subosc-speed mode", + "value": "0" + }, + { + "label": "Subosc-speed mode", + "value": "1" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "SOPCMTSF", + "label": "Operating Power Control Mode Transition Status Flag", + "mask": "10", + "settings": [ + { + "label": "Transition completed", + "value": "0" + }, + { + "label": "During transition", + "value": "10" + } + ] + } + ], + "key": "SYSTEM_SOPCCR", + "unused": "000000ee" + }, + { + "address": "4001e413", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "MODRV", + "label": "Main Clock Oscillator Drive Capability 0 Switching", + "mask": "30", + "settings": [ + { + "label": "20 MHz to 24 MHz", + "value": "0" + }, + { + "label": "16 MHz to 20 MHz", + "value": "10" + }, + { + "label": "8 MHz to 16 MHz", + "value": "20" + }, + { + "label": "8 MHz", + "value": "30" + } + ] + }, + { + "hidden": false, + "init": "0", + "key": "MOSEL", + "label": "Main Clock Oscillator Switching", + "mask": "40", + "settings": [ + { + "label": "Resonator", + "value": "0" + }, + { + "label": "External clock input", + "value": "40" + } + ] + } + ], + "key": "SYSTEM_MOMCR", + "unused": "0000008f" + }, + { + "address": "4001e480", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SOSTP", + "label": "Sub Clock Oscillator Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the sub-clock oscillator", + "value": "0" + }, + { + "label": "Stop the sub-clock oscillator", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_SOSCCR", + "unused": "000000fe" + }, + { + "address": "4001e481", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "SODRV", + "label": "Sub-Clock Oscillator Drive Capability Switching", + "mask": "2", + "settings": [ + { + "label": "Standard", + "value": "0" + }, + { + "label": "Low", + "value": "2" + } + ] + } + ], + "key": "SYSTEM_SOMCR", + "unused": "000000fd" + }, + { + "address": "4001e490", + "default": "0", + "fields": [ + { + "hidden": false, + "init": "0", + "key": "LCSTP", + "label": "LOCO Stop", + "mask": "1", + "settings": [ + { + "label": "Operate the LOCO clock", + "value": "0" + }, + { + "label": "Stop the LOCO clock", + "value": "1" + } + ] + } + ], + "key": "SYSTEM_LOCOCR", + "unused": "000000fe" + } + ], "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CFP", diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBG/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBG/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBG/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBG/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBM/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG2CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CBM/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFB/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFB/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFB/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFB/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFC/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFC/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFC/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFC/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFP/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFP/mcu.h index 70f0ff8e9..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFP/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AG3CFP/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBG/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBG/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBG/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBG/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBM/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH2CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CBM/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFB/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFB/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFB/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFB/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFC/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFC/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFC/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFC/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFP/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFP/mcu.h index ab9cb310e..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFP/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5AH3CFP/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBG/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBG/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBG/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBG/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBM/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF2CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CBM/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFB/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFB/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFB/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFB/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFC/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFC/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFC/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFC/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFP/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFP/mcu.h index dc22a2ae3..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFP/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BF3CFP/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBG/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBG/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBG/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBG/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBM/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG2CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CBM/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFB/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFB/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFB/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFB/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFC/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFC/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFC/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFC/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFP/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFP/mcu.h index 9da915c92..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFP/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BG3CFP/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBG/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBG/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBG/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBG/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBM/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH2CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CBM/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CBM/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CBM/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CBM/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFB/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFB/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFB/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFB/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFC/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFC/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFC/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFC/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFP/mcu.h b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFP/mcu.h index 66950aaf8..0c272829a 100644 --- a/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFP/mcu.h +++ b/ARM/gcc_clang/def/renesas/R7FA6M5BH3CFP/mcu.h @@ -49,14 +49,9 @@ extern "C" { /** @} */ /* End of group Configuration_of_CMSIS */ // Note: Changed for MikroE implementation. -// #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "ra6m5_core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ // Note: Changed for MikroE implementation. -// #include "system.h" /*!< R7FA6M5BH System */ -#include - -#define __I volatile // Note: Added for MikroE implementation. -#define __O __I // Note: Added for MikroE implementation. -#define __IO __I // Note: Added for MikroE implementation. +// #include "system.h" /*!< R7FA6M5BH System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -1912,25 +1907,6 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -5822,9 +5798,9 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure uint32_t : 12; __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ uint32_t : 5; __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ @@ -6018,12 +5994,12 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the * extended repeat area on the destination address. For details * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ } DMAMD_b; }; __IM uint16_t RESERVED1; @@ -6035,7 +6011,7 @@ typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure struct { __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ + * as the address update mode for transfer source or destination. */ } DMOFR_b; }; @@ -7565,11 +7541,11 @@ typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ uint16_t : 15; } FCACHEIV_b; }; @@ -8266,7 +8242,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -8279,7 +8255,7 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This * bit is only available in GPT324 to GPT329. In GPT320 to * GPT323, this bit is read as 0. The write value should be * 0.) */ @@ -12042,14 +12018,10 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12313,7 +12285,7 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure { uint32_t : 26; __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ } SFMCNT1_b; }; @@ -14536,11 +14508,11 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ uint8_t : 7; } ECC1STSEN_b; }; @@ -17089,7 +17061,7 @@ typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -19458,7 +19430,7 @@ typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ } INTENB0_b; @@ -21394,14 +21366,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbg/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbg/interrupts_mcu.h index cb1b7faaf..058541e2c 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbg/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbg/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG2CBG MCU specific interrupt per module definitions. +* @brief R7FA6M5AG2CBG MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG2CBG. +// No interrupt registers for R7FA6M5AG2CBG. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG2CBG. +// No interrupt bits for R7FA6M5AG2CBG. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbm/interrupts_mcu.h index 3bef21b27..ba8a58d80 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag2cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG2CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5AG2CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG2CBM. +// No interrupt registers for R7FA6M5AG2CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG2CBM. +// No interrupt bits for R7FA6M5AG2CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cbm/interrupts_mcu.h index bbb2f9532..6112d5f06 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG3CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5AG3CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG3CBM. +// No interrupt registers for R7FA6M5AG3CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG3CBM. +// No interrupt bits for R7FA6M5AG3CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfb/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfb/interrupts_mcu.h index 69427975e..64b39a963 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfb/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfb/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG3CFB MCU specific interrupt per module definitions. +* @brief R7FA6M5AG3CFB MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG3CFB. +// No interrupt registers for R7FA6M5AG3CFB. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG3CFB. +// No interrupt bits for R7FA6M5AG3CFB. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfc/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfc/interrupts_mcu.h index 3b31f7e53..c621995c2 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfc/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfc/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG3CFC MCU specific interrupt per module definitions. +* @brief R7FA6M5AG3CFC MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG3CFC. +// No interrupt registers for R7FA6M5AG3CFC. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG3CFC. +// No interrupt bits for R7FA6M5AG3CFC. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfp/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfp/interrupts_mcu.h index 6ab33f2a7..9bace0930 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfp/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ag3cfp/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AG3CFP MCU specific interrupt per module definitions. +* @brief R7FA6M5AG3CFP MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AG3CFP. +// No interrupt registers for R7FA6M5AG3CFP. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AG3CFP. +// No interrupt bits for R7FA6M5AG3CFP. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbg/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbg/interrupts_mcu.h index 30b77b809..4e129ddf6 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbg/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbg/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH2CBG MCU specific interrupt per module definitions. +* @brief R7FA6M5AH2CBG MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH2CBG. +// No interrupt registers for R7FA6M5AH2CBG. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH2CBG. +// No interrupt bits for R7FA6M5AH2CBG. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbm/interrupts_mcu.h index faafb4625..0e598d2f0 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah2cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH2CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5AH2CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH2CBM. +// No interrupt registers for R7FA6M5AH2CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH2CBM. +// No interrupt bits for R7FA6M5AH2CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cbm/interrupts_mcu.h index b7b647fd0..838ffbee3 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH3CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5AH3CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH3CBM. +// No interrupt registers for R7FA6M5AH3CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH3CBM. +// No interrupt bits for R7FA6M5AH3CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfb/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfb/interrupts_mcu.h index 4bda1c8fa..bda5f7578 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfb/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfb/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH3CFB MCU specific interrupt per module definitions. +* @brief R7FA6M5AH3CFB MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH3CFB. +// No interrupt registers for R7FA6M5AH3CFB. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH3CFB. +// No interrupt bits for R7FA6M5AH3CFB. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfc/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfc/interrupts_mcu.h index a12aa0946..5352bd8e0 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfc/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfc/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH3CFC MCU specific interrupt per module definitions. +* @brief R7FA6M5AH3CFC MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH3CFC. +// No interrupt registers for R7FA6M5AH3CFC. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH3CFC. +// No interrupt bits for R7FA6M5AH3CFC. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfp/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfp/interrupts_mcu.h index e3786f69a..eeff1be87 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfp/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5ah3cfp/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5AH3CFP MCU specific interrupt per module definitions. +* @brief R7FA6M5AH3CFP MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5AH3CFP. +// No interrupt registers for R7FA6M5AH3CFP. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5AH3CFP. +// No interrupt bits for R7FA6M5AH3CFP. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbg/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbg/interrupts_mcu.h index fbc39712d..871e57f68 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbg/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbg/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF2CBG MCU specific interrupt per module definitions. +* @brief R7FA6M5BF2CBG MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF2CBG. +// No interrupt registers for R7FA6M5BF2CBG. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF2CBG. +// No interrupt bits for R7FA6M5BF2CBG. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbm/interrupts_mcu.h index f7b0dca83..e60912352 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf2cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF2CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BF2CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF2CBM. +// No interrupt registers for R7FA6M5BF2CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF2CBM. +// No interrupt bits for R7FA6M5BF2CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cbm/interrupts_mcu.h index 96fc7089a..b112d9a06 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF3CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BF3CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF3CBM. +// No interrupt registers for R7FA6M5BF3CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF3CBM. +// No interrupt bits for R7FA6M5BF3CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfb/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfb/interrupts_mcu.h index 3f5fce34e..6f53bd4aa 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfb/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfb/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF3CFB MCU specific interrupt per module definitions. +* @brief R7FA6M5BF3CFB MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF3CFB. +// No interrupt registers for R7FA6M5BF3CFB. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF3CFB. +// No interrupt bits for R7FA6M5BF3CFB. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfc/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfc/interrupts_mcu.h index ac65f4fcb..f01b4ae03 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfc/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfc/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF3CFC MCU specific interrupt per module definitions. +* @brief R7FA6M5BF3CFC MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF3CFC. +// No interrupt registers for R7FA6M5BF3CFC. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF3CFC. +// No interrupt bits for R7FA6M5BF3CFC. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfp/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfp/interrupts_mcu.h index 7aeda9996..a799322a3 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfp/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bf3cfp/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BF3CFP MCU specific interrupt per module definitions. +* @brief R7FA6M5BF3CFP MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BF3CFP. +// No interrupt registers for R7FA6M5BF3CFP. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BF3CFP. +// No interrupt bits for R7FA6M5BF3CFP. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbg/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbg/interrupts_mcu.h index 3bea62045..924e7b041 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbg/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbg/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG2CBG MCU specific interrupt per module definitions. +* @brief R7FA6M5BG2CBG MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG2CBG. +// No interrupt registers for R7FA6M5BG2CBG. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG2CBG. +// No interrupt bits for R7FA6M5BG2CBG. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbm/interrupts_mcu.h index 2b7e520fa..4e512e7fd 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg2cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG2CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BG2CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG2CBM. +// No interrupt registers for R7FA6M5BG2CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG2CBM. +// No interrupt bits for R7FA6M5BG2CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cbm/interrupts_mcu.h index 0f272d227..2e4356d70 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG3CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BG3CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG3CBM. +// No interrupt registers for R7FA6M5BG3CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG3CBM. +// No interrupt bits for R7FA6M5BG3CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfb/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfb/interrupts_mcu.h index 7546f4b46..42495b857 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfb/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfb/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG3CFB MCU specific interrupt per module definitions. +* @brief R7FA6M5BG3CFB MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG3CFB. +// No interrupt registers for R7FA6M5BG3CFB. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG3CFB. +// No interrupt bits for R7FA6M5BG3CFB. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfc/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfc/interrupts_mcu.h index 71d2517a6..503ba5367 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfc/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfc/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG3CFC MCU specific interrupt per module definitions. +* @brief R7FA6M5BG3CFC MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG3CFC. +// No interrupt registers for R7FA6M5BG3CFC. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG3CFC. +// No interrupt bits for R7FA6M5BG3CFC. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfp/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfp/interrupts_mcu.h index 368b6332a..1557079ec 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfp/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bg3cfp/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BG3CFP MCU specific interrupt per module definitions. +* @brief R7FA6M5BG3CFP MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BG3CFP. +// No interrupt registers for R7FA6M5BG3CFP. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BG3CFP. +// No interrupt bits for R7FA6M5BG3CFP. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbg/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbg/interrupts_mcu.h index b6322485a..6634a675b 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbg/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbg/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH2CBG MCU specific interrupt per module definitions. +* @brief R7FA6M5BH2CBG MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH2CBG. +// No interrupt registers for R7FA6M5BH2CBG. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH2CBG. +// No interrupt bits for R7FA6M5BH2CBG. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbm/interrupts_mcu.h index 7265c702a..268e38e3a 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh2cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH2CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BH2CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH2CBM. +// No interrupt registers for R7FA6M5BH2CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH2CBM. +// No interrupt bits for R7FA6M5BH2CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cbm/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cbm/interrupts_mcu.h index 0597c5993..2cd9f8432 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cbm/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cbm/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH3CBM MCU specific interrupt per module definitions. +* @brief R7FA6M5BH3CBM MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH3CBM. +// No interrupt registers for R7FA6M5BH3CBM. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH3CBM. +// No interrupt bits for R7FA6M5BH3CBM. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfb/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfb/interrupts_mcu.h index 594f3974e..d16467c5e 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfb/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfb/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH3CFB MCU specific interrupt per module definitions. +* @brief R7FA6M5BH3CFB MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH3CFB. +// No interrupt registers for R7FA6M5BH3CFB. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH3CFB. +// No interrupt bits for R7FA6M5BH3CFB. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfc/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfc/interrupts_mcu.h index a1a351d90..623f7af91 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfc/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfc/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH3CFC MCU specific interrupt per module definitions. +* @brief R7FA6M5BH3CFC MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH3CFC. +// No interrupt registers for R7FA6M5BH3CFC. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH3CFC. +// No interrupt bits for R7FA6M5BH3CFC. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfp/interrupts_mcu.h b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfp/interrupts_mcu.h index 9580274a3..ebd50c070 100644 --- a/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfp/interrupts_mcu.h +++ b/ARM/gcc_clang/interrupts/include/interrupts_mcu/r7fa6m5bh3cfp/interrupts_mcu.h @@ -28,8 +28,8 @@ ** included in all copies or substantial portions of the Software. ** ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, ** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT ** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE @@ -38,24 +38,13 @@ ****************************************************************************/ /*! * @file interrupts_mcu.h -* @brief extracted_R7FA6M5BH3CFP MCU specific interrupt per module definitions. +* @brief R7FA6M5BH3CFP MCU specific interrupt per module definitions. */ #ifndef _INTERRUPTS_MCU_H_ #define _INTERRUPTS_MCU_H_ // Interrupt table -static const int INTERRUPTS_RESET = 1; -static const int INTERRUPTS_NMI = 2; -static const int INTERRUPTS_HARDFAULT = 3; -static const int INTERRUPTS_MEMMANAGE = 4; -static const int INTERRUPTS_BUSFAULT = 5; -static const int INTERRUPTS_USAGEFAULT = 6; -static const int INTERRUPTS_SECUREFAULT = 7; -static const int INTERRUPTS_SVC = 11; -static const int INTERRUPTS_DEBUGMON = 12; -static const int INTERRUPTS_PENDSV = 14; -static const int INTERRUPTS_SYSTICK = 15; static const int INTERRUPTS_IELSR0 = 16; static const int INTERRUPTS_IELSR1 = 17; static const int INTERRUPTS_IELSR2 = 18; @@ -155,11 +144,11 @@ static const int INTERRUPTS_IELSR95 = 111; // EOF Interrupt table // Interrupt addresses -// No interrupt registers for extracted_R7FA6M5BH3CFP. +// No interrupt registers for R7FA6M5BH3CFP. // EOF Interrupt addresses // Interrupt register bit values -// No interrupt bits for extracted_R7FA6M5BH3CFP. +// No interrupt bits for R7FA6M5BH3CFP. // EOF Interrupt register bit values #endif // _INTERRUPTS_MCU_H_ diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbg.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbg.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbm.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag2cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cbm.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfb.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfb.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfc.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfc.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfp.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ag3cfp.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbg.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbg.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbm.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah2cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cbm.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfb.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfb.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfc.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfc.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfp.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5ah3cfp.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbg.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbg.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbm.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf2cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cbm.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfb.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfb.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfc.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfc.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfp.ld index 30c553b68..e39f60c86 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bf3cfp.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbg.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbg.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbm.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg2cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cbm.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfb.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfb.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfc.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfc.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfp.ld index c0b250252..070ab01da 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bg3cfp.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbg.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbg.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbm.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh2cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cbm.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cbm.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfb.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfb.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfc.ld index a2b356deb..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfc.ld @@ -1,838 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ -/* generated memory regions file - do not edit */ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfp.ld index 3121fa13b..8a1ce765a 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/clang-llvm/r7fa6m5bh3cfp.ld @@ -1,839 +1,736 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } -/* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* -GROUP(libgcc.a libc.a libm.a) -*/ - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ +/* code entry point...need to define to keep crt0 _start out */ ENTRY(Reset_Handler) + SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - __etext = LOADADDR(.data); - - /* - * Needs to be in its own segment with the PLT entries first - * so that the linker will compute the offsets to those - * entries correctly. - */ - .got : { - *(.got.plt) - *(.got) - } > FLASH - - .tdata : { - *(.tdata .tdata.* .gnu.linkonce.td.*) - /* Dummy byte to work with LLVM linker bug. Without this, the ALIGN for this section will carry through and affect the next if this section ends up empty */ - BYTE(0xFF); - PROVIDE(__tdata_end = .); - } > RAM AT > FLASH - PROVIDE( __tls_base = ADDR(.tdata)); - PROVIDE( __tdata_start = ADDR(.tdata)); - PROVIDE( __tdata_source = LOADADDR(.tdata) ); - PROVIDE( __tdata_size = SIZEOF(.tdata) ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); - - .tbss (NOLOAD): - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) - *(.tcommon) - PROVIDE( __tls_end = . ); - PROVIDE( __tbss_end = . ); - } > RAM AT > RAM - PROVIDE( __tbss_start = ADDR(.tbss)); - PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); - PROVIDE( __tbss_size = SIZEOF(.tbss) ); - PROVIDE( __tls_size = __tls_end - __tls_base ); - PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); - PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); - PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); - - . = .; - __dtcm_data_pre_location = LOADADDR(.tdata) + SIZEOF(.tdata); + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ ALIGN(.,32) (NOLOAD) : + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Initialized thread local storage */ + __ram_tdata$$ : + { + __ram_tdata$$Base = . ;__ram_tdata$$Load = LOADADDR(__ram_tdata$$) ; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __ram_tdata$$Limit = . ; + } > RAM AT > FLASH + /* Zeroed thread local storage */ + __ram_tbss$$ (NOLOAD) : + { + __ram_tbss$$Base = . ; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + __ram_tbss$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ ALIGN(.,8) (NOLOAD) : + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; - - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF +PROVIDE( __tls_base = ADDR(__ram_tdata$$) ); +PROVIDE( __tdata_source = LOADADDR(__ram_tdata$$) ); +PROVIDE( __tdata_size = SIZEOF(__ram_tdata$$) ); +PROVIDE( __tbss_offset = ADDR(__ram_tbss$$) - ADDR(__ram_tdata$$) ); +PROVIDE( __tbss_size = SIZEOF(__ram_tbss$$) ); +PROVIDE( __arm32_tls_tcb_offset = 8 ); - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbg.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbg.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbm.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag2cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cbm.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfb.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfb.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfc.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfc.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfp.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ag3cfp.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbg.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbg.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbm.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah2cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cbm.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfb.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfb.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfc.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfc.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfp.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5ah3cfp.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbg.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbg.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbm.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf2cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cbm.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfb.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfb.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfc.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfc.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfp.ld index 85bf21144..d68cfe04f 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bf3cfp.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x100000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbg.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbg.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbm.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg2cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cbm.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfb.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfb.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfc.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfc.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfp.ld index 7b3224411..404446b85 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bg3cfp.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x180000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00180000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbg.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbg.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbg.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbg.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbm.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh2cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cbm.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cbm.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cbm.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cbm.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfb.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfb.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfb.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfb.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfc.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfc.ld index 5eb643163..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfc.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfc.ld @@ -1,800 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ -/* generated memory regions file - do not edit */ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfp.ld b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfp.ld index 5996457cd..0f45b13f7 100644 --- a/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfp.ld +++ b/ARM/gcc_clang/linker_scripts/renesas/gcc_arm_none_eabi/r7fa6m5bh3cfp.ld @@ -1,801 +1,713 @@ -/* - Linker File for Renesas FSP -*/ - -/* Note: Changed for MikroE implementation. */ -/* -INCLUDE memory_regions.ld -*/ -/* Note: Added for MikroE implementation. */ - - /* generated memory regions file - do not edit */ - RAM_START = 0x20000000; - RAM_LENGTH = 0x80000; - FLASH_START = 0x00000000; - FLASH_LENGTH = 0x200000; - DATA_FLASH_START = 0x08000000; - DATA_FLASH_LENGTH = 0x2000; - OPTION_SETTING_START = 0x0100A100; - OPTION_SETTING_LENGTH = 0x100; - OPTION_SETTING_S_START = 0x0100A200; - OPTION_SETTING_S_LENGTH = 0x100; - ID_CODE_START = 0x00000000; - ID_CODE_LENGTH = 0x0; - SDRAM_START = 0x80010000; - SDRAM_LENGTH = 0x0; - QSPI_FLASH_START = 0x60000000; - QSPI_FLASH_LENGTH = 0x4000000; - OSPI_DEVICE_0_START = 0x68000000; - OSPI_DEVICE_0_LENGTH = 0x8000000; - OSPI_DEVICE_1_START = 0x70000000; - OSPI_DEVICE_1_LENGTH = 0x10000000; -/* EOF Note. */ - -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_IMAGE_START_FROM_MMF_REGION = DEFINED(BOOT_IMAGE_FROM_MMF_REGION) ? BOOT_IMAGE_FROM_MMF_REGION : 0; -__bl_MEMORY_MIRROR_REGION_START = DEFINED(MMF_REGION_START_ADDR) ? MMF_REGION_START_ADDR : 0; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_IMAGE_START_FROM_MMF_REGION = !DEFINED(FLASH_IMAGE_START_FROM_MMF_REGION) ? 0 : FLASH_IMAGE_START_FROM_MMF_REGION; -MEMORY_MIRROR_REGION_START = !DEFINED(MEMORY_MIRROR_REGION_START) ? 0 : MEMORY_MIRROR_REGION_START; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START_FROM_MMF_REGION == 1 ? MEMORY_MIRROR_REGION_START : FLASH_IMAGE_START; - -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; -OPTION_SETTING_SAS_SIZE = 0x34; -OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : - OPTION_SETTING_LENGTH == 0 ? 0 : - OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; - -/* Define memory regions. */ + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x00080000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x00200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x00002000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x04000000; + OSPI0_CS0_START = 0x68000000; + OSPI0_CS0_LENGTH = 0x08000000; + OSPI0_CS1_START = 0x70000000; + OSPI0_CS1_LENGTH = 0x10000000; + OPTION_SETTING_OFS0_START = 0x0100a100; + OPTION_SETTING_OFS0_LENGTH = 0x00000004; + OPTION_SETTING_DUALSEL_START = 0x0100a110; + OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; + OPTION_SETTING_OFS1_START = 0x0100a180; + OPTION_SETTING_OFS1_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_START = 0x0100a190; + OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_START = 0x0100a1c0; + OPTION_SETTING_BPS_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_START = 0x0100a1e0; + OPTION_SETTING_PBPS_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEC_START = 0x0100a200; + OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEC_START = 0x0100a210; + OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEC_START = 0x0100a240; + OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_PBPS_SEC_START = 0x0100a260; + OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; + OPTION_SETTING_OFS1_SEL_START = 0x0100a280; + OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BANKSEL_SEL_START = 0x0100a290; + OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; + OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; + OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; MEMORY { - ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH } +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) /* Library configurations */ -/* Note: Changed for MikroE implementation. */ -/* GROUP(libgcc.a libc.a libm.a) -*/ -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) SECTIONS { - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* Some devices have a gap of code flash between the vector table and ROM Registers. - * The flash gap section allows applications to place code and data in this section. */ - *(.flash_gap*) - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - . = .; - __itcm_data_pre_location = .; - - /* Initialized ITCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .itcm_data : ALIGN(16) - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start = .; - - KEEP(*(.itcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* All ITCM data end */ - __itcm_data_end = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); - } > ITCM AT > FLASH = 0x00 - - /* Addresses exported for ITCM initialization. */ - __itcm_data_init_start = LOADADDR(.itcm_data); - __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); - - ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") - - /* Restore location counter. */ - /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ - . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; - - __exidx_start = .; - /DISCARD/ : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - . = .; - __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); - - /* Initialized DTCM data. */ - /* Aligned to FCACHE2 for RA8. */ - .dtcm_data : ALIGN(16) - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start = .; + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from qspi_flash */ + __ospi0_cs0_from_qspi_flash$$ : + { + __ospi0_cs0_from_qspi_flash$$Base = . ;__ospi0_cs0_from_qspi_flash$$Load = LOADADDR(__ospi0_cs0_from_qspi_flash$$) ; + /* section.ospi0_cs0.from_qspi_flash */ + *(.ospi0_cs0_from_qspi_flash) + /* section.ospi0_cs0.code_from_qspi_flash */ + *(.ospi0_cs0_code_from_qspi_flash) + __ospi0_cs0_from_qspi_flash$$Limit = . ; + } > OSPI0_CS0 AT > QSPI_FLASH + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : + { + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = . ; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = . ; + + } > RAM + .ram.flat_nsc ALIGN(.,8192) : + { + __ddsc_RAM_NSC = . ; + + } > RAM + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + } > FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + __exidx_end = . ; + } > FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + .flash.flat_nsc ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_NSC = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Register Select */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Register Select */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL - KEEP(*(.dtcm_data*)) - - /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ - . = ALIGN(8); - - /* Initialized DTCM data end */ - __dtcm_data_end = .; - } > DTCM AT > FLASH = 0x00 - - . = __dtcm_data_end; - /* Uninitialized DTCM data. */ - /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ - .dtcm_bss ALIGN(8) (NOLOAD) : - { - /* Uninitialized DTCM data start */ - __dtcm_bss_start = .; - - KEEP(*(.dtcm_bss*)) - - /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ - . = ALIGN(8); - - /* Uninitialized DTCM data end */ - __dtcm_bss_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); - } > DTCM - - /* Addresses exported for DTCM initialization. */ - __dtcm_data_init_start = LOADADDR(.dtcm_data); - __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - - ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") - ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") - ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") - ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") - ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") - ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") - ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") - - /* Restore location counter. */ - /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ - /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ - . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; - - /* TrustZone Secure Gateway Stubs Section */ - - /* Store location counter for SPI non-retentive sections. */ - sgstubs_pre_location = .; - - /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = sgstubs_pre_location; - .qspi_non_retentive : AT(__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); - .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); - .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); +} - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} \ No newline at end of file diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbg.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbg.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbg.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbg.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag2cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfb.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfb.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfb.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfb.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfc.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfc.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfc.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfc.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfp.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfp.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfp.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ag3cfp.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbg.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbg.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbg.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbg.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah2cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfb.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfb.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfb.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfb.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfc.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfc.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfc.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfc.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfp.c b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfp.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfp.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5ah3cfp.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbg.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbg.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbg.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbg.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf2cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfb.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfb.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfb.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfb.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfc.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfc.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfc.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfc.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfp.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfp.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfp.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bf3cfp.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbg.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbg.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbg.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbg.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg2cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfb.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfb.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfb.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfb.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfc.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfc.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfc.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfc.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfp.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfp.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfp.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bg3cfp.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbg.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbg.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbg.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbg.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh2cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cbm.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cbm.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cbm.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cbm.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfb.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfb.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfb.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfb.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfc.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfc.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfc.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfc.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfp.c b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfp.c index c10849597..5a06b0ad8 100644 --- a/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfp.c +++ b/ARM/gcc_clang/startup/renesas/r7fa6m5bh3cfp.c @@ -37,9 +37,8 @@ #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED #define BSP_WEAK_REFERENCE __attribute__((weak)) #define BSP_STACK_ALIGNMENT (8) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -// EOF Note. +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) /*********************************************************************************************************************** * Macro definitions @@ -71,7 +70,7 @@ int32_t main(void); /*******************************************************************************************************************//** * MCU starts executing here out of reset. Main stack pointer is set up already. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Reset_Handler (void) +void Reset_Handler (void) { /* Initialize system using BSP. */ SystemInit(); @@ -88,7 +87,7 @@ BSP_SECTION_FLASH_GAP void Reset_Handler (void) /*******************************************************************************************************************//** * Default exception handler. **********************************************************************************************************************/ -BSP_SECTION_FLASH_GAP void Default_Handler (void) +void Default_Handler (void) { /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status @@ -98,14 +97,12 @@ BSP_SECTION_FLASH_GAP void Default_Handler (void) } /* Main stack */ -static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) -BSP_PLACE_IN_SECTION(BSP_SECTION_STACK); +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); /* Heap */ +// Note: Added for MikroE implementation. #if (BSP_CFG_HEAP_BYTES > 0) - -BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ - BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); + BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); #endif /* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/m-profile/armv8m_mpu.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/ra6m5_core_cm33.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/ra6m5_core_cm33.h new file mode 100644 index 000000000..a2beb4323 --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/ra6m5_core_cm33.h @@ -0,0 +1,3262 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +// Note: Added for MikroE implementation. +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/m-profile/armv8m_mpu.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/ra6m5_core_cm33.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/ra6m5_core_cm33.h new file mode 100644 index 000000000..a2beb4323 --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/ra6m5_core_cm33.h @@ -0,0 +1,3262 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +// Note: Added for MikroE implementation. +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/m-profile/armv8m_mpu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/ra6m5_core_cm33.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/ra6m5_core_cm33.h new file mode 100644 index 000000000..a2beb4323 --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/ra6m5_core_cm33.h @@ -0,0 +1,3262 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +// Note: Added for MikroE implementation. +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/m-profile/armv8m_mpu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/ra6m5_core_cm33.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/ra6m5_core_cm33.h new file mode 100644 index 000000000..a2beb4323 --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/ra6m5_core_cm33.h @@ -0,0 +1,3262 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +// Note: Added for MikroE implementation. +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/m-profile/armv8m_mpu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/ra6m5_core_cm33.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/ra6m5_core_cm33.h new file mode 100644 index 000000000..a2beb4323 --- /dev/null +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/ra6m5_core_cm33.h @@ -0,0 +1,3262 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +// Note: Added for MikroE implementation. +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ From 078f70dc86a477565b26830d8b4a7e5127bc9573 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Tue, 7 Oct 2025 12:30:11 +0200 Subject: [PATCH 2/8] Added led blinking test for RA6M5 EK --- tests/renesas/ek_ra6m5/main.c | 169 ++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 tests/renesas/ek_ra6m5/main.c diff --git a/tests/renesas/ek_ra6m5/main.c b/tests/renesas/ek_ra6m5/main.c new file mode 100644 index 000000000..93d4bddf4 --- /dev/null +++ b/tests/renesas/ek_ra6m5/main.c @@ -0,0 +1,169 @@ +/** + * @file main.c + * @brief Main function for RA6M5-LED application. + */ + +/** + * Any initialization code needed for MCU to function properly. + * Do not remove this line or clock might not be set correctly. + */ +#ifdef PREINIT_SUPPORTED +#include "preinit.h" +#endif + +#include "mcu.h" + +// MIKROBUS_AN P000 +// MIKROBUS_RST P303 +// MIKROBUS_CS P205 +// MIKROBUS_SCK P204 +// MIKROBUS_CIPO P202 +// MIKROBUS_COPI P203 +// MIKROBUS_PWM P111 +// MIKROBUS_INT P409 +// MIKROBUS_RX P614 +// MIKROBUS_TX P613 +// MIKROBUS_SCL P512 +// MIKROBUS_SDA P511 + +// LD1 P006 +// LD2 P007 +// LD3 P008 + +// TODO - change cycle delay here as desired. +#define DEFINED_CYCLES (50000) + +void pin_toggle(volatile uint16_t *reg, uint16_t mask) +{ + // Change the state of board LEDs + R_PORT0->PODR_b.PODR6 ^= 1; + R_PORT0->PODR_b.PODR7 ^= 1; + R_PORT0->PODR_b.PODR8 ^= 1; + + // Read-modify-write toggle + *reg ^= mask; + // for (uint32_t i = 0; i < DEFINED_CYCLES; i++) asm("NOP"); + Delay_ms(1000); + *reg ^= mask; +} + +int main(void) +{ + /* Do not remove this line or clock might not be set correctly. */ + #ifdef PREINIT_SUPPORTED + preinit(); + #endif + + // Set AN pin as output low + R_PORT0->PDR_b.PDR0 = 1; + R_PORT0->PODR_b.PODR0 = 0; + + // Set RST pin as output low + R_PORT3->PDR_b.PDR3 = 1; + R_PORT3->PODR_b.PODR3 = 0; + + // Set CS pin as output low + R_PORT2->PDR_b.PDR5 = 1; + R_PORT2->PODR_b.PODR5 = 0; + + // Set SCK pin as output low + R_PORT2->PDR_b.PDR4 = 1; + R_PORT2->PODR_b.PODR4 = 0; + + // Set CIPO pin as output low + R_PORT2->PDR_b.PDR2 = 1; + R_PORT2->PODR_b.PODR2 = 0; + + // Set COPI pin as output low + R_PORT2->PDR_b.PDR3 = 1; + R_PORT2->PODR_b.PODR3 = 0; + + // Set PWM pin as output low + R_PORT1->PDR_b.PDR11 = 1; + R_PORT1->PODR_b.PODR11 = 0; + + // Set INT pin as output low + R_PORT4->PDR_b.PDR9 = 1; + R_PORT4->PODR_b.PODR9 = 0; + + // Set RX pin as output low + R_PORT6->PDR_b.PDR14 = 1; + R_PORT6->PODR_b.PODR14 = 0; + + // Set TX pin as output low + R_PORT6->PDR_b.PDR13 = 1; + R_PORT6->PODR_b.PODR13 = 0; + + // Set SCL pin as output low + R_PORT5->PDR_b.PDR12 = 1; + R_PORT5->PODR_b.PODR12 = 0; + + // Set SDA pin as output low + R_PORT5->PDR_b.PDR11 = 1; + R_PORT5->PODR_b.PODR11 = 0; + + // Set LD1 pin as output low + R_PORT0->PDR_b.PDR6 = 1; + R_PORT0->PODR_b.PODR6 = 0; + + // Set LD2 pin as output high + R_PORT0->PDR_b.PDR7 = 1; + R_PORT0->PODR_b.PODR7 = 1; + + // Set LD3 pin as output high + R_PORT0->PDR_b.PDR8 = 1; + R_PORT0->PODR_b.PODR8 = 1; + + while (1) + { + // Toggle MIKROBUS_AN + // R_PORT0->PODR_b.PODR0 + pin_toggle((volatile uint16_t*)&R_PORT0->PODR_b, 0x0001); + + // Toggle MIKROBUS_RST + // R_PORT3->PODR_b.PODR3 + pin_toggle((volatile uint16_t*)&R_PORT3->PODR_b, 0x0008); + + // Toggle MIKROBUS_CS + // R_PORT2->PODR_b.PODR5 + pin_toggle((volatile uint16_t*)&R_PORT2->PODR_b, 0x0020); + + // Toggle MIKROBUS_SCK + // R_PORT2->PODR_b.PODR4 + pin_toggle((volatile uint16_t*)&R_PORT2->PODR_b, 0x0010); + + // Toggle MIKROBUS_CIPO + // R_PORT2->PODR_b.PODR2 + pin_toggle((volatile uint16_t*)&R_PORT2->PODR_b, 0x0004); + + // Toggle MIKROBUS_COPI + // R_PORT2->PODR_b.PODR3 + pin_toggle((volatile uint16_t*)&R_PORT2->PODR_b, 0x0008); + + // Toggle MIKROBUS_PWM + // R_PORT1->PODR_b.PODR11 + pin_toggle((volatile uint16_t*)&R_PORT1->PODR_b, 0x0800); + + // Toggle MIKROBUS_INT + // R_PORT4->PODR_b.PODR9 + pin_toggle((volatile uint16_t*)&R_PORT4->PODR_b, 0x0200); + + // Toggle MIKROBUS_RX + // R_PORT6->PODR_b.PODR14 + pin_toggle((volatile uint16_t*)&R_PORT6->PODR_b, 0x4000); + + // Toggle MIKROBUS_TX + // R_PORT6->PODR_b.PODR13 + pin_toggle((volatile uint16_t*)&R_PORT6->PODR_b, 0x2000); + + // Toggle MIKROBUS_SCL + // R_PORT5->PODR_b.PODR12 + pin_toggle((volatile uint16_t*)&R_PORT5->PODR_b, 0x1000); + + // Toggle MIKROBUS_SDA + // R_PORT5->PODR_b.PODR11 + pin_toggle((volatile uint16_t*)&R_PORT5->PODR_b, 0x0800); + } + + return 0; +} \ No newline at end of file From 6cf51b116e8780be5aa7a6e4cc312f5652314ccb Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Tue, 7 Oct 2025 12:46:58 +0200 Subject: [PATCH 3/8] Added HOCOWTCR to clock file --- ARM/gcc_clang/def/R7FA6M5AG2CBG.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AG2CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AG3CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AG3CFB.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AG3CFC.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AG3CFP.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH2CBG.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH2CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH3CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH3CFB.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH3CFC.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5AH3CFP.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF2CBG.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF2CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF3CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF3CFB.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF3CFC.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BF3CFP.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG2CBG.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG2CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG3CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG3CFB.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG3CFC.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BG3CFP.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH2CBG.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH2CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH3CBM.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH3CFB.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH3CFC.json | 57 ++++++++++++++++++++++++++-- ARM/gcc_clang/def/R7FA6M5BH3CFP.json | 57 ++++++++++++++++++++++++++-- 30 files changed, 1590 insertions(+), 120 deletions(-) diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json index 7a8a529c1..ee137e824 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json index 882b989eb..98b54161f 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json index 3b378a1aa..5c34b93c7 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json index cb8aeab52..af8dfded2 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json index 1eaa8e708..98a6205d1 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json index f9a070b57..ef9cfc75a 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json index ddf06eb1d..226dbbc15 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json index 1c5bd28aa..120d0fcd5 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json index 7e1e25f66..6aed564eb 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json index 04744e96c..41bdc5f99 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json index fbdb778b9..f0faa4cee 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json index 322f3725f..ad2fccd19 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json index f84cb048c..e833cc17f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json index 07d0c5142..367da58d5 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json index c4bd716be..84e9f0522 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json index 79c83857a..b66c79525 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json index 52d26b341..89189f287 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json index 8a1fbf048..7232aff04 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json index 03190b8ec..551e43253 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json index 97e05be94..25e56e689 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json index dccbb18ef..afcc9be5b 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json index d2c72f36a..e1e4513a0 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json index 9fc3c4410..285e7737a 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json index 57bb61762..4a089b7c0 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json index 6ac128f62..81f0dfd15 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json index d37bc3b07..84d2001e9 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json index 97752258b..120b7f18f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json index a7517fe99..5f7d25a25 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json index c4699fbfe..da214187d 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json index 64f69cca8..667b08174 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json @@ -603,12 +603,12 @@ "unused": "000000fe" }, { - "address": "4001e037", - "default": "0", + "address": "4001e000", + "default": "00000000", "fields": [ { "hidden": false, - "init": "0", + "init": "2", "key": "HCFRQ0", "label": "HOCO Frequency Setting 0", "mask": "3", @@ -629,7 +629,56 @@ } ], "key": "SYSTEM_HOCOCR2", - "unused": "000000fc" + "unused": "fffffffc" + }, + { + "address": "4001e0a5", + "default": "00000002", + "fields": [ + { + "hidden": false, + "init": "7", + "key": "HSTS", + "label": "HOCO Wait Time Setting", + "mask": "7", + "settings": [ + { + "label": "Wait time (s) = 3 / fLOCO", + "value": "0" + }, + { + "label": "Wait time (s) = 4 / fLOCO", + "value": "1" + }, + { + "label": "Wait time (s) = 5 / fLOCO", + "value": "2" + }, + { + "label": "Wait time (s) = 6 / fLOCO", + "value": "3" + }, + { + "label": "Wait time (s) = 7 / fLOCO", + "value": "4" + }, + { + "label": "Wait time (s) = 8 / fLOCO", + "value": "5" + }, + { + "label": "Wait time (s) = 9 / fLOCO", + "value": "6" + }, + { + "label": "Wait time (s) = 10 / fLOCO", + "value": "7" + } + ] + } + ], + "key": "SYSTEM_HOCOWTCR", + "unused": "fffffff8" }, { "address": "4001e038", From 8c13a466704ff11ff73761f983815a4358017cc9 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 8 Oct 2025 09:49:36 +0200 Subject: [PATCH 4/8] Removed unused thirdparty files for RA6M5 --- .../ra6m5ag/thirdparty/ra6m5ag/R7FA6M5BH.h | 29959 ---------------- .../ra6m5ag/thirdparty/ra6m5ag/board_cfg.h | 13 - .../ra6m5ag/thirdparty/ra6m5ag/board_sdram.h | 32 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_api.h | 101 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_cfg.h | 61 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_clocks.h | 1727 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_common.h | 623 - .../thirdparty/ra6m5ag/bsp_compiler_support.h | 109 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_delay.h | 73 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_elc.h | 378 - .../thirdparty/ra6m5ag/bsp_exceptions.h | 44 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_feature.h | 588 - .../thirdparty/ra6m5ag/bsp_group_irq.h | 69 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_guard.h | 32 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_io.h | 465 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_irq.h | 238 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_macl.h | 164 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_api.h | 56 - .../thirdparty/ra6m5ag/bsp_mcu_device_cfg.h | 5 - .../ra6m5ag/bsp_mcu_device_pn_cfg.h | 11 - .../thirdparty/ra6m5ag/bsp_mcu_family_cfg.h | 394 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_info.h | 44 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_mmf.h | 141 - .../thirdparty/ra6m5ag/bsp_module_stop.h | 371 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_pin_cfg.h | 16 - .../ra6m5ag/bsp_register_protection.h | 60 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_sdram.h | 37 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_security.h | 33 - .../ra6m5ag/thirdparty/ra6m5ag/bsp_tfu.h | 218 - .../thirdparty/ra6m5ag/fsp_common_api.h | 380 - .../ra6m5ag/thirdparty/ra6m5ag/fsp_features.h | 297 - .../ra6m5ag/thirdparty/ra6m5ag/fsp_version.h | 76 - .../thirdparty/ra6m5ag/instance/r_ioport.h | 522 - .../ra6m5ag/periph/bsp_peripheral.h | 211 - .../ra6m5ag/thirdparty/ra6m5ag/r_ioport_api.h | 192 - .../ra6m5ag/thirdparty/ra6m5ag/r_ioport_cfg.h | 13 - .../ra6m5ag/thirdparty/ra6m5ag/renesas.h | 154 - .../ra6m5ah/thirdparty/ra6m5ah/R7FA6M5BH.h | 29959 ---------------- .../ra6m5ah/thirdparty/ra6m5ah/board_cfg.h | 13 - .../ra6m5ah/thirdparty/ra6m5ah/board_sdram.h | 32 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_api.h | 101 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_cfg.h | 61 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_clocks.h | 1727 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_common.h | 623 - .../thirdparty/ra6m5ah/bsp_compiler_support.h | 109 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_delay.h | 73 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_elc.h | 378 - .../thirdparty/ra6m5ah/bsp_exceptions.h | 44 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_feature.h | 588 - .../thirdparty/ra6m5ah/bsp_group_irq.h | 69 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_guard.h | 32 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_io.h | 465 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_irq.h | 238 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_macl.h | 164 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_api.h | 56 - .../thirdparty/ra6m5ah/bsp_mcu_device_cfg.h | 5 - .../ra6m5ah/bsp_mcu_device_pn_cfg.h | 11 - .../thirdparty/ra6m5ah/bsp_mcu_family_cfg.h | 394 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_info.h | 44 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_mmf.h | 141 - .../thirdparty/ra6m5ah/bsp_module_stop.h | 371 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_pin_cfg.h | 16 - .../ra6m5ah/bsp_register_protection.h | 60 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_sdram.h | 37 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_security.h | 33 - .../ra6m5ah/thirdparty/ra6m5ah/bsp_tfu.h | 218 - .../thirdparty/ra6m5ah/fsp_common_api.h | 380 - .../ra6m5ah/thirdparty/ra6m5ah/fsp_features.h | 297 - .../ra6m5ah/thirdparty/ra6m5ah/fsp_version.h | 76 - .../thirdparty/ra6m5ah/instance/r_ioport.h | 522 - .../ra6m5ah/periph/bsp_peripheral.h | 211 - .../ra6m5ah/thirdparty/ra6m5ah/r_ioport_api.h | 192 - .../ra6m5ah/thirdparty/ra6m5ah/r_ioport_cfg.h | 13 - .../ra6m5ah/thirdparty/ra6m5ah/renesas.h | 154 - .../ra6m5bf/thirdparty/ra6m5bf/R7FA6M5BH.h | 29959 ---------------- .../ra6m5bf/thirdparty/ra6m5bf/board_cfg.h | 13 - .../ra6m5bf/thirdparty/ra6m5bf/board_sdram.h | 32 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_api.h | 101 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_cfg.h | 61 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_clocks.h | 1727 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_common.h | 623 - .../thirdparty/ra6m5bf/bsp_compiler_support.h | 109 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_delay.h | 73 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_elc.h | 378 - .../thirdparty/ra6m5bf/bsp_exceptions.h | 44 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_feature.h | 588 - .../thirdparty/ra6m5bf/bsp_group_irq.h | 69 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_guard.h | 32 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_io.h | 465 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_irq.h | 238 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_macl.h | 164 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_api.h | 56 - .../thirdparty/ra6m5bf/bsp_mcu_device_cfg.h | 5 - .../ra6m5bf/bsp_mcu_device_pn_cfg.h | 11 - .../thirdparty/ra6m5bf/bsp_mcu_family_cfg.h | 394 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_info.h | 44 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_mmf.h | 141 - .../thirdparty/ra6m5bf/bsp_module_stop.h | 371 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_pin_cfg.h | 16 - .../ra6m5bf/bsp_register_protection.h | 60 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_sdram.h | 37 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_security.h | 33 - .../ra6m5bf/thirdparty/ra6m5bf/bsp_tfu.h | 218 - .../thirdparty/ra6m5bf/fsp_common_api.h | 380 - .../ra6m5bf/thirdparty/ra6m5bf/fsp_features.h | 297 - .../ra6m5bf/thirdparty/ra6m5bf/fsp_version.h | 76 - .../thirdparty/ra6m5bf/instance/r_ioport.h | 522 - .../ra6m5bf/periph/bsp_peripheral.h | 211 - .../ra6m5bf/thirdparty/ra6m5bf/r_ioport_api.h | 192 - .../ra6m5bf/thirdparty/ra6m5bf/r_ioport_cfg.h | 13 - .../ra6m5bf/thirdparty/ra6m5bf/renesas.h | 154 - .../ra6m5bg/thirdparty/ra6m5bg/R7FA6M5BH.h | 29959 ---------------- .../ra6m5bg/thirdparty/ra6m5bg/board_cfg.h | 13 - .../ra6m5bg/thirdparty/ra6m5bg/board_sdram.h | 32 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_api.h | 101 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_cfg.h | 61 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_clocks.h | 1727 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_common.h | 623 - .../thirdparty/ra6m5bg/bsp_compiler_support.h | 109 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_delay.h | 73 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_elc.h | 378 - .../thirdparty/ra6m5bg/bsp_exceptions.h | 44 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_feature.h | 588 - .../thirdparty/ra6m5bg/bsp_group_irq.h | 69 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_guard.h | 32 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_io.h | 465 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_irq.h | 238 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_macl.h | 164 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_api.h | 56 - .../thirdparty/ra6m5bg/bsp_mcu_device_cfg.h | 5 - .../ra6m5bg/bsp_mcu_device_pn_cfg.h | 11 - .../thirdparty/ra6m5bg/bsp_mcu_family_cfg.h | 394 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_info.h | 44 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_mmf.h | 141 - .../thirdparty/ra6m5bg/bsp_module_stop.h | 371 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_pin_cfg.h | 16 - .../ra6m5bg/bsp_register_protection.h | 60 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_sdram.h | 37 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_security.h | 33 - .../ra6m5bg/thirdparty/ra6m5bg/bsp_tfu.h | 218 - .../thirdparty/ra6m5bg/fsp_common_api.h | 380 - .../ra6m5bg/thirdparty/ra6m5bg/fsp_features.h | 297 - .../ra6m5bg/thirdparty/ra6m5bg/fsp_version.h | 76 - .../thirdparty/ra6m5bg/instance/r_ioport.h | 522 - .../ra6m5bg/periph/bsp_peripheral.h | 211 - .../ra6m5bg/thirdparty/ra6m5bg/r_ioport_api.h | 192 - .../ra6m5bg/thirdparty/ra6m5bg/r_ioport_cfg.h | 13 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ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/renesas.h diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/R7FA6M5BH.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/R7FA6M5BH.h deleted file mode 100644 index 1a24b7118..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/R7FA6M5BH.h +++ /dev/null @@ -1,29959 +0,0 @@ -/* - * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause - * - * @file ./out/R7FA6M5BH.h - * @brief CMSIS HeaderFile - * @version 1.10.08 - */ - -/** @addtogroup Renesas Electronics Corporation - * @{ - */ - -/** @addtogroup R7FA6M5BH - * @{ - */ - -#ifndef R7FA6M5BH_H - #define R7FA6M5BH_H - - #ifdef __cplusplus -extern "C" { - #endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ - #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ - #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ - #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ - #define __MPU_PRESENT 1 /*!< MPU present */ - #define __FPU_PRESENT 1 /*!< FPU present */ - #define __FPU_DP 0 /*!< Double Precision FPU */ - #define __DSP_PRESENT 1 /*!< DSP extension present */ - #define __SAUREGION_PRESENT 0 /*!< SAU region present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - - #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ - #include "system.h" /*!< R7FA6M5BH System */ - - #ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I - #endif - #ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O - #endif - #ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO - #endif - -/* ======================================== Start of section using anonymous unions ======================================== */ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined(__ICCARM__) - #pragma language=extended - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning 586 - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #else - #warning Not supported compiler type - #endif - -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - -/** - * @brief R_BUS_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ - - struct - { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; - }; - - union - { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ - - struct - { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; - }; - __IM uint32_t RESERVED1; -} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_CSb [CSb] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ - - struct - { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; - }; - __IM uint16_t RESERVED1[3]; - - union - { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ - - struct - { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; - }; - __IM uint16_t RESERVED2[2]; -} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ - - struct - { - __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint8_t : 3; - __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ - uint8_t : 2; - } SDCCR_b; - }; - - union - { - __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ - - struct - { - __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ - uint8_t : 7; - } SDCMOD_b; - }; - - union - { - __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ - - struct - { - __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ - uint8_t : 7; - } SDAMOD_b; - }; - __IM uint8_t RESERVED; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ - - struct - { - __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ - uint8_t : 7; - } SDSELF_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ - - struct - { - __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ - __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count - * Setting. ( REFW+1 Cycles ) */ - } SDRFCR_b; - }; - - union - { - __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ - - struct - { - __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ - uint8_t : 7; - } SDRFEN_b; - }; - __IM uint8_t RESERVED4; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ - - struct - { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ - - struct - { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; - - union - { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ - - struct - { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ - - struct - { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; - }; - - union - { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ - - struct - { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ - uint16_t : 1; - } SDMOD_b; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; - - union - { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ - - struct - { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; - }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ - -/** - * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ - } ADD_b; - }; - - union - { - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ - } STAT_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ - - struct - { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ - - struct - { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ - - struct - { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ - - struct - { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ - __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ - uint8_t : 2; - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - - struct - { - __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when - * a bus error occurs */ - uint32_t : 31; - } IRQEN_b; - }; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ - - struct - { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; - }; - }; - __IM uint32_t RESERVED3; -} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[36]; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ - - struct - { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } STAT_b; - }; - __IM uint8_t RESERVED1[7]; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ - - struct - { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } CLR_b; - }; -} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ - -/** - * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } MRE0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } FLBI_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S0BI_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S1BI_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S2BI_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S3BI_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } STBYSBI_b; - }; - __IM uint32_t RESERVED7; - - union - { - union - { - __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } ECBI_b; - }; - - union - { - __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI0BI_b; - }; - }; - __IM uint32_t RESERVED8; - - union - { - union - { - __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } EOBI_b; - }; - - union - { - __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI1BI_b; - }; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PBBI_b; - }; - __IM uint32_t RESERVED10; - - union - { - union - { - __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PABI_b; - }; - - union - { - __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU0SAHBI_b; - }; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PSBI_b; - }; -} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ - -/** - * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } FHBI_b; - }; - - union - { - __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } MRC0BI_b; - }; - }; - __IM uint32_t RESERVED[5]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S1BI_b; - }; -} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ - -/** - * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ - - struct - { - __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read - * Write. */ - - struct - { - __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write - * Status. */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - - struct - { - __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ - __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ - __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ - uint16_t : 13; - } BUSOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } BUSOADPT_b; - }; - __IM uint16_t RESERVED1[5]; - - union - { - __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection - * Register. */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ - } MSAOAD_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } MSAPT_b; - }; -} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ - -/** - * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ - - struct - { - __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ - __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ - __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ - __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ - __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ - __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ - __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ - __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ - __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ - __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ - __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ - __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ - __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ - __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ - __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ - __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ - __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ - __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ - __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ - __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ - __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ - __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ - __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ - __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ - __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ - __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ - __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ - __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ - __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ - __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ - __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ - __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ - } STAT_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ - - struct - { - __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ - __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ - __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ - __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ - __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ - __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ - __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ - __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ - __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ - __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ - __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ - __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ - __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ - __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ - __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ - __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ - __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ - __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ - __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ - __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ - __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ - __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ - __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ - __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ - __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ - __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ - __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ - __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ - __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ - __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ - __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ - __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ - } CLR_b; - }; -} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ - -/** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - - struct - { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ - uint16_t : 2; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ - uint16_t : 10; - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) - */ -typedef struct -{ - union - { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ - - struct - { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; - }; - - union - { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ - - struct - { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; - }; - - union - { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ - - struct - { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; - }; - - union - { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ - - struct - { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; - }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ - - struct - { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; - }; - - union - { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ - - struct - { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ - - struct - { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; - }; - - union - { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ - - struct - { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; - }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ - union - { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ - - struct - { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; - }; - - union - { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct - { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - - struct - { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - - struct - { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct - { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ - - struct - { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - - struct - { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - - struct - { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ - - struct - { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ - - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ - union - { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - - struct - { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; - }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ - union - { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ - - struct - { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; - }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) - */ -typedef struct -{ - union - { - __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ - uint16_t : 12; - } AC_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ - - struct - { - __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. - * NOTE: Some low-order bits are fixed to 0. */ - } S_b; - }; - - union - { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ - - struct - { - __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination. NOTE: Some low-order - * bits are fixed to 1. */ - } E_b; - }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } EN_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } ENPT_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_SEC_b; - }; - __IM uint16_t RESERVED3; - __IM uint32_t RESERVED4[60]; - __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ - __IM uint32_t RESERVED5[32]; -} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ - union - { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ - - struct - { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; - }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; - - union - { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union - { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union - { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; - - union - { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; - }; - __IM uint8_t RESERVED3[3]; - - union - { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; - - union - { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; - }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; - }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; - }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ - union - { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ - - struct - { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; - }; - - union - { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ - - struct - { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; - }; - - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; - - union - { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct - { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; - - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ - - struct - { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; - - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ - - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; - - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; - }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ - - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct - { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - - struct - { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ - - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct - { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ - - struct - { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED23[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ - - struct - { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; - }; - - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; - - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ - - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ - __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ - uint32_t : 2; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ - uint32_t : 27; - } MSSAR_b; - }; - - union - { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - - union - { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ - - struct - { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; - }; - - union - { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; - }; - - union - { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ - - struct - { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; - }; - - union - { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ - - struct - { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; - }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ - - union - { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - - union - { - __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ - }; - __IM uint32_t RESERVED4[58]; - - union - { - union - { - __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ - uint32_t : 31; - } BUSMABT_b; - }; - __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - }; - __IM uint32_t RESERVED5[46]; - - union - { - __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ - __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ - }; - __IM uint32_t RESERVED6[33]; - - union - { - __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ - - struct - { - __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ - uint32_t : 2; - __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ - uint32_t : 12; - __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ - uint32_t : 15; - } BUSDIVBYP_b; - }; - __IM uint32_t RESERVED7[63]; - - union - { - __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ - - struct - { - __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ - uint16_t : 15; - } BUSTHRPUT_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[255]; - __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED10[16]; - - union - { - __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address - * and Read/Write Status registers. */ - }; - __IM uint32_t RESERVED11[28]; - - union - { - __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ - __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ - }; - __IM uint32_t RESERVED12[16]; - __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED13[5]; - __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ -} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ - union - { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; - }; - - union - { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct - { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; - }; - - union - { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - - struct - { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; - - union - { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - - struct - { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; - }; - - union - { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ - - struct - { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - - union - { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; - }; - - union - { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ - - struct - { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; - }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; - }; - - union - { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - - struct - { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; - }; - - union - { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ - - struct - { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; - }; - - union - { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ - - struct - { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; - }; - - union - { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ - - struct - { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; - }; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - - struct - { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; - }; - - union - { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ - - struct - { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; - }; - - union - { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - - struct - { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; - }; - - union - { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; - }; - - union - { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; - }; - __IM uint32_t RESERVED3[18]; - - union - { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ - - struct - { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; - }; - __IM uint32_t RESERVED4[18]; - - union - { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ - - struct - { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; - }; - __IM uint32_t RESERVED5[18]; - - union - { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; - }; - __IM uint32_t RESERVED6[18]; - - union - { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct - { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; - }; - - union - { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; - }; - - union - { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ - - struct - { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; - }; - - union - { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; - }; - - union - { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; - }; - - union - { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ - - struct - { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; - }; - - union - { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ - - struct - { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; - }; - __IM uint32_t RESERVED7[2]; - - union - { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ - - struct - { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; - }; - __IM uint32_t RESERVED8[288]; - - union - { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ - - struct - { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; - }; - __IM uint32_t RESERVED9[288]; - - union - { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ - - struct - { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; - }; - __IM uint32_t RESERVED10[36]; - - union - { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ - - struct - { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; - }; - __IM uint32_t RESERVED11[36]; - - union - { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ - - struct - { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; - }; - __IM uint32_t RESERVED12[36]; - - union - { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ - - struct - { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; - }; - __IM uint32_t RESERVED13[36]; - - union - { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ - - struct - { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; - }; - __IM uint32_t RESERVED14[40]; - - union - { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; - }; - __IM uint32_t RESERVED15[6]; - - union - { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; - }; - __IM uint32_t RESERVED16[6]; - - union - { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; - }; - __IM uint32_t RESERVED17[6]; - - union - { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; - }; - __IM uint32_t RESERVED18[6]; - - union - { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; - }; - __IM uint32_t RESERVED19[6]; - - union - { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; - }; - __IM uint32_t RESERVED20[6]; - - union - { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; - }; - __IM uint32_t RESERVED21[6]; - - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; - - union - { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; - }; - __IM uint32_t RESERVED23[6]; - - union - { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; - }; - __IM uint32_t RESERVED24[6]; - - union - { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; - }; - __IM uint32_t RESERVED25[6]; - - union - { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; - }; - __IM uint32_t RESERVED26[6]; - - union - { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - - struct - { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; - }; - - union - { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ - - struct - { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; - }; - __IM uint32_t RESERVED27; - - union - { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; - }; - - union - { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ - - struct - { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; - }; - __IM uint32_t RESERVED28[24]; - - union - { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ - - struct - { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; - }; - __IM uint32_t RESERVED29[6]; - - union - { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ - - struct - { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; - }; - __IM uint32_t RESERVED30[6]; - - union - { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ - - struct - { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; - }; - __IM uint32_t RESERVED31[46]; - - union - { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ - - struct - { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; - }; - __IM uint32_t RESERVED32; - - union - { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ - - struct - { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; - }; - - union - { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ - - struct - { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; - }; - __IM uint32_t RESERVED33; - - union - { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ - - struct - { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; - }; - __IM uint32_t RESERVED34; - - union - { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ - - struct - { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; - }; - - union - { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ - - struct - { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ - - struct - { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ - - struct - { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; - - union - { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ - - struct - { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; - }; - - union - { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ - - struct - { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; - }; - __IM uint32_t RESERVED36[2]; - - union - { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ - - struct - { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; - }; - - union - { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ - - struct - { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; - }; - __IM uint32_t RESERVED37[2]; - - union - { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; - }; - __IM uint32_t RESERVED38[10]; - - union - { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ - - struct - { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; - }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; - - union - { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ - - struct - { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; - }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ - -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; - - union - { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - - struct - { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; - }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ - -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ - union - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - - struct - { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; - }; - - union - { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - - struct - { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; - }; - - union - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ - - struct - { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; - }; - - union - { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct - { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; - - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ - - struct - { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; - }; - - union - { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ - - struct - { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; - }; - - union - { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; - }; - - union - { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; - }; - - union - { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ - - struct - { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; - }; - - union - { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ - - struct - { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; - }; - - union - { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; - }; - - union - { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ - - struct - { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; - }; - - union - { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ - - struct - { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; - }; - - union - { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ - - struct - { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; - }; - - union - { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ - - struct - { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; - }; - - union - { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ - - struct - { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; - }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ - -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ - union - { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ - - struct - { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; - }; - - union - { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; - }; - - union - { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; - }; - - union - { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; - }; - - union - { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ - - struct - { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; - }; - - union - { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; - }; - - union - { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ - - struct - { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; - }; - __IM uint16_t RESERVED[9]; - - union - { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; - - union - { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ - - struct - { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ - union - { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct - { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct - { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 12; - __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ - __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; - __IM uint32_t RESERVED1[123]; - - union - { - __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ - - struct - { - __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ - __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ - uint32_t : 6; - __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ - uint32_t : 21; - } FSBLSTAT_b; - }; -} R_DEBUG_Type; /*!< Size = 516 (0x204) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ - -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ - union - { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ - - struct - { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ - - struct - { - __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ - uint8_t : 3; - __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ - uint8_t : 3; - } DMCTL_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[11]; - - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ - - struct - { - __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ - uint32_t : 4; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; - }; - __IM uint32_t RESERVED6[15]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ - union - { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ - - struct - { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; - }; - - union - { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ - - struct - { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; - }; - - union - { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; - }; - - union - { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; - }; - - union - { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ - - struct - { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ - - struct - { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; - }; - - union - { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ - - struct - { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-24 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-24 Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-24 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-24 Mode */ - } DMAMD_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ - - struct - { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-24 mode for transfer source or destination. */ - } DMOFR_b; - }; - - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ - - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - - union - { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ - - struct - { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; - }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ - - union - { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct - { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; - - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ - - struct - { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; - }; - - union - { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct - { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ - -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ - - struct - { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ - - struct - { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; - }; - - union - { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ - - struct - { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; - }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ - -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ - union - { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_b; - }; - - union - { - __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ - - struct - { - __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ - uint8_t : 7; - } DTCADMOD_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ - - struct - { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ - - struct - { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; - }; - - union - { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_SEC_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - - union - { - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_SEC_b; - }; - - union - { - __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ - - struct - { - __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ - } DTCDISP_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ - - struct - { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; - }; - - union - { - __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ - } DTCIBR_b; - }; - - union - { - __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ - - struct - { - __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ - uint8_t : 7; - } DTCOR_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ - - struct - { - __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ - uint16_t : 7; - __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ - } DTCSQE_b; - }; - __IM uint16_t RESERVED10; -} R_DTC_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ - union - { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; - }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; - - union - { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ - - struct - { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ - - struct - { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ - -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ -{ - union - { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ - - struct - { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ - - struct - { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ - - struct - { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ - - struct - { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ - - struct - { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ - - struct - { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; - }; - __IM uint32_t RESERVED5[5]; - - union - { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ - - struct - { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ - - struct - { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; - }; - - union - { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ - - struct - { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; - }; - - union - { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ - - struct - { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ - - struct - { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; - }; - - union - { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ - - struct - { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; - }; - __IM uint32_t RESERVED8[20]; - - union - { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ - - struct - { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ - - struct - { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ - - struct - { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ - - union - { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ - - struct - { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; - }; - - union - { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ - - struct - { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ - - struct - { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; - }; - - union - { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ - - struct - { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union - { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; - }; - - union - { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; - }; - - union - { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ - - struct - { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; - }; - - union - { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ - - struct - { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; - }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ - -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ -{ - union - { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ - - struct - { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ - - struct - { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ - - struct - { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ - - struct - { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ - - struct - { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ - - struct - { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ - - struct - { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; - }; - __IM uint32_t RESERVED11[2]; - - union - { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ - - struct - { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; - }; - - union - { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ - - struct - { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; - }; - - union - { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ - - struct - { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; - }; - - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ - - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ - - struct - { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; - }; - - union - { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ - - struct - { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; - }; - __IM uint32_t RESERVED13[18]; - - union - { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ - - struct - { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; - }; - - union - { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; - }; - __IM uint32_t RESERVED14; - - union - { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ - - struct - { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; - }; - - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ - union - { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ - -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ - - struct - { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; - - union - { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ - - struct - { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; - }; - - union - { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ - - struct - { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union - { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ - - struct - { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ - - struct - { - __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ - uint8_t : 5; - } FCNTSELR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR0_b; - }; - - union - { - __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR1_b; - }; - __IM uint32_t RESERVED12[9]; - - union - { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ - - struct - { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; - }; - __IM uint16_t RESERVED13; - - union - { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ - - struct - { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; - }; - __IM uint16_t RESERVED14; - - union - { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ - - struct - { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; - }; - - union - { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ - - struct - { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; - }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16; - - union - { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ - - struct - { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; - }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[4]; - - union - { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ - - struct - { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; - }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[11]; - - union - { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ - - struct - { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; - - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ - - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; - - union - { - union - { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ - - struct - { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; - }; - - union - { - __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ - - struct - { - __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address - * or the last blank checked address which is found in 'Blank - * Check' command execution. */ - uint32_t : 8; - } FBCADDR_b; - }; - }; - - union - { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ - - struct - { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; - }; - - union - { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ - - struct - { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ - - struct - { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ - - struct - { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; - }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; - - union - { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ - - struct - { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-24 Register */ - - struct - { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-24 Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; - - union - { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ - - struct - { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; - - union - { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ - - struct - { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ - uint16_t : 6; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ - __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ - uint16_t : 4; - __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ - } FSAR_b; - }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief General PWM Timer (R_GPT0) - */ - -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ - union - { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ - - struct - { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; - }; - - union - { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ - - struct - { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; - }; - - union - { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ - - struct - { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; - }; - - union - { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ - - struct - { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; - }; - - union - { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ - - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; - }; - - union - { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ - - struct - { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; - }; - - union - { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ - - struct - { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; - - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ - - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; - - union - { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ - - struct - { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ - uint32_t : 7; - } GTICASR_b; - }; - - union - { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ - - struct - { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ - uint32_t : 7; - } GTICBSR_b; - }; - - union - { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ - - struct - { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 3; - __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ - __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ - uint32_t : 2; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; - }; - - union - { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ - - struct - { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection - * timing setting */ - uint32_t : 3; - } GTUDDTYC_b; - }; - - union - { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ - - struct - { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-24.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-24.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; - }; - - union - { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ - - struct - { - __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; - }; - - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ - - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; - }; - - union - { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ - - struct - { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; - }; - - union - { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ - - struct - { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; - }; - - union - { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ - - struct - { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; - }; - - union - { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ - - struct - { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; - }; - - union - { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ - - struct - { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; - }; - - union - { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ - - struct - { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; - - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; - - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; - - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ - - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; - - union - { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; - }; - - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ - - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; - - union - { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; - }; - - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ - - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; - }; - - union - { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ - - struct - { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; - }; - - union - { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ - - struct - { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; - }; - - union - { - __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Control Register */ - - struct - { - __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter - * 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 - * Skipping Count Setting */ - __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping - * Counter 1 Initial Value */ - __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping - * Counter 1 */ - __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping - * 2 Skipping Count Setting */ - __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Initial Value */ - __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping - * Counter 2 */ - } GTADCMSC_b; - }; - - union - { - __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Setting Register */ - - struct - { - __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 9; - __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 9; - } GTADCMSS_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ - - struct - { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; - }; - - union - { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ - - struct - { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; - }; - __IM uint32_t RESERVED1[2]; - - union - { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ - - struct - { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; - }; - - union - { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ - - struct - { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; - }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ - -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ - union - { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ - - struct - { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; - }; - __IM uint32_t RESERVED[15]; - - union - { - __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection - * Register */ - - struct - { - __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ - uint16_t : 7; - __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ - } GTONCWP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling - * Register */ - - struct - { - __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ - uint16_t : 3; - __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ - __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ - uint16_t : 7; - } GTONCCR_b; - }; - __IM uint16_t RESERVED2; -} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ - -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ - union - { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ - - struct - { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 1; - __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; - }; - __IM uint32_t RESERVED[60]; - - union - { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - - struct - { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - - union - { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ - - struct - { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; - }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; - - union - { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ - - struct - { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; - }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; - - union - { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ - - struct - { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; - - union - { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - - struct - { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - - union - { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ - - struct - { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; - }; - - union - { - __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ - - struct - { - __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze - * Mode */ - uint32_t : 27; - } WUPEN2_b; - }; - __IM uint32_t RESERVED10[5]; - - union - { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ - - struct - { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; - }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; - __IM uint32_t RESERVED16[24]; - - union - { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ - - struct - { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; - }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ - union - { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ - - struct - { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; - }; - - union - { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ - - struct - { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; - }; - - union - { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ - - struct - { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; - }; - - union - { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ - - struct - { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; - }; - - union - { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ - - struct - { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; - }; - - union - { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ - - struct - { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; - }; - - union - { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ - - struct - { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; - }; - - union - { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ - - struct - { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; - }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ - - union - { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ - - struct - { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; - }; - - union - { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ - - struct - { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; - }; - - union - { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ - - struct - { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; - }; - - union - { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ - - struct - { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ - - struct - { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; - }; - - union - { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ - - struct - { - __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; - }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; - }; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; - - union - { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ - -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ - union - { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ - - struct - { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ - - struct - { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; - }; - - union - { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ - - struct - { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; - }; - - union - { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ - - struct - { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ - - struct - { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 2; - __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ - __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ - __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ - __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ - uint32_t : 3; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; - }; - - union - { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; - }; - - union - { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; - }; - - union - { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; - }; - - union - { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ - - struct - { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ - - struct - { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; - }; - __IM uint32_t RESERVED4[4]; - - union - { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ - - struct - { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ - - struct - { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; - }; - - union - { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ - - struct - { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ - uint32_t : 13; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; - }; - - union - { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ - - struct - { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; - }; - - union - { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ - - struct - { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; - }; - - union - { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ - - struct - { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; - }; - - union - { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ - - struct - { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; - }; - - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ - - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; - - union - { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ - - struct - { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; - }; - - union - { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ - - struct - { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; - }; - - union - { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ - - struct - { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ - - struct - { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ - - struct - { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; - }; - - union - { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ - - struct - { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; - }; - __IM uint32_t RESERVED9[2]; - - union - { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ - - struct - { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; - }; - __IM uint32_t RESERVED10[3]; - - union - { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ - - struct - { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; - }; - __IM uint32_t RESERVED11[23]; - - union - { - __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ - - struct - { - __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ - uint32_t : 31; - } STCTL_b; - }; - - union - { - __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ - - struct - { - __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ - __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ - __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ - uint32_t : 5; - __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ - uint32_t : 16; - } ATCTL_b; - }; - - union - { - __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ - - struct - { - __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ - uint32_t : 31; - } ATTRG_b; - }; - - union - { - __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ - - struct - { - __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, - * SC2. */ - uint32_t : 31; - } ATCCNTE_b; - }; - __IM uint32_t RESERVED12[4]; - - union - { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ - - struct - { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; - }; - __IM uint32_t RESERVED13[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED14[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - - union - { - __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ - - struct - { - __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ - } HCMDQP_b; - }; - - union - { - __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ - - struct - { - __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ - } HRSPQP_b; - }; - - union - { - __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ - - struct - { - __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ - } HTDTBP_b; - }; - - union - { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; - }; - - union - { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; - }; - __IM uint32_t RESERVED15[10]; - - union - { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ - - struct - { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; - }; - - union - { - __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ - uint32_t : 16; - } HQTHCTL_b; - }; - - union - { - __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold - * Control Register */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ - uint32_t : 5; - } HTBTHCTL_b; - }; - __IM uint32_t RESERVED16; - - union - { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ - - struct - { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 3; - __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ - uint32_t : 7; - } BST_b; - }; - - union - { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ - - struct - { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ - uint32_t : 7; - } BSTE_b; - }; - - union - { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ - - struct - { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ - uint32_t : 7; - } BIE_b; - }; - - union - { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ - - struct - { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 3; - __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ - uint32_t : 7; - } BSTFC_b; - }; - - union - { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; - }; - - union - { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; - }; - - union - { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; - }; - - union - { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; - }; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ - __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ - uint32_t : 1; - __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ - uint32_t : 22; - } HTST_b; - }; - - union - { - __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ - __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ - uint32_t : 22; - } HTSTE_b; - }; - - union - { - __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ - __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ - uint32_t : 22; - } HTIE_b; - }; - - union - { - __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ - __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ - uint32_t : 1; - __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ - uint32_t : 22; - } HTSTFC_b; - }; - - union - { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ - - struct - { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; - }; - - union - { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - - struct - { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ - uint32_t : 13; - } SVST_b; - }; - - union - { - __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ - - struct - { - __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; - }; - - union - { - __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ - - struct - { - __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ - } MRCCPT_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; - }; - __IM uint32_t RESERVED19; - - union - { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; - }; - __IM uint32_t RESERVED20; - - union - { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; - }; - __IM uint32_t RESERVED21; - - union - { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; - }; - __IM uint32_t RESERVED22; - - union - { - __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS4_b; - }; - __IM uint32_t RESERVED23; - - union - { - __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS5_b; - }; - __IM uint32_t RESERVED24; - - union - { - __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS6_b; - }; - __IM uint32_t RESERVED25; - - union - { - __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS7_b; - }; - __IM uint32_t RESERVED26[16]; - - union - { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - - struct - { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; - }; - __IM uint32_t RESERVED27[3]; - - union - { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; - }; - - union - { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; - }; - - union - { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; - }; - __IM uint32_t RESERVED28[5]; - - union - { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; - }; - - union - { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; - }; - - union - { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; - }; - - union - { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; - }; - - union - { - __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT4_b; - }; - - union - { - __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT5_b; - }; - - union - { - __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT6_b; - }; - - union - { - __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT7_b; - }; - __IM uint32_t RESERVED29[12]; - - union - { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - - struct - { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; - }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED30; - - union - { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; - }; - - union - { - __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD1_b; - }; - - union - { - __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD2_b; - }; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ - - struct - { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; - }; - - union - { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - - struct - { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; - }; - - union - { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ - - struct - { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; - }; - - union - { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ - - struct - { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; - }; - - union - { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - - struct - { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; - }; - - union - { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ - - struct - { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; - }; - - union - { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ - - struct - { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; - }; - - union - { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ - - struct - { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; - }; - - union - { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ - - struct - { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; - }; - - union - { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ - - struct - { - __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ - __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ - __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ - uint32_t : 5; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; - }; - - union - { - __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) - * Register */ - - struct - { - __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ - __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ - uint32_t : 4; - __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ - uint32_t : 24; - } CETSS_b; - }; - - union - { - __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ - - struct - { - __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ - __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ - __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ - uint32_t : 29; - } CGHDRCAP_b; - }; - - union - { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ - - struct - { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; - }; - __IM uint32_t RESERVED32[4]; - - union - { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; - }; - - union - { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; - }; - __IM uint32_t RESERVED33[9]; - - union - { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ - - struct - { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; - }; - - union - { - __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ - uint32_t : 16; - } HQSTLV_b; - }; - - union - { - __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ - uint32_t : 16; - } HDBSTLV_b; - }; - - union - { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - - struct - { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; - }; - - union - { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ - - struct - { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; - __IM uint32_t RESERVED34[3]; - - union - { - __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ - - struct - { - __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ - uint32_t : 16; - } SC1CPT_b; - }; - - union - { - __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ - - struct - { - __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ - uint32_t : 16; - } SC2CPT_b; - }; -} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OADPT_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[62]; - __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ - - struct - { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; - }; - - union - { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ - - struct - { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; - }; - - union - { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ - - struct - { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; - }; - - union - { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; - }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ - -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ - union - { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; - - struct - { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; - }; - - union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; - }; - - union - { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; - - struct - { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; - - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ - - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; - }; - - union - { - union - { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ - - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; - - struct - { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; - - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; - }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ - -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-MISC (R_PMISC) - */ - -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ - union - { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; - }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ - union - { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct - { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; - - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - - struct - { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; - - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; - - union - { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct - { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - - struct - { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; - - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ - - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; - }; - - union - { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct - { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct - { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ - __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using - * time error adjustment function inlow-consumption clock - * mode. */ - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; - }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; - - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; - - union - { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; - - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; - }; - __IM uint8_t RESERVED9; - - union - { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; - - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; - }; - __IM uint8_t RESERVED10; - - union - { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; - - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; - }; - __IM uint8_t RESERVED11; - - union - { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; - - union - { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; - }; - __IM uint8_t RESERVED12; - - union - { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; - - union - { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; - }; - - union - { - union - { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; - - union - { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ - - struct - { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; - }; - - union - { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - - struct - { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; - }; - - union - { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ - - struct - { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; - }; - __IM uint8_t RESERVED19; - - union - { - __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ - - struct - { - uint16_t : 5; - __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ - } RADJ2_b; - }; - __IM uint16_t RESERVED20[7]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ - -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ - union - { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; - - union - { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; - - union - { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; - - union - { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct - { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; - - union - { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF - * = 0, and MMR.MANEN = 1) */ - - struct - { - __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_MANC_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - union - { - __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ - __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ - uint16_t : 2; - __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ - uint16_t : 3; - } TDRHL_MAN_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - union - { - __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ - uint16_t : 2; - __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ - uint16_t : 3; - } RDRHL_MAN_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ - - struct - { - __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ - __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ - __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ - uint8_t : 1; - __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ - __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ - __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ - __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ - } MMR_b; - }; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; - }; - - union - { - __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ - __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ - uint8_t : 2; - } TMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ - - struct - { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; - }; - - union - { - __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ - __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ - uint8_t : 2; - } RMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ - - struct - { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; - }; - - union - { - __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ - - struct - { - __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ - __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ - uint8_t : 5; - } MESR_b; - }; - }; - - union - { - union - { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ - - struct - { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; - }; - - union - { - __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ - - struct - { - __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ - __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ - uint8_t : 5; - } MECR_b; - }; - }; - - union - { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ - - struct - { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; - }; - - union - { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ - - struct - { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; - - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct - { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ - - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ - - struct - { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ - - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ - - struct - { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ - - struct - { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; - - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct - { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ - __IM uint16_t RESERVED1[4]; - - union - { - __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ - - struct - { - __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ - uint8_t : 7; - } SCIMSKEN_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_SCI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ - -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ - union - { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ - - struct - { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ - - struct - { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; - }; - - union - { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - - struct - { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; - }; - - union - { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - - struct - { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; - }; - - union - { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - - struct - { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; - }; - - union - { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - - struct - { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; - }; - - union - { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - - struct - { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; - }; - - union - { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ - - struct - { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; - }; - - union - { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - - struct - { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; - }; - - union - { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ - - struct - { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; - }; - - union - { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - - struct - { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; - }; - - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ - - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; - - union - { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - - struct - { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; - }; - - union - { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; - }; - - union - { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ - - struct - { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; - }; - - union - { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; - }; - - union - { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct - { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; - }; - - union - { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct - { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; - }; - - union - { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ - - struct - { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; - }; - - union - { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - - struct - { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ - - struct - { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; - }; - - union - { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - - struct - { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; - }; - - union - { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ - - struct - { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - - struct - { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; - }; - __IM uint32_t RESERVED3[79]; - - union - { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ - - struct - { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; - }; - __IM uint32_t RESERVED4[3]; - - union - { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ - - struct - { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; - }; - __IM uint32_t RESERVED6[4]; - - union - { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ - - struct - { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; - }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ - - struct - { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; - }; - - union - { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - - struct - { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; - }; - - union - { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ - - struct - { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; - }; - - union - { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - - struct - { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ - }; - - union - { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ - - struct - { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; - }; - - union - { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - - struct - { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; - }; - - union - { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ - - struct - { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; - }; - - union - { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ - - struct - { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; - }; - - union - { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ - - struct - { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; - }; - - union - { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ - - struct - { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; - }; - - union - { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ - - struct - { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; - }; - - union - { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ - - struct - { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; - }; - - union - { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ - - struct - { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; - }; - - union - { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ - - struct - { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; - }; - - union - { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ - - struct - { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; - }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ - -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ - union - { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ - - struct - { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; - }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; - - union - { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ - - struct - { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; - }; - __IM uint8_t RESERVED3[179]; - - union - { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ - - struct - { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; - }; - - union - { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; - }; - - union - { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-24 Enable Register */ - - struct - { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-24 Enable */ - uint8_t : 7; - } ECC1STSEN_b; - }; - - union - { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; - }; - - union - { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; - }; - __IM uint8_t RESERVED4[11]; - - union - { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; - }; - __IM uint8_t RESERVED5[3]; - - union - { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ - - struct - { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; - }; - __IM uint8_t RESERVED6[3]; - - union - { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; - }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ -{ - union - { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ - - struct - { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; - }; - - union - { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ - - struct - { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ - - struct - { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 3; - __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ - uint32_t : 4; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; - }; - - union - { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ - - struct - { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; - }; - - union - { - union - { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - - struct - { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; - }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - - union - { - union - { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - - struct - { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; - }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - }; - - union - { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ - - struct - { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; - }; - - union - { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ - - struct - { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; - }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System Pins (R_SYSTEM) - */ - -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ - - struct - { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; - }; - - union - { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; - }; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ - - struct - { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ - - struct - { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; - }; - - union - { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ - - struct - { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; - }; - - union - { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ - - struct - { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ - - struct - { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; - }; - - union - { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ - - struct - { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; - }; - - union - { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; - }; - - union - { - __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register - * 2 */ - - struct - { - __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ - uint8_t : 1; - __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ - uint8_t : 2; - } HOCOCR2_b; - }; - - union - { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; - }; - - union - { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ - - struct - { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; - }; - - union - { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ - - struct - { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; - }; - - union - { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ - - struct - { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ - uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ - uint8_t : 1; - } OSCSF_b; - }; - __IM uint8_t RESERVED8; - - union - { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ - - struct - { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; - }; - - union - { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ - - struct - { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; - }; - - union - { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ - - struct - { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; - }; - - union - { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ - - struct - { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; - }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; - - union - { - __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ - - struct - { - __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ - uint16_t : 2; - } PLL2CCR_b; - }; - - union - { - __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ - - struct - { - __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ - uint8_t : 7; - } PLL2CR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ - - struct - { - __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock - * (valid only when LPOPTEN = 1) */ - __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ - __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W - * clock (valid only when LPOPT.LPOPTEN = 1) */ - uint8_t : 3; - __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ - } LPOPT_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ - - struct - { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ - - struct - { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; - }; - - union - { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ - - struct - { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; - }; - __IM uint32_t RESERVED15[3]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO - * trimming bits */ - } MOCOUTCR_b; - }; - - union - { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; - }; - __IM uint8_t RESERVED17; - __IM uint32_t RESERVED18[2]; - - union - { - __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ - - struct - { - __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ - uint8_t : 5; - } USBCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ - uint8_t : 5; - } OCTACKDIVCR_b; - }; - - union - { - __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ - uint8_t : 5; - } SCISPICKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ - - struct - { - __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ - uint8_t : 5; - } CANFDCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - - struct - { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; - }; - - union - { - __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ - - struct - { - __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ - uint8_t : 5; - } USB60CKDIVCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - - struct - { - __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ - uint8_t : 5; - } CECCKDIVCR_b; - }; - - union - { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ - - struct - { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ - - struct - { - __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ - uint8_t : 5; - } I3CCKDIVCR_b; - }; - __IM uint16_t RESERVED19; - - union - { - __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ - __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ - } USBCKCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ - - struct - { - __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ - uint8_t : 3; - __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ - __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ - } OCTACKCR_b; - }; - - union - { - __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ - - struct - { - __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ - uint8_t : 3; - __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ - __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ - } SCISPICKCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ - - struct - { - __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ - __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ - } CANFDCKCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - - struct - { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; - }; - - union - { - __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ - - struct - { - __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ - uint8_t : 2; - __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ - __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ - } USB60CKCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ - - struct - { - __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ - __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ - } CECCKCR_b; - }; - - union - { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ - - struct - { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ - - struct - { - __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ - uint8_t : 3; - __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ - __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ - } I3CCKCR_b; - }; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ - uint32_t : 29; - } SNZREQCR1_b; - }; - __IM uint32_t RESERVED22; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ - - struct - { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; - }; - __IM uint8_t RESERVED24; - - union - { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ - - struct - { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; - }; - - union - { - __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ - - struct - { - __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ - uint8_t : 7; - } SNZEDCR1_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ - - struct - { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; - }; - - union - { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ - - struct - { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; - }; - - union - { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ - - struct - { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; - }; - __IM uint8_t RESERVED27; - - union - { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ - - struct - { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; - }; - __IM uint8_t RESERVED28[2]; - - union - { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ - - struct - { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; - }; - __IM uint16_t RESERVED29[2]; - - union - { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ - - struct - { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; - }; - __IM uint8_t RESERVED30; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ - - struct - { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ - uint16_t : 1; - __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ - } RSTSR1_b; - }; - __IM uint16_t RESERVED32; - __IM uint32_t RESERVED33[3]; - - union - { - __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_ALT_b; - }; - - union - { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ - - struct - { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; - }; - __IM uint16_t RESERVED34; - __IM uint32_t RESERVED35[3]; - - union - { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; - }; - - union - { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; - }; - - union - { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; - }; - - union - { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; - }; - __IM uint32_t RESERVED36[183]; - - union - { - __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute - * Register */ - - struct - { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ - __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ - __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ - __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ - __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ - __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ - __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ - __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ - __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ - __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ - __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ - __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ - } CGFSAR_b; - }; - __IM uint32_t RESERVED37; - - union - { - __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - uint32_t : 1; - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 1; - __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - uint32_t : 3; - __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - uint32_t : 22; - } LPMSAR_b; - }; - - union - { - union - { - __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - uint32_t : 30; - } LVDSAR_b; - }; - - union - { - __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 29; - } RSTSAR_b; - }; - }; - - union - { - __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 13; - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - uint32_t : 8; - } BBFSAR_b; - }; - __IM uint32_t RESERVED38[3]; - - union - { - __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution - * Register */ - - struct - { - __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit - * 0 */ - __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit - * 1 */ - __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit - * 2 */ - __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit - * 3 */ - __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit - * 4 */ - __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit - * 5 */ - __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit - * 6 */ - __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit - * 7 */ - __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit - * 8 */ - __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit - * 9 */ - __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit - * 10 */ - __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit - * 11 */ - __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit - * 12 */ - __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit - * 13 */ - __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit - * 14 */ - __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit - * 15 */ - __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit - * 16 */ - __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit - * 17 */ - __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit - * 18 */ - __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit - * 19 */ - __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit - * 20 */ - uint32_t : 3; - __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit - * 24 */ - uint32_t : 1; - __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit - * 26 */ - __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit - * 27 */ - uint32_t : 4; - } DPFSAR_b; - }; - __IM uint32_t RESERVED39[6]; - __IM uint16_t RESERVED40; - - union - { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ - - struct - { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ - uint16_t : 3; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; - }; - - union - { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ - - struct - { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; - }; - - union - { - __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ - - struct - { - __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ - uint8_t : 2; - } DPSWCR_b; - }; - - union - { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ - - struct - { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; - }; - - union - { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ - - struct - { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; - }; - - union - { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ - - struct - { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; - }; - - union - { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 4; - } DPSIER3_b; - }; - - union - { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ - - struct - { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; - }; - - union - { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ - - struct - { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; - }; - - union - { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ - - struct - { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; - }; - - union - { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ - uint8_t : 4; - } DPSIFR3_b; - }; - - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; - }; - - union - { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; - }; - - union - { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ - - struct - { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; - }; - __IM uint8_t RESERVED41; - - union - { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ - - struct - { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; - }; - - union - { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ - - struct - { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; - }; - - union - { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ - - struct - { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; - }; - - union - { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ - - struct - { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; - }; - __IM uint8_t RESERVED42; - - union - { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; - }; - __IM uint16_t RESERVED43; - - union - { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ - - struct - { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; - }; - - union - { - union - { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; - }; - - union - { - __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 2; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ - } LVD1CMPCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - - struct - { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; - }; - - union - { - __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 4; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ - } LVD2CMPCR_b; - }; - }; - __IM uint8_t RESERVED44; - - union - { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; - }; - - union - { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; - }; - __IM uint8_t RESERVED45; - - union - { - __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select - * Register */ - - struct - { - __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ - uint8_t : 7; - } VBATTMNSELR_b; - }; - - union - { - __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ - - struct - { - __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ - uint8_t : 7; - } VBATTMONR_b; - }; - - union - { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ - - struct - { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; - }; - __IM uint32_t RESERVED46[8]; - - union - { - union - { - __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ - - struct - { - __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ - __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ - uint8_t : 2; - __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ - __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ - __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ - __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ - } DCDCCTL_b; - }; - - union - { - __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ - - struct - { - __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ - __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ - uint8_t : 6; - } LDOSCR_b; - }; - }; - - union - { - __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ - - struct - { - __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ - uint8_t : 6; - } VCCSEL_b; - }; - __IM uint16_t RESERVED47; - - union - { - __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ - - struct - { - __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ - uint8_t : 7; - } PL2LDOSCR_b; - }; - __IM uint8_t RESERVED48; - __IM uint16_t RESERVED49; - __IM uint32_t RESERVED50[14]; - - union - { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; - }; - - union - { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ - - struct - { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; - }; - - union - { - __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ - - struct - { - __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ - uint8_t : 6; - } SOMRG_b; - }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[3]; - - union - { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; - }; - __IM uint8_t RESERVED53; - - union - { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; - }; - __IM uint8_t RESERVED54; - __IM uint32_t RESERVED55[7]; - - union - { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; - }; - - union - { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ - - struct - { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; - }; - - union - { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ - - struct - { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; - }; - __IM uint8_t RESERVED56; - - union - { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ - - struct - { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; - }; - __IM uint8_t RESERVED57; - - union - { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ - - struct - { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; - }; - __IM uint8_t RESERVED58; - - union - { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; - }; - - union - { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ - - struct - { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; - }; - - union - { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ - - struct - { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; - }; - - union - { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ - - struct - { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; - }; - - union - { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ - - struct - { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; - }; - - union - { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ - - struct - { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; - }; - - union - { - __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ - uint8_t : 4; - } VBTBER_b; - }; - __IM uint8_t RESERVED59; - __IM uint16_t RESERVED60; - __IM uint32_t RESERVED61[15]; - - union - { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ - - struct - { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; - }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ - -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ - union - { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ - - struct - { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; - }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ - -typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ -{ - union - { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; - }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ - -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } DVCHGR_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ - uint16_t : 4; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - - union - { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - - struct - { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; - - union - { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ - - struct - { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ - - struct - { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; - - union - { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ - - struct - { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct - { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED23[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED25[5]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - __IM uint32_t RESERVED26[165]; - - union - { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ - - struct - { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union - { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ - - struct - { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ - -typedef struct /*!< (@ 0x40083400) R_WDT Structure */ -{ - union - { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ - - struct - { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; - }; - - union - { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; - }; - - union - { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/** - * @brief TrustZone Filter (R_TZF) - */ - -typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ -{ - union - { - __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFPT_b; - }; -} R_TZF_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief R_CACHE (R_CACHE) - */ - -typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ -{ - union - { - __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ - - struct - { - __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ - uint32_t : 31; - } CCACTL_b; - }; - - union - { - __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ - uint32_t : 31; - } CCAFCT_b; - }; - - union - { - __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ - uint32_t : 30; - } CCALCF_b; - }; - __IM uint32_t RESERVED[13]; - - union - { - __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ - - struct - { - __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ - uint32_t : 31; - } SCACTL_b; - }; - - union - { - __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ - uint32_t : 31; - } SCAFCT_b; - }; - - union - { - __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ - uint32_t : 30; - } SCALCF_b; - }; - __IM uint32_t RESERVED1[109]; - - union - { - __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection - * Register */ - - struct - { - __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint32_t : 31; - } CAPOAD_b; - }; - - union - { - __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ - - struct - { - __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ - __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ - uint32_t : 24; - } CAPRCR_b; - }; -} R_CACHE_Type; /*!< Size = 520 (0x208) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU System Security Control Unit (R_CPSCU) - */ - -typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ -{ - union - { - __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ - - struct - { - __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ - __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ - __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ - uint32_t : 29; - } CSAR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ - - struct - { - __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ - __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection - * 2 */ - __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ - uint32_t : 29; - } SRAMSAR_b; - }; - - union - { - __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ - - struct - { - __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ - uint32_t : 28; - } STBRAMSAR_b; - }; - __IM uint32_t RESERVED1[6]; - - union - { - __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ - uint32_t : 31; - } DTCSAR_b; - }; - - union - { - __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ - uint32_t : 31; - } DMACSAR_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ - - struct - { - __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ - uint32_t : 16; - } ICUSARA_b; - }; - - union - { - __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ - - struct - { - __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ - uint32_t : 31; - } ICUSARB_b; - }; - - union - { - __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ - - struct - { - __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ - uint32_t : 24; - } ICUSARC_b; - }; - - union - { - __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ - - struct - { - __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ - uint32_t : 31; - } ICUSARD_b; - }; - - union - { - __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ - - struct - { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 2; - __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ - } ICUSARE_b; - }; - - union - { - __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ - - struct - { - __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ - __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ - __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ - __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 3; - __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ - __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ - __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ - __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ - __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ - __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ - __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ - __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ - uint32_t : 17; - } ICUSARF_b; - }; - - union - { - __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ - - struct - { - __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ - __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ - __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ - __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ - __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ - __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ - __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ - uint32_t : 25; - } ICUSARM_b; - }; - __IM uint32_t RESERVED3[5]; - - union - { - __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ - } ICUSARG_b; - }; - - union - { - __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ - } ICUSARH_b; - }; - - union - { - __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ - } ICUSARI_b; - }; - __IM uint32_t RESERVED4[33]; - - union - { - __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ - - struct - { - __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ - uint32_t : 31; - } BUSSARA_b; - }; - - union - { - __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ - - struct - { - __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ - uint32_t : 31; - } BUSSARB_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ - - struct - { - __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ - uint32_t : 31; - } BUSSARC_b; - }; - - union - { - __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ - - struct - { - __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ - uint32_t : 31; - } BUSPARC_b; - }; - __IM uint32_t RESERVED6[6]; - - union - { - __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution - * Register A */ - - struct - { - __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ - uint32_t : 24; - } MMPUSARA_b; - }; - - union - { - __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution - * Register B */ - - struct - { - __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ - uint32_t : 31; - } MMPUSARB_b; - }; - __IM uint32_t RESERVED7[18]; - - union - { - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; - - union - { - __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ - - struct - { - __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ - uint32_t : 31; - } DEBUGSAR_b; - }; - }; - __IM uint32_t RESERVED8[7]; - - union - { - __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ - - struct - { - __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ - uint32_t : 24; - } DMACCHSAR_b; - }; - __IM uint32_t RESERVED9[3]; - - union - { - __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ - - struct - { - __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ - uint32_t : 31; - } CPUDSAR_b; - }; - __IM uint32_t RESERVED10[147]; - - union - { - __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register - * 0 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR0_b; - }; - - union - { - __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register - * 1 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR1_b; - }; - __IM uint32_t RESERVED11[126]; - - union - { - __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ - - struct - { - __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn - * and ELCSRn */ - uint32_t : 31; - } TEVTRCR_b; - }; -} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Consumer Electronics Control (R_CEC) - */ - -typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ -{ - union - { - __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ - - struct - { - __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ - __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device - * 1) */ - __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device - * 2) */ - __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ - __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ - __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ - __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ - __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ - __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ - __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device - * 3) */ - __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ - __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device - * 3) */ - __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ - __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ - __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ - uint16_t : 1; - } CADR_b; - }; - - union - { - __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ - - struct - { - __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ - __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing - * Select */ - __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ - __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ - __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ - __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ - } CECCTL1_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ - - struct - { - __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ - uint16_t : 7; - } STATB_b; - }; - - union - { - __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ - uint16_t : 7; - } STATL_b; - }; - - union - { - __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ - uint16_t : 7; - } LGC0L_b; - }; - - union - { - __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ - uint16_t : 7; - } LGC1L_b; - }; - - union - { - __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ - - struct - { - __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ - uint16_t : 7; - } DATB_b; - }; - - union - { - __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ - - struct - { - __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ - uint16_t : 7; - } NOMT_b; - }; - - union - { - __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ - uint16_t : 7; - } STATLL_b; - }; - - union - { - __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATLH_b; - }; - - union - { - __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ - uint16_t : 7; - } STATBL_b; - }; - - union - { - __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATBH_b; - }; - - union - { - __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LL_b; - }; - - union - { - __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LH_b; - }; - - union - { - __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ - uint16_t : 7; - } LGC1LL_b; - }; - - union - { - __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ - uint16_t : 7; - } LGC1LH_b; - }; - - union - { - __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ - uint16_t : 7; - } DATBL_b; - }; - - union - { - __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ - uint16_t : 7; - } DATBH_b; - }; - - union - { - __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ - - struct - { - __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ - uint16_t : 7; - } NOMP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ - __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ - uint8_t : 1; - __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ - } CECEXMD_b; - }; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ - - struct - { - __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ - __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ - uint8_t : 6; - } CECEXMON_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[10]; - __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ - __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ - - union - { - __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ - - struct - { - __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ - __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ - __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ - __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ - __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ - __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ - __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ - uint8_t : 1; - } CECES_b; - }; - - union - { - __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ - - struct - { - __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ - __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ - __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ - __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ - __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ - uint8_t : 2; - __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ - } CECS_b; - }; - - union - { - __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ - - struct - { - __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ - __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ - __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ - __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ - __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ - __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ - __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ - uint8_t : 1; - } CECFC_b; - }; - - union - { - __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ - - struct - { - __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ - __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ - __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ - __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ - __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ - __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ - } CECCTL0_b; - }; -} R_CEC_Type; /*!< Size = 70 (0x46) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Octa Serial Peripheral Interface (R_OSPI) - */ - -typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ -{ - union - { - __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ - - struct - { - __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ - __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ - uint32_t : 16; - } DCR_b; - }; - - union - { - __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ - - struct - { - __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ - __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ - __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ - __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ - } DAR_b; - }; - - union - { - __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ - - struct - { - __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ - __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ - uint32_t : 3; - __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ - __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ - __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ - __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ - __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ - __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ - __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ - uint32_t : 2; - } DCSR_b; - }; - - union - { - __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ - - struct - { - __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ - __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ - } DSR_b[2]; - }; - - union - { - __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ - - struct - { - __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ - __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ - __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ - __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ - __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ - uint32_t : 4; - } MDTR_b; - }; - - union - { - __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ - - struct - { - __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ - } ACTR_b; - }; - - union - { - __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ - - struct - { - __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ - } ACAR_b[2]; - }; - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ - __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ - __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ - __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ - __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DRCSTR_b; - }; - - union - { - __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ - __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ - __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ - __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ - __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DWCSTR_b; - }; - - union - { - __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ - __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ - __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ - uint32_t : 16; - } DCSTR_b; - }; - - union - { - __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ - - struct - { - __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ - __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ - __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ - __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ - uint32_t : 4; - __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device - * 0 */ - __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device - * 1 */ - __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ - uint32_t : 17; - __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ - } CDSR_b; - }; - - union - { - __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ - - struct - { - __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ - __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ - __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ - __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ - } MDLR_b; - }; - - union - { - __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ - - struct - { - __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ - __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ - __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ - __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ - } MRWCR_b[2]; - }; - - union - { - __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ - - struct - { - __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ - __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ - __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ - __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ - __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ - __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ - __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ - uint32_t : 1; - __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ - __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ - __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ - __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ - __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ - __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ - __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ - uint32_t : 1; - } MRWCSR_b; - }; - - union - { - __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ - - struct - { - __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ - __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ - uint32_t : 16; - } ESR_b; - }; - - union - { - __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ - - struct - { - __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ - } CWNDR_b; - }; - - union - { - __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ - - struct - { - __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ - __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ - __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ - __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ - } CWDR_b; - }; - - union - { - __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ - - struct - { - __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ - __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ - __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ - __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ - } CRR_b; - }; - - union - { - __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ - - struct - { - __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ - __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ - uint32_t : 26; - } ACSR_b; - }; - __IM uint32_t RESERVED1[5]; - - union - { - __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ - - struct - { - __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are - * Low in single continuous write of OctaRAM. */ - uint32_t : 7; - __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 - * are Low in single continuous read of OctaRAM. */ - uint32_t : 7; - } DCSMXR_b; - }; - - union - { - __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating - * size Register */ - - struct - { - __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single - * continuous write of device 0. */ - uint32_t : 5; - __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single - * continuous write of device 1. */ - uint32_t : 5; - } DWSCTSR_b; - }; -} R_OSPI_Type; /*!< Size = 132 (0x84) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 High-Speed Module (R_USB_HS0) - */ - -typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ - uint16_t : 7; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller - * Operation */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit - * when switching from device B to device A in OTGmode. If - * the HNPBTOA bit is 1, the internal function controlremains - * in the Suspend state until the HNP processing endseven - * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } CFIFO_b; - }; - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } D0FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write - * transmit data to the FIFO buffer by accessing these bits. */ - } D1FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-24 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be - * set only in the initial setting (before communications).The - * setting cannot be changed once communication starts. */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency - * can be improved by setting this bit to 1 if no low-speed - * device is connected directly or via FS-HUB to the USB port. */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ - - struct - { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected - * : read-only Host controller selected : read-write */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected - * : read-only Host controller selected : read-write */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected - * : read-only Host controller selected : read-write */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected - * : read-only Host controller selected : read-write */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected - * : read-only Host controller selected : read-write */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * destination function device for control transfer when the - * host controller function is selected. */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - - union - { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ - - struct - { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number - * of the selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - uint16_t : 1; - } PIPEBUF_b; - }; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the selected pipe.A size - * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * peripheral device when the host controller function is - * selected. */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the - * transfer interval timing for the selected pipe as n-th - * power of 2 of the frame timing. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for - * the next transaction of the relevant pipe. */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe - * is being used for the USB bus */ - __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is set for DATA1 */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is cleared to DATA0 */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto - * buffer clear mode for the relevant pipe */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto - * response mode for the relevant pipe. */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO - * buffer status for the relevant pipe in the transmitting - * direction. */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status - * for the relevant pipe. */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED14[11]; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED15[7]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED16[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED17; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ - - struct - { - __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset - * value for adjusting the terminating resistance. */ - uint16_t : 1; - } PHYTRIM1_b; - }; - - union - { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ - - struct - { - __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ - uint16_t : 1; - } PHYTRIM2_b; - }; - __IM uint32_t RESERVED19[3]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; -} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGTX0) - */ - -typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ -{ - union - { - __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ - __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ - }; -} R_AGTX0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CANFD ECC (R_ECCMB0) - */ - -typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ -{ - union - { - __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ - - struct - { - __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ - __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ - __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ - __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ - __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ - __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ - __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ - uint32_t : 2; - __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag - * Clear */ - __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ - __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ - uint32_t : 2; - __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ - __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ - __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ - uint32_t : 14; - } EC710CTL_b; - }; - - union - { - __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ - uint16_t : 5; - __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ - uint16_t : 6; - __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ - } EC710TMC_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ - - struct - { - __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ - } EC710TED_b; - }; - - union - { - __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ - - struct - { - __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ - uint32_t : 22; - } EC710EAD0_b; - }; -} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Flash (R_FLAD) - */ - -typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ -{ - __IM uint8_t RESERVED[64]; - - union - { - __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ - - struct - { - __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ - } FCKMHZ_b; - }; -} R_FLAD_Type; /*!< Size = 65 (0x41) */ - -/** @} */ /* End of group Device_Peripheral_peripherals */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ADC0_BASE 0x40170000UL - #define R_ADC1_BASE 0x40170200UL - #define R_PSCU_BASE 0x400E0000UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40083600UL - #define R_CANFD_BASE 0x400B0000UL - #define R_CRC_BASE 0x40108000UL - #define R_CTSU_BASE 0x400D0000UL - #define R_DAC_BASE 0x40171000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40109000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40082000UL - #define R_ETHERC0_BASE 0x40114100UL - #define R_ETHERC_EDMAC_BASE 0x40114000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GPT0_BASE 0x40169000UL - #define R_GPT1_BASE 0x40169100UL - #define R_GPT2_BASE 0x40169200UL - #define R_GPT3_BASE 0x40169300UL - #define R_GPT4_BASE 0x40169400UL - #define R_GPT5_BASE 0x40169500UL - #define R_GPT6_BASE 0x40169600UL - #define R_GPT7_BASE 0x40169700UL - #define R_GPT8_BASE 0x40169800UL - #define R_GPT9_BASE 0x40169900UL - #define R_GPT10_BASE 0x40169A00UL - #define R_GPT11_BASE 0x40169B00UL - #define R_GPT12_BASE 0x40169C00UL - #define R_GPT13_BASE 0x40169D00UL - #define R_GPT_OPS_BASE 0x40169A00UL - #define R_GPT_POEG0_BASE 0x4008A000UL - #define R_GPT_POEG1_BASE 0x4008A100UL - #define R_GPT_POEG2_BASE 0x4008A200UL - #define R_GPT_POEG3_BASE 0x4008A300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x4009F000UL - #define R_IIC1_BASE 0x4009F100UL - #define R_IIC2_BASE 0x4009F200UL - #define R_IWDT_BASE 0x40083200UL - #define R_I3C0_BASE 0x4011F000UL - #define R_I3C1_BASE 0x4011F400UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40084000UL - #define R_PORT0_BASE 0x40080000UL - #define R_PORT1_BASE 0x40080020UL - #define R_PORT2_BASE 0x40080040UL - #define R_PORT3_BASE 0x40080060UL - #define R_PORT4_BASE 0x40080080UL - #define R_PORT5_BASE 0x400800A0UL - #define R_PORT6_BASE 0x400800C0UL - #define R_PORT7_BASE 0x400800E0UL - #define R_PORT8_BASE 0x40080100UL - #define R_PORT9_BASE 0x40080120UL - #define R_PORT10_BASE 0x40080140UL - #define R_PORT11_BASE 0x40080160UL - #define R_PORT12_BASE 0x40080180UL - #define R_PORT13_BASE 0x400801A0UL - #define R_PORT14_BASE 0x400801C0UL - #define R_PFS_BASE 0x40080800UL - #define R_PMISC_BASE 0x40080D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40083000UL - #define R_SCI0_BASE 0x40118000UL - #define R_SCI1_BASE 0x40118100UL - #define R_SCI2_BASE 0x40118200UL - #define R_SCI3_BASE 0x40118300UL - #define R_SCI4_BASE 0x40118400UL - #define R_SCI5_BASE 0x40118500UL - #define R_SCI6_BASE 0x40118600UL - #define R_SCI7_BASE 0x40118700UL - #define R_SCI8_BASE 0x40118800UL - #define R_SCI9_BASE 0x40118900UL - #define R_SDHI0_BASE 0x40092000UL - #define R_SDHI1_BASE 0x40092400UL - #define R_SPI0_BASE 0x4011A000UL - #define R_SPI1_BASE 0x4011A100UL - #define R_SPI2_BASE 0x40072200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SSI0_BASE 0x4009D000UL - #define R_SSI1_BASE 0x4009D100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x400F3000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_WDT_BASE 0x40083400UL - #define R_TZF_BASE 0x40000E00UL - #define R_CACHE_BASE 0x40007000UL - #define R_CPSCU_BASE 0x40008000UL - #define R_CEC_BASE 0x400AC000UL - #define R_OSPI_BASE 0x400A6000UL - #define R_USB_HS0_BASE 0x40111000UL - #define R_AGTX0_BASE 0x400E8000UL - #define R_AGTX1_BASE 0x400E8100UL - #define R_AGTX2_BASE 0x400E8200UL - #define R_AGTX3_BASE 0x400E8300UL - #define R_AGTX4_BASE 0x400E8400UL - #define R_AGTX5_BASE 0x400E8500UL - #define R_AGTX6_BASE 0x400E8600UL - #define R_AGTX7_BASE 0x400E8700UL - #define R_AGTX8_BASE 0x400E8800UL - #define R_AGTX9_BASE 0x400E8900UL - #define R_ECCMB0_BASE 0x4036F200UL - #define R_ECCMB1_BASE 0x4036F300UL - #define R_FLAD_BASE 0x407FC000UL - #define R_WDT1_BASE 0x40044300UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) - #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) - #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) - #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - #define R_TZF ((R_TZF_Type *) R_TZF_BASE) - #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) - #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) - #define R_CEC ((R_CEC_Type *) R_CEC_BASE) - #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) - #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) - #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) - #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) - #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) - #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) - #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) - #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) - #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) - #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) - #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) - #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) - #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) - #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - -/* ========================================= End of section using anonymous unions ========================================= */ - #if defined(__CC_ARM) - #pragma pop - #elif defined(__ICCARM__) - -/* leave anonymous unions enabled */ - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning restore - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #endif - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_clusters - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ SDRAM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SDCCR ========================================================= */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCMOD ========================================================= */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDAMOD ========================================================= */ - #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ - #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDSELF ========================================================= */ - #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ - #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDRFCR ========================================================= */ - #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ - #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ -/* ======================================================== SDRFEN ========================================================= */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ -/* ========================================================= SDICR ========================================================= */ - #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ - #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SDIR ========================================================== */ - #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ - #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ - #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ - #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ -/* ========================================================= SDADR ========================================================= */ - #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ - #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ -/* ========================================================= SDTR ========================================================== */ - #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ - #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ - #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ - #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ - #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ - #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ -/* ========================================================= SDMOD ========================================================= */ - #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ - #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ -/* ========================================================= SDSR ========================================================== */ - #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ - #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ - #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ - #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= IRQEN ========================================================= */ - #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ - #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ DMACDTCERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FLBI ========================================================== */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== MRE0BI ========================================================= */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S2BI ========================================================== */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S3BI ========================================================== */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== STBYSBI ======================================================== */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= ECBI ========================================================== */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= EOBI ========================================================== */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI0BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI1BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PBBI ========================================================== */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PABI ========================================================== */ - #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PIBI ========================================================== */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PSBI ========================================================== */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU0SAHBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT1 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FHBI ========================================================== */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ======================================================== MRC0BI ========================================================= */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ BMSAERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ - #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ OAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BUSOAD ========================================================= */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSOADPT ======================================================== */ - #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== MSAOAD ========================================================= */ - #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= MSAPT ========================================================= */ - #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ MBWERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ - #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ - #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ - #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ ELSEGR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== BY =========================================================== */ - #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ - #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ - #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ - #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ ELSR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== HA =========================================================== */ - #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ - #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ SAR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== L =========================================================== */ - #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ - #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ -/* =========================================================== U =========================================================== */ - #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ - #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ - #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ REGION ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AC =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ -/* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ GROUP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== EN =========================================================== */ - #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= ENPT ========================================================== */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== RPT ========================================================== */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== RPT_SEC ======================================================== */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================== CTL ========================================================== */ - #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ - #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== SA =========================================================== */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== EA =========================================================== */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ PIN ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= PmnPFS_BY ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ======================================================= PmnPFS_HA ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ -/* ======================================================== PmnPFS ========================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PORT ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PMSAR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PMSAR ========================================================= */ - -/* =========================================================================================================================== */ -/* ================ RTCCR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RTCCR ========================================================= */ - #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ - #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ - #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ - #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RSEC ========================================================== */ - #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ - #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMIN ========================================================== */ - #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ - #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ -/* ========================================================== RHR ========================================================== */ - #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ - #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RDAY ========================================================== */ - #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ - #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMON ========================================================== */ - #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= AGTCR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTMR1 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ -/* ======================================================== AGTMR2 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ -/* ===================================================== AGTIOSEL_ALT ====================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ -/* ======================================================== AGTIOC ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTISR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTCMSR ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ -/* ======================================================= AGTIOSEL ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ AGT16 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ AGT32 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ - -/** @} */ /* End of group PosMask_clusters */ - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ADCSR ========================================================= */ - #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ - #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ - #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ - #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ - #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ - #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ - #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ - #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ - #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ - #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSA ========================================================= */ - #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ - #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADS ========================================================= */ - #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ - #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADC ========================================================= */ - #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ - #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ - #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ -/* ========================================================= ADCER ========================================================= */ - #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ - #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ - #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ - #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ - #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ - #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ - #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ - #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ - #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSTRGR ======================================================== */ - #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ - #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ - #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ - #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ -/* ======================================================== ADEXICR ======================================================== */ - #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ - #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ - #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ - #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ - #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ - #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ - #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ - #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ - #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSB ========================================================= */ - #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ - #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADDBLDR ======================================================== */ - #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ - #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADTSDR ========================================================= */ - #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ - #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADOCDR ========================================================= */ - #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ - #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADRD_RIGHT ======================================================= */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ -/* ======================================================= ADRD_LEFT ======================================================= */ - #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ - #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ========================================================= ADDR ========================================================== */ - #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ - #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADSHCR ========================================================= */ - #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ - #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ - #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ - #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ - #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ -/* ======================================================== ADDISCR ======================================================== */ - #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ - #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ - #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADSHMSR ======================================================== */ - #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ - #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADACSR ========================================================= */ - #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ - #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ -/* ======================================================== ADGSPCR ======================================================== */ - #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ - #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ - #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ - #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ -/* ========================================================= ADICR ========================================================= */ - #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ - #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ -/* ======================================================= ADDBLDRA ======================================================== */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADDBLDRB ======================================================== */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADHVREFCNT ======================================================= */ - #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= ADWINMON ======================================================== */ - #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ - #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ - #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ - #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPCR ======================================================== */ - #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ - #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ - #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ - #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ - #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ - #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ - #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCMPANSER ======================================================= */ - #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ - #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPLER ======================================================== */ - #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ - #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPANSR ======================================================= */ - #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ - #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPLR ======================================================== */ - #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ - #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPDR0 ======================================================== */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPDR1 ======================================================== */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADCMPSR ======================================================== */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPSER ======================================================== */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPBNSR ======================================================= */ - #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ - #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ -/* ======================================================= ADWINLLB ======================================================== */ - #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ - #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADWINULB ======================================================== */ - #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ - #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPBSR ======================================================== */ - #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ - #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSSTRL ======================================================== */ - #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRT ======================================================== */ - #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRO ======================================================== */ - #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTR ========================================================= */ - #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADPGACR ======================================================== */ - #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ - #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ - #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ - #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ - #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ - #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ - #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ - #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ - #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ - #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ - #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ - #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ - #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ - #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ - #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ - #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ - #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADRD ========================================================== */ - #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ -/* ========================================================= ADRST ========================================================= */ - #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ====================================================== VREFAMPCNT ======================================================= */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ - #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCALEXE ======================================================== */ - #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ - #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ - #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANIM ========================================================= */ - #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ - #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGAGS0 ======================================================== */ - #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ - #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= ADPGADCR0 ======================================================= */ - #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ - #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ - #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ - #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ - #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ - #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ - #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ - #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ - #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADREF ========================================================= */ - #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ - #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ - #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ -/* ======================================================== ADEXREF ======================================================== */ - #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ - #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADAMPOFF ======================================================== */ - #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ - #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ -/* ======================================================== ADTSTPR ======================================================== */ - #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ - #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ - #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================= ADDDACER ======================================================== */ - #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ - #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ - #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ - #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADEXTSTR ======================================================== */ - #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ - #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ - #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ - #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ -/* ======================================================== ADTSTRA ======================================================== */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ - #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ - #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADTSTRB ======================================================== */ - #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ - #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ -/* ======================================================== ADTSTRC ======================================================== */ - #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ - #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ - #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ADTSTRD ======================================================== */ - #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ - #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR0 ======================================================= */ - #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ - #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR1 ======================================================= */ - #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ - #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR2 ======================================================= */ - #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ - #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSWCR ========================================================= */ - #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ - #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ - #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ -/* ======================================================== ADGSCS ========================================================= */ - #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ - #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ - #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ -/* ========================================================= ADSER ========================================================= */ - #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ - #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ -/* ======================================================== ADBUF0 ========================================================= */ - #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF1 ========================================================= */ - #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF2 ========================================================= */ - #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF3 ========================================================= */ - #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF4 ========================================================= */ - #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF5 ========================================================= */ - #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF6 ========================================================= */ - #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF7 ========================================================= */ - #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF8 ========================================================= */ - #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF9 ========================================================= */ - #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF10 ======================================================== */ - #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF11 ======================================================== */ - #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF12 ======================================================== */ - #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF13 ======================================================== */ - #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF14 ======================================================== */ - #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF15 ======================================================== */ - #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUFEN ======================================================== */ - #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ - #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADBUFPTR ======================================================== */ - #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ - #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ - #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS0 ======================================================= */ - #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS1 ======================================================= */ - #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADREFMON ======================================================== */ - #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ - #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ - #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ - #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ - #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ - #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ - #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ - #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ - #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ - #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ - #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ - #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ - #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ - #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ - #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ - #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ - #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ - #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ - #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ - #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ - #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ - #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ - #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ - #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ - #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ - #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ - #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ - #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ - #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ -/* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ - #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ - #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ - #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ -/* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ -/* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ -/* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ - #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ -/* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ - #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSMABT ======================================================== */ - #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSDIVBYP ======================================================= */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSTHRPUT ======================================================= */ - #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ - #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CACR0 ========================================================= */ - #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ - #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR1 ========================================================= */ - #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ - #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ - #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ - #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR2 ========================================================= */ - #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ - #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ - #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ - #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ - #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ -/* ========================================================= CAICR ========================================================= */ - #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ - #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ - #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ - #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ - #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ - #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ - #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ -/* ========================================================= CASTR ========================================================= */ - #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ - #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ - #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ - #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ -/* ======================================================== CAULVR ========================================================= */ - #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ - #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CALLVR ========================================================= */ - #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ - #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CACNTBR ======================================================== */ - #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ - #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CRCCR0 ========================================================= */ - #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ - #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ - #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ - #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ -/* ======================================================== CRCCR1 ========================================================= */ - #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ - #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ - #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CRCDIR ========================================================= */ - #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ - #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDIR_BY ======================================================= */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCDOR ========================================================= */ - #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ - #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDOR_HA ======================================================= */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ -/* ======================================================= CRCDOR_BY ======================================================= */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCSAR ========================================================= */ - #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ - #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTSUCR0 ======================================================== */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ -/* ======================================================== CTSUCR1 ======================================================== */ - #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ - #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ - #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUSDPRS ======================================================= */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSST ======================================================== */ - #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ - #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ -/* ======================================================= CTSUMCH0 ======================================================== */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUMCH1 ======================================================== */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUCHAC ======================================================== */ - #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUCHTRC ======================================================= */ - #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUDCLKC ======================================================= */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== CTSUST ========================================================= */ - #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ - #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ - #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ - #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ - #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ - #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ -/* ======================================================== CTSUSSC ======================================================== */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSO0 ======================================================== */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ - #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ - #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ -/* ======================================================== CTSUSO1 ======================================================== */ - #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ - #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ -/* ======================================================== CTSUSC ========================================================= */ - #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ - #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ -/* ======================================================== CTSURC ========================================================= */ - #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ - #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ -/* ======================================================= CTSUERRS ======================================================== */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUTRMR ======================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DACR ========================================================== */ - #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ - #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ - #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ - #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ -/* ========================================================= DADR ========================================================== */ - #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ - #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DADPR ========================================================= */ - #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ - #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADSCR ======================================================== */ - #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ - #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ -/* ======================================================= DAVREFCR ======================================================== */ - #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ - #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ -/* ========================================================= DAPC ========================================================== */ - #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ - #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== DAAMPCR ======================================================== */ - #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ - #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DAASWCR ======================================================== */ - #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ - #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ - #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ - #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== DBGSTR ========================================================= */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ -/* ======================================================= DBGSTOPCR ======================================================= */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ -/* ======================================================= FSBLSTAT ======================================================== */ - #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ - #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ -/* ======================================================== DMECHR ========================================================= */ - #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ - #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ - #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ - #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ - #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ -/* ========================================================= DELSR ========================================================= */ - #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMSAR ========================================================= */ - #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ - #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMDAR ========================================================= */ - #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ - #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCRA ========================================================= */ - #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ - #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ - #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ - #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMCRB ========================================================= */ - #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ - #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ - #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMTMD ========================================================= */ - #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ - #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ - #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ - #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ - #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ - #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ -/* ========================================================= DMINT ========================================================= */ - #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ - #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ - #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ - #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ - #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ - #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMAMD ========================================================= */ - #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ - #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ - #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ - #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ - #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ - #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ - #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ -/* ========================================================= DMOFR ========================================================= */ - #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ - #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCNT ========================================================= */ - #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ - #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMREQ ========================================================= */ - #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ - #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ - #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSTS ========================================================= */ - #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ - #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ - #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ - #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSRR ========================================================= */ -/* ========================================================= DMDRR ========================================================= */ -/* ========================================================= DMSBS ========================================================= */ - #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ - #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ - #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMDBS ========================================================= */ - #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ - #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ - #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMBWR ========================================================= */ - #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ - #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DOCR ========================================================== */ - #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ - #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ - #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ - #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ - #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ -/* ========================================================= DODIR ========================================================= */ - #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ - #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DODSR ========================================================= */ - #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ - #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= DTCADMOD ======================================================== */ - #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ - #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ -/* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ -/* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ====================================================== DTCVBR_SEC ======================================================= */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DTCDISP ======================================================== */ - #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ - #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCIBR ========================================================= */ - #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ - #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ -/* ========================================================= DTCOR ========================================================= */ - #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ - #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSQE ========================================================= */ - #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ - #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARA ======================================================== */ - #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ - #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ - #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ - #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARB ======================================================== */ - #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ - #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ - #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ - #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ - #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ - #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ - #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ - #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ - #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ - #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ - #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ - #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ - #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ - #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ - #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ - #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ - #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARC ======================================================== */ - #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ - #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ - #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ - #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ECMR ========================================================== */ - #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ - #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ - #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ - #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ - #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ - #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ - #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ - #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ - #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ - #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ - #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ - #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ - #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ -/* ========================================================= RFLR ========================================================== */ - #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ - #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ - #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ - #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ - #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ - #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ - #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ -/* ======================================================== ECSIPR ========================================================= */ - #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ - #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ - #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ - #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ -/* ========================================================== PIR ========================================================== */ - #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ - #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ - #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ - #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ - #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ -/* ========================================================== PSR ========================================================== */ - #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ - #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ -/* ========================================================= RDMLR ========================================================= */ - #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ - #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ -/* ========================================================= IPGR ========================================================== */ - #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ - #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ -/* ========================================================== APR ========================================================== */ - #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ - #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ -/* ========================================================== MPR ========================================================== */ - #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ - #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFCF ========================================================== */ - #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ - #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ -/* ======================================================== TPAUSER ======================================================== */ - #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ - #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ -/* ======================================================= TPAUSECR ======================================================== */ -/* ========================================================= BCFRR ========================================================= */ - #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ - #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ -/* ========================================================= MAHR ========================================================== */ - #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ - #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MALR ========================================================== */ - #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ - #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ -/* ========================================================= TROCR ========================================================= */ - #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ - #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CDCR ========================================================== */ -/* ========================================================= LCCR ========================================================== */ - #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ - #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CNDCR ========================================================= */ - #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ - #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CEFCR ========================================================= */ - #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ - #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= FRECR ========================================================= */ - #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ - #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TSFRCR ========================================================= */ - #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ - #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TLFRCR ========================================================= */ - #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ - #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RFCR ========================================================== */ - #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ - #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MAFCR ========================================================= */ - #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ - #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= EDMR ========================================================== */ - #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ - #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ - #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDTRR ========================================================= */ - #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ - #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDRRR ========================================================= */ - #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ - #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ -/* ========================================================= TDLAR ========================================================= */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDLAR ========================================================= */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= EESR ========================================================== */ - #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ - #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ - #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ - #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ - #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ - #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ - #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ - #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ - #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ - #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ - #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ - #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ - #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ - #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ - #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ - #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ - #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ -/* ======================================================== EESIPR ========================================================= */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ -/* ======================================================== TRSCER ========================================================= */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ -/* ========================================================= RMFCR ========================================================= */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= TFTR ========================================================== */ - #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ - #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ -/* ========================================================== FDR ========================================================== */ - #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ - #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ - #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ - #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ -/* ========================================================= RMCR ========================================================== */ - #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ - #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ -/* ========================================================= TFUCR ========================================================= */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFOCR ========================================================= */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ -/* ========================================================= IOSR ========================================================== */ - #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ - #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ -/* ========================================================= FCFTR ========================================================= */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ -/* ======================================================== RPADIR ========================================================= */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ -/* ========================================================= TRIMD ========================================================= */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ -/* ========================================================= RBWAR ========================================================= */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDFAR ========================================================= */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TBRAR ========================================================= */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TDFAR ========================================================= */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/* ====================================================== FACI_CMD16 ======================================================= */ -/* ======================================================= FACI_CMD8 ======================================================= */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ -/* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FMEPROT ======================================================== */ - #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ - #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT0 ======================================================== */ - #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ - #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT1 ======================================================== */ - #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ - #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ - #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ - #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ - #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ -/* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ -/* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ -/* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ -/* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ -/* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ -/* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== FBCADDR ======================================================== */ - #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ - #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ -/* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ -/* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ -/* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ -/* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ -/* ======================================================= FCNTSELR ======================================================== */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ -/* ====================================================== FCNTDATAR0 ======================================================= */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FCNTDATAR1 ======================================================= */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ -/* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ -/* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ -/* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ - #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ - #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ - #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ - #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= GTWP ========================================================== */ - #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ - #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ - #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ - #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ - #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTR ========================================================= */ - #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ - #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTP ========================================================= */ - #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ - #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCLR ========================================================= */ - #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ - #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSSR ========================================================= */ - #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ - #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ - #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ - #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ - #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ - #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ - #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ - #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ - #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ - #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ - #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ - #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ - #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTPSR ========================================================= */ - #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ - #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ - #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ - #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ - #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ - #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ - #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ - #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ - #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ - #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ - #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ - #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ - #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCSR ========================================================= */ - #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ - #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ - #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ - #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ - #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ - #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ - #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ - #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ - #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ - #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ - #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ - #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ - #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ - #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ - #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTUPSR ========================================================= */ - #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ - #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ - #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ - #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ - #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ - #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ - #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ - #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ - #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ - #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ - #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ - #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ - #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTDNSR ========================================================= */ - #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ - #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ - #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ - #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ - #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ - #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ - #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ - #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ - #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ - #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ - #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ - #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ - #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICASR ======================================================== */ - #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ - #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ - #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ - #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ - #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ - #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ - #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ - #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ - #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ - #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ - #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ - #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ - #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICBSR ======================================================== */ - #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ - #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ - #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ - #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ - #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ - #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ - #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ - #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ - #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ - #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ - #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ - #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ - #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ - #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ - #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ - #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ - #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ - #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ - #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ - #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ - #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ - #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ - #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ -/* ======================================================= GTUDDTYC ======================================================== */ - #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ - #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ - #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ - #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ - #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ - #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ - #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ - #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ -/* ========================================================= GTIOR ========================================================= */ - #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ - #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ - #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ - #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ - #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ - #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ - #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ - #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ - #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ - #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ - #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ - #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ - #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ - #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ - #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ - #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ - #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ - #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ - #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTINTAD ======================================================== */ - #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ - #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ - #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ - #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ - #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ - #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ - #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ - #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ - #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ - #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ - #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ - #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTST ========================================================== */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ - #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ - #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ - #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ - #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ - #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ - #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ - #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ - #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ - #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ - #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ - #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ - #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ - #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ - #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ - #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ - #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ - #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ - #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTBER ========================================================= */ - #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ - #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ - #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ - #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ - #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ - #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ - #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ - #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ - #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ - #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ - #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ - #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ - #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ - #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ -/* ========================================================= GTITC ========================================================= */ - #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ - #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ - #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ - #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ - #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ - #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ - #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ - #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ - #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ - #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ - #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCNT ========================================================= */ - #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ - #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTCCR ========================================================= */ - #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ - #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPR ========================================================== */ - #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ - #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPBR ========================================================= */ - #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ - #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTPDBR ========================================================= */ - #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ - #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRA ======================================================== */ - #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ - #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRB ======================================================== */ - #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ - #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRA ======================================================== */ - #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ - #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRB ======================================================== */ - #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ - #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRA ======================================================= */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRB ======================================================= */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTDTCR ========================================================= */ - #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ - #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ - #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ - #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ - #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ -/* ========================================================= GTDVU ========================================================= */ - #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDVD ========================================================= */ - #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ - #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBU ========================================================= */ - #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBD ========================================================= */ - #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ - #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTSOS ========================================================= */ - #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ - #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ -/* ======================================================== GTSOTR ========================================================= */ - #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ - #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTADSMR ======================================================== */ - #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ - #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ - #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ - #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ - #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTEITC ========================================================= */ - #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ - #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ - #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ - #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ - #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ - #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ - #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ - #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= GTEITLI1 ======================================================== */ - #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ - #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ - #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ - #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ - #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ - #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ - #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ - #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ - #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ -/* ======================================================= GTEITLI2 ======================================================== */ - #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ - #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ - #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ -/* ======================================================== GTEITLB ======================================================== */ - #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ - #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ - #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ - #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ - #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ - #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ - #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ - #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ -/* ======================================================== GTICLF ========================================================= */ - #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ - #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ - #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ - #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ - #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ - #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ -/* ========================================================= GTPC ========================================================== */ - #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ - #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ - #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ - #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ -/* ======================================================= GTADCMSC ======================================================== */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ - #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ - #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ -/* ======================================================= GTADCMSS ======================================================== */ - #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ - #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ -/* ======================================================== GTSECSR ======================================================== */ - #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ - #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ - #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ - #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ - #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ - #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ - #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ - #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ - #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ - #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ - #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTSECR ========================================================= */ - #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ - #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ - #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ - #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ - #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ - #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ - #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ - #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ - #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ - #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ - #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ - #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ - #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ -/* ======================================================== GTBER2 ========================================================= */ - #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ - #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ - #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ - #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ - #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ - #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ - #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ - #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ - #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ - #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ - #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ - #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ - #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ - #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ - #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ - #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ - #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ - #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ - #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ - #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ - #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ -/* ======================================================== GTOLBR ========================================================= */ - #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ - #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ - #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTICCR ========================================================= */ - #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ - #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ - #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ - #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ - #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ - #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ - #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ - #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ - #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ - #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ - #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ - #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ - #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ - #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ - #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ - #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ - #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ - #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ - #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ - #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ - #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= OPSCR ========================================================= */ - #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ - #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ - #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ - #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ - #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ - #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ - #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ - #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ - #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ - #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ - #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ - #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ - #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ - #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ - #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ -/* ======================================================== GTONCWP ======================================================== */ - #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== GTONCCR ======================================================== */ - #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ - #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ - #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ - #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ - #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ - #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ -/* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ -/* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ -/* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ -/* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ -/* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN2 ========================================================= */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ICCR1 ========================================================= */ - #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ - #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ - #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ - #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ - #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ - #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ - #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ - #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ - #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ -/* ========================================================= ICCR2 ========================================================= */ - #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ - #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ - #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ - #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ - #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ - #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ - #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR1 ========================================================= */ - #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ - #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ - #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ - #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ -/* ========================================================= ICMR2 ========================================================= */ - #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ - #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ - #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ - #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ - #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ - #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR3 ========================================================= */ - #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ - #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ - #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ - #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ - #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ - #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ - #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ - #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ -/* ========================================================= ICFER ========================================================= */ - #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ - #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ - #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ - #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ - #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ - #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ - #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ - #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ - #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSER ========================================================= */ - #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ - #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ - #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ - #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ - #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ - #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ - #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ -/* ========================================================= ICIER ========================================================= */ - #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ - #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ - #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ - #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ - #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ - #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ - #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ - #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR1 ========================================================= */ - #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ - #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ - #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ - #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ - #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ - #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ - #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR2 ========================================================= */ - #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ - #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ - #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ - #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ - #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ - #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ - #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ -/* ========================================================= ICBRL ========================================================= */ - #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ - #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICBRH ========================================================= */ - #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ - #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICDRT ========================================================= */ - #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ - #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ -/* ========================================================= ICDRR ========================================================= */ - #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ - #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ -/* ========================================================= ICWUR ========================================================= */ - #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ - #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ - #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ - #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ - #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ - #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICWUR2 ========================================================= */ - #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ - #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ - #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ - #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== IWDTRR ========================================================= */ - #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ - #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ -/* ======================================================== IWDTCR ========================================================= */ - #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ======================================================== IWDTSR ========================================================= */ - #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== IWDTRCR ======================================================== */ - #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= IWDTCSTPR ======================================================= */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PRTS ========================================================== */ - #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ - #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ -/* ========================================================= CECTL ========================================================= */ - #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ - #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ -/* ========================================================= BCTL ========================================================== */ - #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ - #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ - #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ - #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ - #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ - #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ - #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSDVAD ========================================================= */ - #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ - #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ - #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTCTL ========================================================= */ - #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ - #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ - #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ - #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ - #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ - #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ - #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ - #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ - #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ - #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ - #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ - #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ - #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ -/* ========================================================= PRSST ========================================================= */ - #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ - #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ - #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ - #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ -/* ========================================================= INST ========================================================== */ - #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ - #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ -/* ========================================================= INSTE ========================================================= */ - #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ - #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ -/* ========================================================= INIE ========================================================== */ - #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ - #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== INSTFC ========================================================= */ - #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ - #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= DVCT ========================================================== */ - #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ - #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ -/* ======================================================== IBINCTL ======================================================== */ - #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ - #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ - #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ -/* ========================================================= BFCTL ========================================================= */ - #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ - #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ - #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ - #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ - #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ - #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ - #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ - #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ -/* ========================================================= SVCTL ========================================================= */ - #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ - #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ - #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ - #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ - #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ -/* ======================================================= REFCKCTL ======================================================== */ - #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ - #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ -/* ========================================================= STDBR ========================================================= */ - #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ - #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ - #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ - #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ - #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ - #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ -/* ========================================================= EXTBR ========================================================= */ - #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ - #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ - #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ - #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ - #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ -/* ======================================================== BFRECDT ======================================================== */ - #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ - #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BAVLCDT ======================================================== */ - #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ - #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BIDLCDT ======================================================== */ - #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ - #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== OUTCTL ========================================================= */ - #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ - #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ - #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ - #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ - #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ - #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ - #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ - #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ -/* ========================================================= INCTL ========================================================= */ - #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ - #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ - #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ - #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ -/* ======================================================== TMOCTL ========================================================= */ - #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ - #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ - #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ - #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ - #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ - #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ -/* ========================================================= WUCTL ========================================================= */ - #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ - #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ - #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ - #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ - #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ -/* ======================================================== ACKCTL ========================================================= */ - #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ - #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ - #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ - #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTRCTL ======================================================== */ - #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ - #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ - #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTLCTL ======================================================== */ - #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ - #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ - #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ - #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ - #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ - #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ - #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SVTDLG0 ======================================================== */ - #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ - #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= STCTL ========================================================= */ - #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ - #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ATCTL ========================================================= */ - #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ - #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ - #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ - #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ - #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ -/* ========================================================= ATTRG ========================================================= */ - #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ - #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== ATCCNTE ======================================================== */ - #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ - #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ -/* ======================================================== CNDCTL ========================================================= */ - #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ - #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ - #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ - #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ -/* ======================================================== NCMDQP ========================================================= */ -/* ======================================================== NRSPQP ========================================================= */ -/* ======================================================== NTDTBP0 ======================================================== */ -/* ======================================================== NIBIQP ========================================================= */ -/* ========================================================= NRSQP ========================================================= */ -/* ======================================================== HCMDQP ========================================================= */ - #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ - #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HRSPQP ========================================================= */ - #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ - #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HTDTBP ========================================================= */ - #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ - #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== NQTHCTL ======================================================== */ - #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ - #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= NTBTHCTL0 ======================================================= */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ======================================================= NRQTHCTL ======================================================== */ - #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ - #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ -/* ======================================================== HQTHCTL ======================================================== */ - #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= HTBTHCTL ======================================================== */ - #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ========================================================== BST ========================================================== */ - #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ - #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ - #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ - #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ - #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ - #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ - #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ - #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ - #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTE ========================================================== */ - #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ - #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ - #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ - #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ - #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ - #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ - #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ - #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ - #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ -/* ========================================================== BIE ========================================================== */ - #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ - #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ - #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ - #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ - #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ - #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ - #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ - #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ - #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTFC ========================================================= */ - #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ - #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ - #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ - #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ - #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ - #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ - #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ - #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ - #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= NTST ========================================================== */ - #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ - #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ - #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ - #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ - #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ -/* ========================================================= NTSTE ========================================================= */ - #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ - #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ - #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ - #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ - #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ -/* ========================================================= NTIE ========================================================== */ - #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ - #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ - #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ - #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ - #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ -/* ======================================================== NTSTFC ========================================================= */ - #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ - #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ - #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ - #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ -/* ========================================================= HTST ========================================================== */ - #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ - #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ - #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ -/* ========================================================= HTSTE ========================================================= */ - #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ - #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ - #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ -/* ========================================================= HTIE ========================================================== */ - #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ - #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ - #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== HTSTFC ========================================================= */ - #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ - #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ - #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= BCST ========================================================== */ - #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ - #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ - #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ - #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ -/* ========================================================= SVST ========================================================== */ - #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ - #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ - #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ - #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ - #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ -/* ========================================================= WUST ========================================================== */ - #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ - #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ -/* ======================================================== MRCCPT ========================================================= */ - #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ - #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DATBAS0 ======================================================== */ - #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS1 ======================================================== */ - #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS2 ======================================================== */ - #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS3 ======================================================== */ - #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS4 ======================================================== */ - #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS5 ======================================================== */ - #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS6 ======================================================== */ - #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS7 ======================================================== */ - #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= EXDATBAS ======================================================== */ - #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ - #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ - #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ - #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ - #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= SDATBAS0 ======================================================== */ - #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS1 ======================================================== */ - #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS2 ======================================================== */ - #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================== MSDCT0 ========================================================= */ - #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT1 ========================================================= */ - #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT2 ========================================================= */ - #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT3 ========================================================= */ - #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT4 ========================================================= */ - #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT5 ========================================================= */ - #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT6 ========================================================= */ - #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT7 ========================================================= */ - #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ========================================================= SVDCT ========================================================= */ - #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ - #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ - #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ - #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ - #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ - #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ - #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ - #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================= SDCTPIDL ======================================================== */ -/* ======================================================= SDCTPIDH ======================================================== */ -/* ======================================================== SVDVAD0 ======================================================== */ - #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD1 ======================================================== */ - #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD2 ======================================================== */ - #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== CSECMD ========================================================= */ - #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ - #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ - #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ - #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ -/* ======================================================== CEACTST ======================================================== */ - #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ - #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CMWLG ========================================================= */ - #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ - #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= CMRLG ========================================================= */ - #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ - #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ - #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ - #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ -/* ======================================================== CETSTMD ======================================================== */ - #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ - #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ -/* ======================================================== CGDVST ========================================================= */ - #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ - #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ - #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ - #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ - #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ - #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ - #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ -/* ======================================================== CMDSPW ========================================================= */ - #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ - #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPR ========================================================= */ - #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ - #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ - #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ - #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPT ========================================================= */ - #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ - #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ - #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ - #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ -/* ========================================================= CETSM ========================================================= */ - #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ - #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ - #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ - #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ - #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ - #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ - #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ -/* ========================================================= CETSS ========================================================= */ - #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ - #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ - #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ - #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ - #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ -/* ======================================================= CGHDRCAP ======================================================== */ - #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ - #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ - #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ - #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BITCNT ========================================================= */ - #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ - #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ - #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ - #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ -/* ======================================================== NQSTLV ========================================================= */ - #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ - #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ - #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ - #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================= NDBSTLV0 ======================================================== */ - #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================= NRSQSTLV ======================================================== */ - #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ - #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HQSTLV ========================================================= */ - #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ - #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HDBSTLV ======================================================== */ - #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================== PRSTDBG ======================================================== */ - #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ - #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ - #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ - #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ - #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ -/* ======================================================= MSERRCNT ======================================================== */ - #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ - #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ -/* ======================================================== SC1CPT ========================================================= */ - #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ - #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ -/* ======================================================== SC2CPT ========================================================= */ - #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ - #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= OADPT ========================================================= */ - #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== MSTPCRA ======================================================== */ - #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRB ======================================================== */ - #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ - #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRC ======================================================== */ - #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ - #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRD ======================================================== */ - #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ - #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRE ======================================================== */ - #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ - #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ -/* ======================================================= LSMRWDIS ======================================================== */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ - #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PODR ========================================================== */ - #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ========================================================== PDR ========================================================== */ - #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EIDR ========================================================== */ - #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ - #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ -/* ========================================================= PIDR ========================================================== */ - #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PORR ========================================================== */ - #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ - #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ -/* ========================================================= POSR ========================================================== */ - #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EORR ========================================================== */ - #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ - #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ -/* ========================================================= EOSR ========================================================== */ - #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PFENET ========================================================= */ - #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ - #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ - #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ - #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================== PRWCNTR ======================================================== */ - #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ - #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SFMSMD ========================================================= */ - #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ - #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ - #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ - #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ - #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ - #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ - #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ - #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ - #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ - #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ - #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ -/* ======================================================== SFMSSC ========================================================= */ - #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ - #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ - #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ - #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSKC ========================================================= */ - #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ - #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ - #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMSST ========================================================= */ - #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ - #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ - #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ - #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMCOM ========================================================= */ - #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ - #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMCMD ========================================================= */ - #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ - #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCST ========================================================= */ - #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ - #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ - #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMSIC ========================================================= */ - #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ - #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMSAC ========================================================= */ - #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ - #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ - #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMSDC ========================================================= */ - #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ - #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ - #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ - #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ - #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ - #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSPC ========================================================= */ - #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ - #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ - #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMPMD ========================================================= */ - #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ - #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCNT1 ======================================================== */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ - #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ - #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ - #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECCNT ======================================================== */ - #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ - #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINCNT ======================================================== */ - #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ - #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ -/* ======================================================== RHRCNT ========================================================= */ - #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ - #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ -/* ======================================================== RWKCNT ========================================================= */ - #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================== RDAYCNT ======================================================== */ - #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RMONCNT ======================================================== */ - #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RYRCNT ========================================================= */ - #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT0AR ======================================================== */ - #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ - #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECAR ========================================================= */ - #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT1AR ======================================================== */ - #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ - #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINAR ========================================================= */ - #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT2AR ======================================================== */ - #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ - #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RHRAR ========================================================= */ - #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT3AR ======================================================== */ - #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ - #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RWKAR ========================================================= */ - #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================= BCNT0AER ======================================================== */ - #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RDAYAR ========================================================= */ - #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT1AER ======================================================== */ - #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RMONAR ========================================================= */ - #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT2AER ======================================================== */ - #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ========================================================= RYRAR ========================================================= */ - #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT3AER ======================================================== */ - #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RYRAREN ======================================================== */ - #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR1 ========================================================== */ - #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ - #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ - #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ - #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ - #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ - #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ - #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR2 ========================================================== */ - #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ - #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ - #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ - #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ - #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ - #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ - #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ - #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ - #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR4 ========================================================== */ - #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ - #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ - #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRH ========================================================== */ - #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ - #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRL ========================================================== */ - #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= RADJ ========================================================== */ - #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ - #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ - #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ - #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ -/* ========================================================= RADJ2 ========================================================= */ - #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ - #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SMR ========================================================== */ - #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ - #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ - #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ - #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ======================================================= SMR_SMCI ======================================================== */ - #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ - #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ - #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ - #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ - #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ========================================================== BRR ========================================================== */ - #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ - #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ -/* ========================================================== SCR ========================================================== */ - #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ======================================================= SCR_SMCI ======================================================== */ - #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ========================================================== TDR ========================================================== */ - #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ - #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ -/* ========================================================== SSR ========================================================== */ - #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_FIFO ======================================================== */ - #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ - #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ - #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_MANC ======================================================== */ - #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ - #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_SMCI ======================================================== */ - #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ - #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ========================================================== RDR ========================================================== */ - #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ - #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ -/* ========================================================= SCMR ========================================================== */ - #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ - #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ - #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ - #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ - #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ - #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ -/* ========================================================= SEMR ========================================================== */ - #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ - #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ - #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ - #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ - #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ - #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ - #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ - #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ - #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= SNFR ========================================================== */ - #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ - #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ -/* ========================================================= SIMR1 ========================================================= */ - #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ - #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ - #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ - #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR2 ========================================================= */ - #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ - #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ - #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ - #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR3 ========================================================= */ - #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ - #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ - #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ - #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ - #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ - #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SISR ========================================================== */ - #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ - #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ -/* ========================================================= SPMR ========================================================== */ - #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ - #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ - #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ - #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ - #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ - #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ - #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ - #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ -/* ========================================================= TDRHL ========================================================= */ - #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ - #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FTDRHL ========================================================= */ - #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ -/* ========================================================= FTDRH ========================================================= */ - #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ - #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ - #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FTDRL ========================================================= */ - #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ - #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= RDRHL ========================================================= */ - #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ - #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FRDRHL ========================================================= */ - #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ - #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ - #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ - #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ - #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ - #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ -/* ======================================================= TDRHL_MAN ======================================================= */ - #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ -/* ======================================================= RDRHL_MAN ======================================================= */ - #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRH ========================================================= */ - #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ - #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ - #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRL ========================================================= */ - #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ - #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= MDDR ========================================================== */ - #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ - #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ -/* ========================================================= DCCR ========================================================== */ - #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ - #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ - #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ - #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ - #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ - #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ -/* ========================================================== FCR ========================================================== */ - #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ - #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ - #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ - #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ - #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ - #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ - #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ - #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ -/* ========================================================== FDR ========================================================== */ - #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ - #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ - #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ - #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ -/* ========================================================== LSR ========================================================== */ - #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ - #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ - #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ - #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ -/* ========================================================== CDR ========================================================== */ - #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ - #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ -/* ========================================================= SPTR ========================================================== */ - #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ - #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ - #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ - #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ - #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ - #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ - #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ - #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ACTR ========================================================== */ - #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ - #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ - #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ - #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ - #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ - #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ -/* ========================================================= ESMER ========================================================= */ - #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ - #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR0 ========================================================== */ - #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ - #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ - #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ - #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR1 ========================================================== */ - #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ - #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ - #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ - #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ - #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ - #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ -/* ========================================================== CR2 ========================================================== */ - #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ - #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ - #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ - #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ - #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ -/* ========================================================== CR3 ========================================================== */ - #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ - #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ -/* ========================================================== PCR ========================================================== */ - #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ - #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ - #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ - #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ -/* ========================================================== ICR ========================================================== */ - #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ - #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ - #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ - #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ - #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ - #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ - #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ - #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ - #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ - #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ - #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ - #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ - #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ -/* ========================================================= STCR ========================================================== */ - #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ - #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ - #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ - #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ - #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ - #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ - #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0DR ========================================================= */ -/* ========================================================= CF0CR ========================================================= */ - #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ - #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ - #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ - #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ - #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ - #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ - #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ - #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ - #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0RR ========================================================= */ -/* ======================================================== PCF1DR ========================================================= */ -/* ======================================================== SCF1DR ========================================================= */ -/* ========================================================= CF1CR ========================================================= */ - #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ - #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ - #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ - #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ - #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ - #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ - #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ - #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ - #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF1RR ========================================================= */ -/* ========================================================== TCR ========================================================== */ - #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ - #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ -/* ========================================================== TMR ========================================================== */ - #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ - #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ - #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ - #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ - #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ -/* ========================================================= TPRE ========================================================== */ -/* ========================================================= TCNT ========================================================== */ -/* ======================================================= SCIMSKEN ======================================================== */ - #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ - #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== MMR ========================================================== */ - #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ - #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ - #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ - #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ - #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ - #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ - #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ - #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ -/* ========================================================= TMPR ========================================================== */ - #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ - #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ - #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= RMPR ========================================================== */ - #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ - #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ - #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= MESR ========================================================== */ - #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ - #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ - #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ - #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ -/* ========================================================= MECR ========================================================== */ - #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ - #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ - #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ - #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SD_CMD ========================================================= */ - #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ - #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ - #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ - #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ - #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ - #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ - #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ - #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ -/* ======================================================== SD_ARG ========================================================= */ - #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ - #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_ARG1 ======================================================== */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== SD_STOP ======================================================== */ - #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ - #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ - #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_SECCNT ======================================================= */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SD_RSP10 ======================================================== */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP1 ======================================================== */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP32 ======================================================== */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP3 ======================================================== */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP54 ======================================================== */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP5 ======================================================== */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP76 ======================================================== */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ -/* ======================================================== SD_RSP7 ======================================================== */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ -/* ======================================================= SD_INFO1 ======================================================== */ - #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ - #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ - #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ - #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_INFO2 ======================================================== */ - #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ - #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ - #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ - #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ - #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ - #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ - #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ - #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ - #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ - #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ - #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ - #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO1_MASK ===================================================== */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO2_MASK ===================================================== */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_CLK_CTRL ====================================================== */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ -/* ======================================================== SD_SIZE ======================================================== */ - #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ - #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= SD_OPTION ======================================================= */ - #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ - #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ - #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ - #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ - #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ -/* ====================================================== SD_ERR_STS1 ====================================================== */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_ERR_STS2 ====================================================== */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SD_BUF0 ======================================================== */ - #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ - #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SDIO_MODE ======================================================= */ - #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ - #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ - #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ - #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SDIO_INFO1 ======================================================= */ - #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ -/* ==================================================== SDIO_INFO1_MASK ==================================================== */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_DMAEN ======================================================== */ - #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ - #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ -/* ======================================================= SOFT_RST ======================================================== */ - #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ - #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ -/* ======================================================= SDIF_MODE ======================================================= */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ -/* ======================================================= EXT_SWAP ======================================================== */ - #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ - #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SPCR ========================================================== */ - #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ - #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ - #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ - #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ - #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ - #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ - #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ - #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ - #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ -/* ========================================================= SSLP ========================================================== */ - #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ - #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ - #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ - #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ - #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ - #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ - #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ - #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ - #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPCR ========================================================= */ - #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ - #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ - #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ - #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ - #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSR ========================================================== */ - #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ - #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ - #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ - #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ - #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ - #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ - #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ - #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ - #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ -/* ========================================================= SPDR ========================================================== */ -/* ======================================================== SPDR_HA ======================================================== */ -/* ======================================================== SPDR_BY ======================================================== */ -/* ========================================================= SPSCR ========================================================= */ - #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ - #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ -/* ========================================================= SPBR ========================================================== */ - #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ - #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ -/* ========================================================= SPDCR ========================================================= */ - #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ - #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ - #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ - #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ - #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ - #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= SPCKD ========================================================= */ - #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ - #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SSLND ========================================================= */ - #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ - #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPND ========================================================== */ - #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ - #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR2 ========================================================= */ - #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ - #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ - #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ - #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ - #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ - #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ - #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCMD ========================================================= */ - #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ - #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ - #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ - #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ - #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ - #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ - #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ - #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ - #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ - #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ - #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ - #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ -/* ======================================================== SPDCR2 ========================================================= */ - #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ - #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ - #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSSR ========================================================= */ - #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ - #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ - #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR3 ========================================================= */ - #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ - #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ - #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ - #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPR ========================================================== */ - #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ - #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ - #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ - #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PARIOAD ======================================================== */ - #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR ======================================================== */ - #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMWTSC ======================================================== */ -/* ======================================================== ECCMODE ======================================================== */ - #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ - #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== ECC2STS ======================================================== */ - #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ - #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECC1STSEN ======================================================= */ - #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ - #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ECC1STS ======================================================== */ - #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ - #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCPRCR ======================================================== */ - #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECCPRCR2 ======================================================== */ - #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ - #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCETST ======================================================== */ - #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ - #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCOAD ========================================================= */ - #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR2 ======================================================= */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ - #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SSICR ========================================================= */ - #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ - #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ - #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ - #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ - #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ - #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ - #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ - #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ - #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ - #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ - #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ - #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ - #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ - #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ - #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ - #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ - #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ - #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ - #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ - #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ - #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ - #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ -/* ========================================================= SSISR ========================================================= */ - #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ - #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ - #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ - #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ - #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ - #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ - #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ - #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ - #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ - #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ - #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFCR ========================================================= */ - #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ - #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ - #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ - #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ - #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ - #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ - #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ - #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ - #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ - #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFSR ========================================================= */ - #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ - #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ - #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ - #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ - #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFTDR ======================================================== */ - #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ - #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFTDR16 ======================================================= */ -/* ======================================================= SSIFTDR8 ======================================================== */ -/* ======================================================== SSIFRDR ======================================================== */ - #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ - #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFRDR16 ======================================================= */ -/* ======================================================= SSIFRDR8 ======================================================== */ -/* ======================================================== SSIOFR ========================================================= */ - #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ - #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ - #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ - #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== SSISCR ========================================================= */ - #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ - #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ - #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ - #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ -/* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ -/* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ -/* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ -/* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ -/* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ -/* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR2 ======================================================== */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ -/* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ -/* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ -/* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ -/* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ -/* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ -/* ========================================================= LPOPT ========================================================= */ - #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ - #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ - #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ -/* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ -/* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ -/* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ -/* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ -/* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ -/* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ -/* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ -/* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ -/* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ -/* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ -/* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ -/* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ -/* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ -/* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LDOSCR ========================================================= */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ -/* ======================================================= PL2LDOSCR ======================================================= */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ -/* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ -/* ========================================================= SOMRG ========================================================= */ - #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ - #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ -/* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ -/* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ -/* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ -/* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ -/* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== SCISPICKDIVCR ===================================================== */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== CANFDCKDIVCR ====================================================== */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== GPTCKDIVCR ======================================================= */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== USB60CKDIVCR ====================================================== */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== CECCKDIVCR ======================================================= */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== I3CCKDIVCR ======================================================= */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== IICCKDIVCR ======================================================= */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ -/* ====================================================== SCISPICKCR ======================================================= */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= CANFDCKCR ======================================================= */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== GPTCKCR ======================================================== */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= USB60CKCR ======================================================= */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCKCR ======================================================== */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== IICCKCR ======================================================== */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== I3CCKCR ======================================================== */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ - #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ -/* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ -/* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ -/* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCDR ========================================================= */ - #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ - #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCR ========================================================== */ - #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ - #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ - #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ - #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ - #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ - #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ========================================================= CFIFO ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DVCHGR ========================================================= */ - #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ - #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ - #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ - #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ====================================================== USBBCCTRL0 ======================================================= */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ -/* ======================================================== UCKSEL ========================================================= */ - #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ - #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ -/* ========================================================= USBMC ========================================================= */ - #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ - #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ - #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSLEW ======================================================== */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR0R_FS ======================================================= */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR1R_FS ======================================================= */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= WDTRR ========================================================= */ - #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ - #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ -/* ========================================================= WDTCR ========================================================= */ - #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ========================================================= WDTSR ========================================================= */ - #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== WDTRCR ========================================================= */ - #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= WDTCSTPR ======================================================== */ - #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFOAD ========================================================= */ - #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ========================================================= TZFPT ========================================================= */ - #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CCACTL ========================================================= */ - #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ - #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCAFCT ========================================================= */ - #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ - #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCALCF ========================================================= */ - #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ - #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ -/* ======================================================== SCACTL ========================================================= */ - #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ - #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCAFCT ========================================================= */ - #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCALCF ========================================================= */ - #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ -/* ======================================================== CAPOAD ========================================================= */ - #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================== CAPRCR ========================================================= */ - #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ - #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ - #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CSAR ========================================================== */ - #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ - #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ - #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ - #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ -/* ======================================================== SRAMSAR ======================================================== */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ -/* ======================================================= STBRAMSAR ======================================================= */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DTCSAR ========================================================= */ - #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ - #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACSAR ======================================================== */ - #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ - #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARA ======================================================== */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ -/* ======================================================== ICUSARB ======================================================== */ - #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ - #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARC ======================================================== */ - #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ - #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ -/* ======================================================== ICUSARD ======================================================== */ - #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ - #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARE ======================================================== */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARF ======================================================== */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARG ======================================================== */ - #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARH ======================================================== */ - #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARI ======================================================== */ - #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARM ======================================================== */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARA ======================================================== */ - #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ - #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARB ======================================================== */ - #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ - #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARC ======================================================== */ - #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ - #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSPARC ======================================================== */ - #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ - #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MMPUSARA ======================================================== */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ -/* ======================================================= MMPUSARB ======================================================== */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGSAR ======================================================== */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DMACCHSAR ======================================================= */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ -/* ======================================================== CPUDSAR ======================================================== */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SRAMSABAR0 ======================================================= */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ====================================================== SRAMSABAR1 ======================================================= */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ======================================================== TEVTRCR ======================================================== */ - #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ - #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CADR ========================================================== */ - #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ - #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ - #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ - #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ - #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ - #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ - #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ - #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ - #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ - #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ - #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ - #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ - #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ - #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ - #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ - #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL1 ======================================================== */ - #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ - #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ - #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ - #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ - #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ - #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ - #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= STATB ========================================================= */ - #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ - #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= STATL ========================================================= */ - #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ - #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC0L ========================================================= */ - #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ - #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC1L ========================================================= */ - #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ - #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATB ========================================================== */ - #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ - #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMT ========================================================== */ - #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ - #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLL ========================================================= */ - #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ - #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLH ========================================================= */ - #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ - #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBL ========================================================= */ - #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ - #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBH ========================================================= */ - #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ - #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LL ========================================================= */ - #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ - #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LH ========================================================= */ - #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ - #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LL ========================================================= */ - #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ - #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LH ========================================================= */ - #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ - #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBL ========================================================= */ - #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ - #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBH ========================================================= */ - #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ - #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMP ========================================================== */ - #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ - #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CECEXMD ======================================================== */ - #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ - #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ - #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= CECEXMON ======================================================== */ - #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ - #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ - #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ -/* ========================================================= CTXD ========================================================== */ -/* ========================================================= CRXD ========================================================== */ -/* ========================================================= CECES ========================================================= */ - #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ - #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ - #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ - #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ - #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ - #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ - #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ - #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ -/* ========================================================= CECS ========================================================== */ - #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ - #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ - #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ - #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ - #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ - #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ - #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ -/* ========================================================= CECFC ========================================================= */ - #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ - #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ - #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ - #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ - #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ - #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ - #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ - #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL0 ======================================================== */ - #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ - #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ - #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ - #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ - #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ - #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ - #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ - #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DCR ========================================================== */ - #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ - #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ - #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ -/* ========================================================== DAR ========================================================== */ - #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ - #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ - #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ - #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ - #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= DCSR ========================================================== */ - #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ - #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ - #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ - #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ - #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ - #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ - #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ - #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ - #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ - #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ -/* ========================================================== DSR ========================================================== */ - #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ - #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ - #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ - #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ -/* ========================================================= MDTR ========================================================== */ - #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ - #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ - #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ - #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ - #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ - #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ -/* ========================================================= ACTR ========================================================== */ - #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ - #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ACAR ========================================================== */ - #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ - #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DRCSTR ========================================================= */ - #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ - #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ - #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ - #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ - #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ - #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ - #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ - #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ - #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ -/* ======================================================== DWCSTR ========================================================= */ - #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ - #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ - #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ - #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ - #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ - #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ - #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ - #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ - #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ - #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ - #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ -/* ========================================================= DCSTR ========================================================= */ - #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ - #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ - #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ - #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ -/* ========================================================= CDSR ========================================================== */ - #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ - #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ - #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ - #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ - #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ - #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ - #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ - #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ - #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ -/* ========================================================= MDLR ========================================================== */ - #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ - #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ - #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ - #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ - #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ -/* ========================================================= MRWCR ========================================================= */ - #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ - #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ - #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ - #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ - #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ -/* ======================================================== MRWCSR ========================================================= */ - #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ - #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ - #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ - #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ - #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ - #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ - #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ - #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ - #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ - #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ - #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ - #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ - #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ - #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ - #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ -/* ========================================================== ESR ========================================================== */ - #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ - #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ - #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ - #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ -/* ========================================================= CWNDR ========================================================= */ - #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ - #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CWDR ========================================================== */ - #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ - #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ - #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ - #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ - #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ -/* ========================================================== CRR ========================================================== */ - #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ - #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ - #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ - #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ - #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= ACSR ========================================================== */ - #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ - #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ - #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ -/* ======================================================== DCSMXR ========================================================= */ - #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ - #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ - #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ - #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== DWSCTSR ======================================================== */ - #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ - #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ - #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ - #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ - #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CFIFO ========================================================= */ - #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ - #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ - #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPEBUF ======================================================== */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================= PHYTRIM1 ======================================================== */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ -/* ======================================================= PHYTRIM2 ======================================================== */ - #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ - #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ - #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ - #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= EC710CTL ======================================================== */ - #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ - #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ - #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ - #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ - #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ - #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ - #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ - #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ -/* ======================================================= EC710TMC ======================================================== */ - #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ - #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ - #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ -/* ======================================================= EC710TED ======================================================== */ - #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ - #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= EC710EAD0 ======================================================= */ - #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ - #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCKMHZ ========================================================= */ - #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ - #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ - -/** @} */ /* End of group PosMask_peripherals */ - - #ifdef __cplusplus -} - #endif - -#endif /* R7FA6M5BH_H */ - -/** @} */ /* End of group R7FA6M5BH */ - -/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_cfg.h deleted file mode 100644 index 825f8cd32..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BOARD_CFG_H_ -#define BOARD_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - void bsp_init(void * p_args); - - #ifdef __cplusplus - } - #endif -#endif /* BOARD_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_sdram.h deleted file mode 100644 index 2d5eb7405..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/board_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BOARD_SDRAM_H -#define BOARD_SDRAM_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. - * It is only present if the new support has not been enabled. */ -#if 1 != BSP_CFG_SDRAM_ENABLED - #define bsp_sdram_init() R_BSP_SdramInit(true) -#endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_api.h deleted file mode 100644 index d912bc0ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_api.h +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_API_H -#define BSP_API_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* FSP Common Includes. */ -#include "fsp_common_api.h" - -/* Gets MCU configuration information. */ -#include "bsp_cfg.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic push - -/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. - * We are not modifying these files so we will ignore these warnings temporarily. */ - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" -#endif - -/* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_exceptions.h" -#include "vector_data.h" - -/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ -#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" -#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic pop -#endif - -#if defined(BSP_API_OVERRIDE) - #include BSP_API_OVERRIDE -#else - -/* BSP Common Includes. */ - #include "../../src/bsp/mcu/all/bsp_common.h" - -/* BSP MCU Specific Includes. */ - #include "../../src/bsp/mcu/all/bsp_register_protection.h" - #include "../../src/bsp/mcu/all/bsp_irq.h" - #include "../../src/bsp/mcu/all/bsp_io.h" - #include "../../src/bsp/mcu/all/bsp_group_irq.h" - #include "../../src/bsp/mcu/all/bsp_clocks.h" - #include "../../src/bsp/mcu/all/bsp_module_stop.h" - #include "../../src/bsp/mcu/all/bsp_security.h" - -/* Factory MCU information. */ - #include "../../inc/fsp_features.h" - -/* BSP Common Includes (Other than bsp_common.h) */ - #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" - - #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") - #include "../../src/bsp/mcu/all/internal/bsp_internal.h" - #endif - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_cfg.h deleted file mode 100644 index 8074418ad..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_cfg.h +++ /dev/null @@ -1,61 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - #include "bsp_clock_cfg.h" - #include "bsp_mcu_family_cfg.h" - #include "board_cfg.h" - #define RA_NOT_DEFINED 0 - #ifndef BSP_CFG_RTOS - #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else - #define BSP_CFG_RTOS (0) - #endif - #endif - #ifndef BSP_CFG_RTC_USED - #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) - #endif - #undef RA_NOT_DEFINED - #if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif - #define BSP_CFG_MCU_VCC_MV (3300) - #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0) - #define BSP_CFG_PARAM_CHECKING_ENABLE (0) - #define BSP_CFG_ASSERT (0) - - #define BSP_CFG_PFS_PROTECT ((1)) - - #define BSP_CFG_C_RUNTIME_INIT ((1)) - #define BSP_CFG_EARLY_INIT ((0)) - - #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED - #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - #endif - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE - #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE - #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS - #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - #endif - - #ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_clocks.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_clocks.h deleted file mode 100644 index 7ef416625..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_clocks.h +++ /dev/null @@ -1,1727 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_CLOCKS_H -#define BSP_CLOCKS_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_clock_cfg.h" -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match SCKCR.CKSEL values. */ -#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. - #endif - #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. - #endif - #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. - #endif -#else - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ - #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. - #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. - -/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ - #define BSP_PRV_OSTC_OFFSET (0x7FU) - -#endif - -/* PLLs are not supported in the following scenarios: - * - When using low voltage mode - * - When using an MCU that does not have a PLL - * - When the PLL only accepts the main oscillator as a source and XTAL is not used - */ -#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) - #define BSP_PRV_PLL_SUPPORTED (1) - #if BSP_FEATURE_CGC_HAS_PLL2 - #define BSP_PRV_PLL2_SUPPORTED (1) - #else - #define BSP_PRV_PLL2_SUPPORTED (0) - #endif -#else - #define BSP_PRV_PLL_SUPPORTED (0) - #define BSP_PRV_PLL2_SUPPORTED (0) -#endif - -/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency - * calculated here is also used to initialize the g_clock_freq array. */ -#if BSP_PRV_PLL_SUPPORTED - #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ - (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif -#if BSP_PRV_PLL2_SUPPORTED - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif - -#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) - -/* Frequencies of clocks with fixed freqencies. */ -#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz -#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz - -#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #endif - #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ - (BSP_CFG_PLL_DIV + 1U)) - #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ - (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) - #endif -#endif - -/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ -#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) -#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) -#else - #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) -#endif - -#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) -#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) -#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) -#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) -#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) -#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) -#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) -#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) - -/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have - * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ -#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) -#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) -#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) -#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) -#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) -#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) -#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) -#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) -#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) -#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) - -/* System clock divider options. */ -#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. -#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. -#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. -#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. -#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. -#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. -#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. -#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). -#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. -#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. -#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. -#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. - -/* USB clock divider options. */ -#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 -#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 -#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 -#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 -#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 -#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 -#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 -#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 -#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 -#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 - -/* USB60 clock divider options. */ -#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 -#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 -#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 -#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 -#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 -#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 -#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 -#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 -#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 -#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 - -/* GLCD clock divider options. */ -#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 -#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 -#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 -#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 -#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 -#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 -#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 -#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 -#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 -#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 - -/* OCTA clock divider options. */ -#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 - -/* CANFD clock divider options. */ -#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 - -/* SCI clock divider options. */ -#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 -#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 -#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 -#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 -#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 -#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 -#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 -#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 -#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 -#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 - -/* SPI clock divider options. */ -#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 -#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 -#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 -#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 -#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 -#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 -#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 -#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 -#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 -#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 - -/* SCISPI clock divider options. */ -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 - -/* GPT clock divider options. */ -#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 -#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 -#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 -#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 -#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 -#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 -#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 -#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 -#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 -#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 - -/* IIC clock divider options. */ -#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 -#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 -#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 -#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 -#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 - -/* CEC clock divider options. */ -#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 -#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 - -/* I3C clock divider options. */ -#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 -#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 -#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 -#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 -#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 -#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 -#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 -#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 -#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 -#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 - -/* ADC clock divider options. */ -#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 -#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 -#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 -#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 -#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 -#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 -#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 -#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 -#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 -#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 - -/* SAU clock divider options. */ -#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 -#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 -#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 -#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 -#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 -#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 - -/* Extra peripheral 0 clock divider options. */ -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 - -/* PLL divider options. */ -#define BSP_CLOCKS_PLL_DIV_1 (0) -#define BSP_CLOCKS_PLL_DIV_2 (1) -#define BSP_CLOCKS_PLL_DIV_3 (2) -#define BSP_CLOCKS_PLL_DIV_4 (3) -#define BSP_CLOCKS_PLL_DIV_5 (4) -#define BSP_CLOCKS_PLL_DIV_6 (5) -#define BSP_CLOCKS_PLL_DIV_8 (7) -#define BSP_CLOCKS_PLL_DIV_9 (8) -#define BSP_CLOCKS_PLL_DIV_1_5 (9) -#define BSP_CLOCKS_PLL_DIV_16 (15) - -/* PLL multiplier options. */ -#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - -/* Offset from decimal multiplier to register value for PLLCCR type 4. */ - #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) - -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) - -#else - - #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U))) - -#endif - -/* Configuration option used to disable clock output. */ -#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) - -/* HOCO cycles per microsecond. */ -#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) - -/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ -#if BSP_HOCO_HZ < 48000000U - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) -#else - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) -#endif - -/* Create a mask of valid bits in SCKDIVCR. */ -#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) -#else - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) -#else - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) -#else - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) -#else - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB - #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) -#else - #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#else - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) -#else - #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) -#endif -#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ - BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ - BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ - BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) - -/* FLL is only used when enabled, present and the subclock is populated. */ -#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_PRV_HOCO_USE_FLL (1) - #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US - #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) - #endif -#else - #define BSP_PRV_HOCO_USE_FLL (0) - #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) -#endif - -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR - #define BSP_PRV_RTC_RESET_DELAY_US (200) -#endif - -/* Operating power control modes. */ -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed -#else - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed - #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed -#endif -#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -typedef struct -{ - uint32_t pll_freq; -} bsp_clock_up2025-07-24_callback_args_t; - - #if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_up2025-07-24_callback_t)(bsp_clock_up2025-07-24_callback_args_t * - p_callback_args); - #elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_up2025-07-24_callback_t)(bsp_clock_up2025-07-24_callback_args_t * - p_callback_args); - #endif - -#endif - -/** PLL multiplier values */ -typedef enum e_cgc_pll_mul -{ - CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 - CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 - CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 - CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 - CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 - CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 - CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 - CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 - CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 - CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 - CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 - CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 - CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 - CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 - CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 - CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 - CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 - CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 - CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 - CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 - CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 - CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 - CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 - CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 - CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 - CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 - CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 - CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 - CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 - CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 - CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 - CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 - CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 - CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 - CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 - CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 - CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 - CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 - CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 - CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 - CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 - CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 - CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 - CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 - CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 - CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 - CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 - CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 - CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 - CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 - CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 - CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 - CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 - CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 - CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 - CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 - CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 - CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 - CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 - CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 - CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 - CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 - CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 - CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 - CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 - CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 - CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 - CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 - CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 - CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 - CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 - CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 - CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 - CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 - CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 - CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 - CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 - CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 - CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 - CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 - CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 - CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 - CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 - CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 - CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 - CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 - CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 - CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 - CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 - CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 - CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 - CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 - CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 - CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 - CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 - CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 - CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 - CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 - CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 - CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 - CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 - CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 - CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 - CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 - CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 - CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 - CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 - CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 - CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 - CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 - CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 - CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 - CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 - CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 - CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 - CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 - CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 - CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 - CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 - CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 - CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 - CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 - CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 - CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 - CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 - CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 - CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 - CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 - CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 - CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 - CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 - CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 - CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 - CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 - CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 - CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 - CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 - CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 - CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 - CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 - CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 - CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 - CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 - CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 - CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 - CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 - CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 - CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 - CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 - CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 - CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 - CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 - CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 - CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 - CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 - CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 - CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 - CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 - CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 - CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 - CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 - CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 - CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 - CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 - CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 - CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 - CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 - CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 - CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 - CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 - CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 - CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 - CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 - CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 - CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 - CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 - CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 - CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 - CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 - CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 - CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 - CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 - CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 - CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 - CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 - CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 - CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 - CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 - CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 - CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 - CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 - CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 - CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 - CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 - CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 - CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 - CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 - CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 - CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 - CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 - CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 - CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 - CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 - CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 - CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 - CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 - CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 - CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 - CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 - CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 - CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 - CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 - CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 - CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 - CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 - CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 - CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 - CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 - CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 - CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 - CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 - CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 - CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 - CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 - CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 - CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 - CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 - CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 - CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 - CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 - CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 - CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 - CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 - CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 - CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 - CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 - CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 - CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 - CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 - CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 - CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 - CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 - CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 - CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 - CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 - CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 - CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 - CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 - CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 - CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 - CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 - CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 - CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 - CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 - CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 - CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 - CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 - CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 - CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 - CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 - CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 - CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 - CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 - CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 - CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 - CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 - CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 - CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 - CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 - CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 - CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 - CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 - CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 - CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 - CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 - CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 - CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 - CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 - CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 - CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 - CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 - CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 - CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 - CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 - CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 - CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 - CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 - CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 - CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 - CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 - CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 - CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 - CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 - CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 - CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 - CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 - CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 - CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 - CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 - CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 - CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 - CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 - CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 - CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 - CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 - CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 - CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 - CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 - CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 - CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 - CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 - CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 - CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 - CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 - CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 - CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 - CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 - CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 - CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 - CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 - CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 - CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 - CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 - CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 - CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 - CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 - CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 - CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 - CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 - CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 - CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 - CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 - CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 - CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 - CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 - CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 - CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 - CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 - CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 - CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 - CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 - CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 - CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 - CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 - CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 - CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 - CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 - CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 - CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 - CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 - CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 - CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 - CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 - CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 - CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 - CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 - CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 - CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 - CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 - CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 - CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 - CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 - CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 - CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 - CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 - CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 - CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 - CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 - CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 - CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 - CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 - CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 - CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 - CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 - CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 - CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 - CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 - CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 - CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 - CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 - CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 - CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 - CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 - CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 - CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 - CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 - CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 - CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 - CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 - CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 - CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 - CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 - CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 - CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 - CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 - CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 - CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 - CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 - CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 - CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 - CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 - CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 - CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 - CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 - CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 - CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 - CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 - CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 - CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 - CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 - CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 - CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 - CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 - CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 - CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 - CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 - CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 - CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 - CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 - CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 - CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 - CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 - CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 - CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 - CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 - CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 - CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 - CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 - CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 - CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 - CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 - CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 - CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 - CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 - CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 - CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 - CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 - CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 - CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 - CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 - CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 - CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 - CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 - CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 - CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 - CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 - CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 - CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 - CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 - CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 - CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 - CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 - CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 - CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 - CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 - CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 - CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 - CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 - CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 - CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 - CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 - CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 - CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 - CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 - CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 - CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 - CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 - CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 - CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 - CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 - CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 - CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 - CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 - CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 - CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 - CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 - CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 - CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 - CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 - CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 - CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 - CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 - CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 - CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 - CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 - CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 - CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 - CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 - CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 - CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 - CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 - CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 - CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 - CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 - CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 - CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 - CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 - CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 - CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 - CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 - CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 - CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 - CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 - CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 - CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 - CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 - CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 - CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 - CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 - CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 - CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 - CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 - CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 - CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 - CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 - CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 - CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 - CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 - CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 - CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 - CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 - CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 - CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 - CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 - CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 - CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 - CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 - CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 - CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 - CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 - CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 - CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 - CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 - CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 - CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 - CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 - CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 - CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 - CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 - CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 - CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 - CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 - CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 - CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 - CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 - CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 - CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 - CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 - CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 - CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 - CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 - CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 - CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 - CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 - CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 - CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 - CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 - CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 - CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 - CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 - CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 - CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 - CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 - CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 - CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 - CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 - CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 - CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 - CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 - CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 - CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 - CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 - CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 - CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 - CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 - CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 - CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 - CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 - CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 - CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 - CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 - CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 - CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 - CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 - CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 - CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 - CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 - CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 - CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 - CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 - CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 - CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 - CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 - CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 - CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 - CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 - CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 - CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 - CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 - CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 - CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 - CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 - CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 - CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 - CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 - CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 - CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 - CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 - CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 - CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 - CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 - CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 - CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 - CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 - CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 - CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 - CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 - CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 - CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 - CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 - CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 - CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 - CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 - CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 - CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 - CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 - CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 - CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 - CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 - CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 - CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 - CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 - CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 - CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 - CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 - CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 - CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 - CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 - CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 - CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 - CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 - CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 - CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 - CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 - CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 - CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 - CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 - CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 - CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 - CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 - CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 - CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 - CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 - CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 - CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 - CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 - CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 - CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 - CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 - CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 - CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 - CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 - CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 - CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 - CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 - CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 - CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 - CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 - CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 - CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 - CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 - CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 - CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 - CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 - CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 - CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 - CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 - CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 - CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 - CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 - CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 - CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 - CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 - CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 - CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 - CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 - CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 - CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 - CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 - CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 - CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 - CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 - CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 - CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 - CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 - CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 - CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 - CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 - CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 - CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 - CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 - CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 - CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 - CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 - CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 - CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 - CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 - CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 - CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 - CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 - CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 - CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 - CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 - CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 - CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 - CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 - CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 - CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 - CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 - CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 - CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 - CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 - CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 - CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 - CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 - CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 - CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 - CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 - CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 - CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 - CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 - CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 - CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 - CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 - CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 - CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 - CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 - CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 - CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 - CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 - CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 - CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 - CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 - CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 - CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 - CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 - CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 - CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 - CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 - CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 - CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 - CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 - CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 - CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 - CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 - CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 - CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 - CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 - CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 - CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 - CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 - CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 - CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 - CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 - CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 - CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 - CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 - CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 - CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 - CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 - CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 - CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 - CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 - CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 - CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 - CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 - CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 - CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 - CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 - CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 - CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 - CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 - CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 - CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 - CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 - CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 - CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 - CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 - CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 - CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 - CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 - CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 - CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 - CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 - CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 - CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 - CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 - CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 - CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 - CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 - CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 - CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 - CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 - CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 - CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 - CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 - CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 - CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 - CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 - CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 - CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 - CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 - CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 - CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 - CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 - CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 - CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 - CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 - CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 - CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 - CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 - CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 - CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 - CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 - CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 - CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 - CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 - CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 - CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 - CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 - CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 - CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 - CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 - CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 - CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 - CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 - CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 - CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 - CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 - CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 - CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 - CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 - CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 - CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 - CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 - CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 - CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 - CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 - CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 - CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 - CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 - CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 - CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 - CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 - CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 - CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 - CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 - CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 - CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 - CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 - CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 - CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 - CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 - CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 - CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 - CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 - CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 - CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 - CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 - CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 - CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 - CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 - CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 - CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 - CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 - CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 - CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 - CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 - CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 - CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 - CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 - CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 - CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 - CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 - CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 - CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 - CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 - CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 - CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 - CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 - CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 - CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 - CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 - CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 - CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 - CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 - CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 - CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 - CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 - CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 - CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 - CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 - CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 - CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 - CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 - CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 - CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 - CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 - CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 - CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 - CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 - CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 - CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 - CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 - CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 - CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 - CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 - CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 - CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 - CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 - CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 - CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 - CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 - CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 - CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 - CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 - CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 - CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 - CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 - CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 - CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 - CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 - CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 - CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 - CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 - CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 - CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 - CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 - CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 - CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 - CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 - CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 - CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 - CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 - CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 - CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 - CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 - CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 - CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 - CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 - CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 - CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 - CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 - CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 - CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 - CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 - CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 - CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 - CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 - CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 - CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 - CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 - CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 - CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 - CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 - CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 - CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 - CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 - CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 - CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 - CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 - CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 - CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 - CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 - CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 - CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 - CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 - CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 - CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 - CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 - CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 - CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 - CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 - CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 - CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 - CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 - CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 - CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 - CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 - CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 - CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 - CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 - CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 - CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 - CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 - CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 - CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 - CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 - CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 - CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 - CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 - CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 - CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 - CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 - CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 - CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 - CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 - CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 - CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 - CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 - CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 - CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 - CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 - CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 - CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 - CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 - CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 - CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 - CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 - CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 - CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 - CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 - CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 - CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 - CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 - CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 - CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 - CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 - CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 - CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 - CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 - CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 - CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 - CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 - CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 - CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 - CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 - CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 - CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 - CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 - CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 - CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 - CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 - CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 - CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 - CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 - CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 - CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 - CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 - CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 - CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 - CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 - CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 - CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 - CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 - CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 - CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 - CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 - CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 - CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 - CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 - CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 - CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 - CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 - CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 - CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 - CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 - CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 - CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 - CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 - CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 - CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 - CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 - CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 - CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 - CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 - CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 - CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 - CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 - CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 - CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 - CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 - CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 - CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 - CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 - CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 - CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 - CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 - CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 - CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 - CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 - CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 - CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 - CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 - CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 - CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 - CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 - CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 - CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 - CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 - CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 - CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 - CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 - CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 - CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 - CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 - CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 - CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 - CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 - CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 - CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 - CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 - CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 - CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 - CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 - CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 - CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 - CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 - CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 - CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 - CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 - CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 - CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 - CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 - CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 - CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 - CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 - CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 - CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 - CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 - CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 - CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 - CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 - CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 - CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 - CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 - CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 - CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 - CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 - CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 - CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 - CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 - CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 - CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 - CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 - CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 -} cgc_pll_mul_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_clock_init(void); // Used internally by BSP - -#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD -void bsp_clock_freq_var_init(void); // Used internally by BSP - -#endif - -#if BSP_TZ_SECURE_BUILD -void r_bsp_clock_up2025-07-24_callback_set(bsp_clock_up2025-07-24_callback_t p_callback, - bsp_clock_up2025-07-24_callback_args_t * p_callback_memory); - -#endif - -/* Used internally by CGC */ - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE -void bsp_prv_operating_mode_set(uint8_t operating_mode); - -#endif - -#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED -uint32_t bsp_prv_power_change_mstp_set(void); -void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); - -#endif - -void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); - -#if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); - -#else -void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); -uint32_t bsp_prv_clock_source_get(void); - -#endif - -/* RTC Initialization */ -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR -void R_BSP_Init_RTC(void); - -#endif - -#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE -bool bsp_prv_rtc_register_clock_set(bool enable); - -#endif - -#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE -bool bsp_prv_clock_prepare_pre_sleep(void); -void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); - -#endif - -/* The public function is used to get state or initialize the sub-clock. */ -#if BSP_FEATURE_RTC_IS_IRTC -fsp_err_t R_BSP_SubclockStatusGet(); -fsp_err_t R_BSP_SubclockInitialize(); - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_common.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_common.h deleted file mode 100644 index 2009b34e6..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_common.h +++ /dev/null @@ -1,623 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_COMMON_H -#define BSP_COMMON_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include -#include - -/* Different compiler support. */ -#include "../../inc/api/fsp_common_api.h" -#include "bsp_compiler_support.h" - -/* BSP TFU Includes. */ -#include "../../src/bsp/mcu/all/bsp_tfu.h" - -#include "../../src/bsp/mcu/all/bsp_sdram.h" - -/* BSP MMF Includes. */ -#include "../../src/bsp/mcu/all/bsp_mmf.h" - -#include "bsp_cfg.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** Used to signify that an ELC event is not able to be used as an interrupt. */ -#define BSP_IRQ_DISABLED (0xFFU) - -/* Version of this module's code and API. */ - -#if 1 == BSP_CFG_RTOS /* ThreadX */ - #include "tx_user.h" - #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) - #include "tx_port.h" - #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); - #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); - #else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE - #endif -#else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE -#endif - -/** Macro that can be defined in order to enable logging in FSP modules. */ -#ifndef FSP_LOG_PRINT - #define FSP_LOG_PRINT(X) -#endif - -/** Macro to log and return error without an assertion. */ -#ifndef FSP_RETURN - - #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ - return err; -#endif - -/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in - * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ -#if (1 == BSP_CFG_ASSERT) - - #ifndef FSP_ERROR_LOG - #define FSP_ERROR_LOG(err) \ - fsp_error_log((err), __FILE__, __LINE__); - #endif -#else - - #define FSP_ERROR_LOG(err) -#endif - -/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP - * functions. */ -#if (3 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) -#elif (2 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) {assert(a);} -#else - #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) -#endif // ifndef FSP_ASSERT - -/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used - * to identify runtime errors in FSP functions. */ - -#define FSP_ERROR_RETURN(a, err) \ - { \ - if ((a)) \ - { \ - (void) 0; /* Do nothing */ \ - } \ - else \ - { \ - FSP_ERROR_LOG(err); \ - return err; \ - } \ - } - -/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register up2025-07-24s. - * This macro can be redefined to add a timeout if necessary. */ -#ifndef FSP_HARDWARE_REGISTER_WAIT - #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} -#endif - -#ifndef FSP_REGISTER_READ - -/* Read a register and discard the result. */ - #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); -#endif - -/**************************************************************** - * - * This check is performed to select suitable ASM API with respect to core - * - * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so - * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ - -#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) - #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) - #endif -#else - #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #endif - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) -#endif - -/* This macro defines a variable for saving previous mask value */ -#ifndef FSP_CRITICAL_SECTION_DEFINE - - #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U -#endif - -/* These macros abstract methods to save and restore the interrupt state for different architectures. */ -#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK - #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) -#else - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI - #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ - (8U - __NVIC_PRIO_BITS))) -#endif - -/** This macro temporarily saves the current interrupt state and disables interrupts. */ -#ifndef FSP_CRITICAL_SECTION_ENTER - #define FSP_CRITICAL_SECTION_ENTER \ - old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ - FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) -#endif - -/** This macro restores the previously saved interrupt state, reenabling interrupts. */ -#ifndef FSP_CRITICAL_SECTION_EXIT - #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) -#endif - -/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ -#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) - -/** Used to signify that the requested IRQ vector is not defined in this system. */ -#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) - -/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ -#if (BSP_CFG_MCU_PART_SERIES == 8) - #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) -#else - #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) -#endif - -/* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE - #define FSP_PRIV_TZ_USE_SECURE_REGS (1) -#else - #define FSP_PRIV_TZ_USE_SECURE_REGS (0) -#endif - -/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ -#if BSP_CFG_EARLY_INIT - #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) -#else - #define BSP_SECTION_EARLY_INIT -#endif - -#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 -BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); - -#endif - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/* - * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register - * from the secure application using the provided non-secure callable functions. - */ - #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) - #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) - #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) -#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/*******************************************************************************************************************//** - * Read a non-secure 8-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) -{ - p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 16-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) -{ - p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 32-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) -{ - p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/* - * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register - * using the non-secure aliased address. - */ - #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) - #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) - #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) -#else - #define FSP_STYPE3_REG8_READ(X, S) (X) - #define FSP_STYPE3_REG16_READ(X, S) (X) - #define FSP_STYPE3_REG32_READ(X, S) (X) -#endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Different warm start entry locations in the BSP. */ -typedef enum e_bsp_warm_start_event -{ - BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. - BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. - BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up -} bsp_warm_start_event_t; - -/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ -typedef enum e_fsp_priv_clock -{ - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_PCLKE = 20, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, - FSP_PRIV_CLOCK_CPUCLK = 32, -} fsp_priv_clock_t; - -/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ -typedef enum e_fsp_priv_source_clock -{ - FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator - FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator - FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator - FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator - FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator - FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output - FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output - FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output - FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output - FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output - FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output - FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output - FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output -} fsp_priv_source_clock_t; - -typedef struct st_bsp_unique_id -{ - union - { - uint32_t unique_id_words[4]; - uint8_t unique_id_bytes[16]; - }; -} bsp_unique_id_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); - -/*********************************************************************************************************************** - * Global variables (defined in other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Return active interrupt vector number value - * - * @return Active interrupt vector number value - **********************************************************************************************************************/ -__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) -{ - xPSR_Type xpsr_value; - xpsr_value.w = __get_xPSR(); - - return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); -} - -/*******************************************************************************************************************//** - * Gets the frequency of a system clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) -{ -#if !BSP_FEATURE_CGC_REGISTER_SET_B - uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; - - #if BSP_FEATURE_CGC_HAS_CPUCLK - if (FSP_PRIV_CLOCK_CPUCLK == clock) - { - return SystemCoreClock; - } - - /* Get CPUCLK divisor */ - uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; - - /* Determine if either divisor is a multiple of 3 */ - if ((cpuclk_div | clock_div) & 8U) - { - /* Convert divisor settings to their actual values */ - cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); - clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); - - /* Calculate clock with multiplication and division instead of shifting */ - return (SystemCoreClock * cpuclk_div) / clock_div; - } - else - { - return (SystemCoreClock << cpuclk_div) >> clock_div; - } - - #else - uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; - - return (SystemCoreClock << iclk_div) >> clock_div; - #endif -#else - FSP_PARAMETER_NOT_USED(clock); - - return SystemCoreClock; -#endif -} - -/*******************************************************************************************************************//** - * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). - * - * @return Clock Divider - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) -{ - if (2U >= ckdivcr) - { - - /* clock_div: - * - Clock Divided by 1: 0 - * - Clock Divided by 2: 1 - * - Clock Divided by 4: 2 - */ - return 1U << ckdivcr; - } - else if (3U == ckdivcr) - { - - /* Clock Divided by 6 */ - return 6U; - } - else if (4U == ckdivcr) - { - - /* Clock Divided by 8 */ - return 8U; - } - else if (5U == ckdivcr) - { - - /* Clock Divided by 3 */ - return 3U; - } - else if (6U == ckdivcr) - { - - /* Clock Divided by 5 */ - return 5; - } - else if (7U == ckdivcr) - { - - /* Clock Divided by 10 */ - return 10; - } - else - { - /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ - } - - /* Clock Divided by 16 */ - return 16U; -} - -#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI/SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) -{ - uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; - uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; - - return R_BSP_SourceClockHzGet(scispicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) -{ - uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = - (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> - R_SYSTEM_SPICKCR_CKSEL_Pos); - - return R_BSP_SourceClockHzGet(spicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SCI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) -{ - uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = - (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> - R_SYSTEM_SCICKCR_SCICKSEL_Pos); - - return R_BSP_SourceClockHzGet(scicksel) / clock_div; -} - -#endif - -/*******************************************************************************************************************//** - * Get unique ID for this device. - * - * @return A pointer to the unique identifier structure - **********************************************************************************************************************/ -__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) -{ -#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 - - return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); -#else - - return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; -#endif -} - -/*******************************************************************************************************************//** - * Disables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheDisable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 - - /* Writeback and flush cache when disabling - * MREF_INTERNAL_12 */ - if (R_CACHE->CCAWTA_b.WT) - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; - } - else - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; - } - - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #else - - /* Disable the C-Cache. */ - R_CACHE->CCACTL = 0U; - #endif -#endif -} - -/*******************************************************************************************************************//** - * Enables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheEnable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invali2025-07-24 the flash cache and wait until it is invali2025-07-24d. (See section 55.3.2.2 "Operation" of the Flash Cache - * in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 - - /* Configure the C-Cache line size. */ - R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; - #else - - /* Check that no flush or writeback are ongoing before enabling - * MREF_INTERNAL_13 */ - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #endif - - /* Enable the C-Cache. */ - R_CACHE->CCACTL = 1U; -#endif -} - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -#if (1 == BSP_CFG_ASSERT) - -/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ -void fsp_error_log(fsp_err_t err, const char * file, int32_t line); - -#endif - -/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will - * alert the user of the error. The user can override this default behavior by defining their own - * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. - */ -#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) - - #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_compiler_support.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_compiler_support.h deleted file mode 100644 index 39f752c3c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_compiler_support.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_COMPILER_SUPPORT_H - #define BSP_COMPILER_SUPPORT_H - - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - #include "arm_cmse.h" - #endif - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - #if defined(__ARMCC_VERSION) /* AC6 compiler */ - -/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load - * memory (ROM) is reserved unnecessarily. */ - #define BSP_UNINIT_SECTION_PREFIX ".bss" - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__GNUC__) /* GCC compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__ICCARM__) /* IAR compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP "HEAP" - #endif - #define BSP_DONT_REMOVE __root - #define BSP_ATTRIBUTE_STACKLESS __stackless - #define BSP_FORCE_INLINE _Pragma("inline=forced") - #endif - - #ifndef BSP_SECTION_STACK - #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" - #endif - #ifndef BSP_SECTION_FLASH_GAP - #define BSP_SECTION_FLASH_GAP - #endif - #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" - #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - #define BSP_SECTION_ROM_REGISTERS ".rom_registers" - #define BSP_SECTION_ID_CODE ".id_code" - -/* Compiler neutral macros. */ - #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - - #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) - - #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED - - #define BSP_WEAK_REFERENCE __attribute__((weak)) - -/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ - #define BSP_STACK_ALIGNMENT (8) - -/*********************************************************************************************************************** - * TrustZone definitions - **********************************************************************************************************************/ - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) - #if defined(__ICCARM__) /* IAR compiler */ - #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call - #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry - #else - #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) - #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) - #endif - #else - #define BSP_CMSE_NONSECURE_CALL - #define BSP_CMSE_NONSECURE_ENTRY - #endif - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/** @} (end of addtogroup BSP_MCU) */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_delay.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_delay.h deleted file mode 100644 index 94a13ccff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_delay.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_DELAY_H -#define BSP_DELAY_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "bsp_compiler_support.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The number of cycles required per software delay loop. */ -#ifndef BSP_DELAY_LOOP_CYCLES - #if defined(RENESAS_CORTEX_M85) - -/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for - * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in - * this case. */ - #if defined(__ICCARM__) - #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) - #else - #define BSP_DELAY_LOOP_CYCLES (1) - #endif - #else - #define BSP_DELAY_LOOP_CYCLES (4) - #endif -#endif - -/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle - * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures - * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count - * of 0. */ -#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) - -/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ -typedef enum -{ - BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds - BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds - BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds -} bsp_delay_units_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_elc.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_elc.h deleted file mode 100644 index 9a2207791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_elc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_ELC_H -#define BSP_ELC_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU_RA6M5 - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* UNCRUSTIFY-OFF */ - -/** Sources of event signals to be linked to other peripherals or the CPU - * @note This list is device specific. - * */ -typedef enum e_elc_event_ra6m5 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end - ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end - ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end - ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end - ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end - ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete - ELC_EVENT_DTC_END = (0x02A), // DTC transfer end - ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode - ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt - ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt - ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry - ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B - ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt - ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A - ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B - ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt - ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A - ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B - ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt - ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A - ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B - ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt - ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A - ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt - ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt - ELC_EVENT_CAN_GLERR = (0x05A), // Global error - ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 - ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 - ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 - ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 - ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 - ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 - ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 - ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 - ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt - ELC_EVENT_CAN0_CHERR = (0x064), // Channel error - ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt - ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request - ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt - ELC_EVENT_CAN1_CHERR = (0x068), // Channel error - ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt - ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request - ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x073), // Receive data full - ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x075), // Transmit end - ELC_EVENT_IIC0_ERI = (0x076), // Transfer error - ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x078), // Receive data full - ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x080), // Transfer error - ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request - ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full - ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt - ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt - ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt - ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow - ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow - ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow - ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow - ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch - ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt - ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x180), // Receive data full - ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x182), // Transmit end - ELC_EVENT_SCI0_ERI = (0x183), // Receive error - ELC_EVENT_SCI0_AM = (0x184), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x186), // Receive data full - ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x188), // Transmit end - ELC_EVENT_SCI1_ERI = (0x189), // Receive error - ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI2_ERI = (0x18F), // Receive error - ELC_EVENT_SCI3_RXI = (0x192), // Receive data full - ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x194), // Transmit end - ELC_EVENT_SCI3_ERI = (0x195), // Receive error - ELC_EVENT_SCI3_AM = (0x196), // Address match event - ELC_EVENT_SCI4_RXI = (0x198), // Receive data full - ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI4_ERI = (0x19B), // Receive error - ELC_EVENT_SCI4_AM = (0x19C), // Address match event - ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI5_AM = (0x1A2), // Address match event - ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI6_AM = (0x1A8), // Address match event - ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI7_AM = (0x1AE), // Address match event - ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error - ELC_EVENT_SCI8_AM = (0x1B4), // Address match event - ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error - ELC_EVENT_SCI9_AM = (0x1BA), // Address match event - ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle - ELC_EVENT_SPI0_ERI = (0x1C7), // Error - ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle - ELC_EVENT_SPI1_ERI = (0x1CC), // Error - ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event - ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error - ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error - ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error - ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt - ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt - ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt -} elc_event_t; - -#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) - -#define ELC_PERIPHERAL_NUM (19U) -#define BSP_OVERRIDE_ELC_PERIPHERAL_T -/** Possible peripherals to be linked to event signals - * @note This list is device specific. - * */ -typedef enum e_elc_peripheral -{ - ELC_PERIPHERAL_GPT_A = (0), - ELC_PERIPHERAL_GPT_B = (1), - ELC_PERIPHERAL_GPT_C = (2), - ELC_PERIPHERAL_GPT_D = (3), - ELC_PERIPHERAL_GPT_E = (4), - ELC_PERIPHERAL_GPT_F = (5), - ELC_PERIPHERAL_GPT_G = (6), - ELC_PERIPHERAL_GPT_H = (7), - ELC_PERIPHERAL_ADC0 = (8), - ELC_PERIPHERAL_ADC0_B = (9), - ELC_PERIPHERAL_ADC1 = (10), - ELC_PERIPHERAL_ADC1_B = (11), - ELC_PERIPHERAL_DAC0 = (12), - ELC_PERIPHERAL_DAC1 = (13), - ELC_PERIPHERAL_IOPORT1 = (14), - ELC_PERIPHERAL_IOPORT2 = (15), - ELC_PERIPHERAL_IOPORT3 = (16), - ELC_PERIPHERAL_IOPORT4 = (17), - ELC_PERIPHERAL_CTSU = (18) -} elc_peripheral_t; - -/** Positions of event link set registers (ELSRs) available on this MCU */ -#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) - -/* UNCRUSTIFY-ON */ -/** @} (end addtogroup BSP_MCU_RA6M5) */ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_exceptions.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_exceptions.h deleted file mode 100644 index f388be329..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_exceptions.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_EXCEPTIONS_H - #define BSP_EXCEPTIONS_H - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ -typedef enum IRQn -{ - Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ -} IRQn_Type; - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_feature.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_feature.h deleted file mode 100644 index 29f6b43f1..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_feature.h +++ /dev/null @@ -1,588 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_FEATURE_H -#define BSP_FEATURE_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "bsp_peripheral.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ -#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) -#if (BSP_CFG_XTAL_HZ >= (20000000)) - #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (16000000)) - #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (8000000)) - #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#else - #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#endif - -// *UNCRUSTIFY-OFF* - -#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. -#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. -#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0xFFFFUL) // Create the mask for the valid calibration data provided by TSCDR. -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. -#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FFUL) // Mask of available channels in ADC unit 0. -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007UL) // Mask of available channels in ADC unit 1. -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. - -#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. -#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. -#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. -#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. - -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. -#define BSP_FEATURE_BSP_FLASH_CACHE (1UL) // Flash cache is present. -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. -#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. -#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1UL) // Indicates there is a separate clock for the CEC. -#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. -#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. -#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. -#define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. -#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. -#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. -#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0UL) // Indicates there is a separate clock for the I3C. -#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. -#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. -#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. -#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. -#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. -#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. -#define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. -#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. -#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. -#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. -#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. -#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. -#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. -#define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. -#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. -#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. -#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. -#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. -#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. -#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. -#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. -#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. -#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. -#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. - -#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. -#define BSP_FEATURE_CANFD_LITE (0UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. -#define BSP_FEATURE_CANFD_NUM_CHANNELS (2UL) // Number of CANFD channels per CANFD peripheral instance. -#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. - -#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. -#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. -#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. -#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. -#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. -#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. -#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. -#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. -#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. -#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. -#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. -#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. -#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. -#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. -#define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. -#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. -#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. -#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. -#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000UL) // Maximum input frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. -#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. -#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000UL) // PLL VCO maximum frequency. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. -#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. -#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. -#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. -#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. - -#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. -#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. -#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. - -#define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA (1UL) // RSA support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1UL) // RSA support with key-wrapping is available. - -#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. -#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. - -#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. -#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. -#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. -#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. -#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. - -#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) -#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. - -#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. -#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. - -#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. - -#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. - -#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. - -#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. - -#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. - -#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1UL) // Number of available ethernet PHYs. -#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. - -#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. -#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. -#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. -#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. -#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. -#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. -#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). -#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). -#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. - -#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. -#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. -#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. - -#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x03FFUL) // Mask of channels that support event count input (has GTUPSR register). -#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. -#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. -#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x03FFUL) // Mask of channels that support dead time control. -#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. -#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. -#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. - -#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. -#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. -#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. -#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. -#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. -#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. -#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. -#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FF0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. - -#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. - -#define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. -#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. - -#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. -#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. - -#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. -#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. -#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. -#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. -#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. -#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. -#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. -#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. -#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. -#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. - -#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. -#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. -#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. -#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. -#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. -#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. -#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. -#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. - -#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. - -#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000UL) // Start address of the CS0 memory mapped region for OSPI. -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000UL) // Start address of the CS1 memory mapped region for OSPI. - -#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. -#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. - -#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. - -#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. -#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. -#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RISP_E11A. -#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. -#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. -#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. -#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. -#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. -#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. -#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. -#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. - -#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. -#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. -#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. -#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. -#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. -#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. - -#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x03F9UL) // Mask of channels with data compare match (DCCR) available. -#define BSP_FEATURE_SCI_CHANNELS (0x03FFUL) // Mask of available SCI channels. -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. -#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. -#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x06UL) // Mask of channels that can support LIN. -#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x06UL) // List of channels that do not support ABCSE functionality. -#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9UL) // Mask of channels which support CTS external pins. -#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x03F9UL) // Mask of channels which support the UART FIFO. -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. -#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. - -#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. - -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. - -#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. - -#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. -#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. -#define BSP_FEATURE_SPI_MAX_CHANNEL (2UL) // Number of available SPI channels. -#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. - -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. - -#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. - -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. - -#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. - -#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. - -#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) -#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. -#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. -#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. - -#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) -#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. -#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. - -#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) -#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. -#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. -#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. -#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. -#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. -#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. -#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. -#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. -#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. -#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_group_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_group_irq.h deleted file mode 100644 index 5aede0736..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_group_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GROUP_IRQ_H -#define BSP_GROUP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#ifndef BSP_OVERRIDE_GROUP_IRQ_T - -/** Which interrupts can have callbacks registered. */ -typedef enum e_bsp_grp_irq -{ - BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred - BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred - BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt - BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt - BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt - BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected - BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt - BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error - BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error - BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error - BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error - BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error - BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error - BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error -} bsp_grp_irq_t; - -#endif - -/* Callback type. */ -typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_group_interrupt_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_guard.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_guard.h deleted file mode 100644 index bfad1d0e8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_guard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GUARD_H -#define BSP_GUARD_H - -#include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUp2025-07-24CallbackSet(bsp_clock_up2025-07-24_callback_t p_callback, - bsp_clock_up2025-07-24_callback_args_t * p_callback_memory); - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_io.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_io.h deleted file mode 100644 index 418c75380..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_io.h +++ /dev/null @@ -1,465 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @defgroup BSP_IO BSP I/O access - * @ingroup RENESAS_COMMON - * @brief This module provides basic read/write access to port pins. - * - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_IO_H -#define BSP_IO_H - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) -#define BSP_IO_PRV_8BIT_MASK (0xFF) -#define BSP_IO_PWPR_B0WI_OFFSET (7U) -#define BSP_IO_PWPR_PFSWE_OFFSET (6U) -#define BSP_IO_PFS_PDR_OUTPUT (4U) -#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Levels that can be set and read for individual pins */ -typedef enum e_bsp_io_level -{ - BSP_IO_LEVEL_LOW = 0, ///< Low - BSP_IO_LEVEL_HIGH ///< High -} bsp_io_level_t; - -/** Direction of individual pins */ -typedef enum e_bsp_io_dir -{ - BSP_IO_DIRECTION_INPUT = 0, ///< Input - BSP_IO_DIRECTION_OUTPUT ///< Output -} bsp_io_direction_t; - -/** Superset list of all possible IO ports. */ -typedef enum e_bsp_io_port -{ - BSP_IO_PORT_00 = 0x0000, ///< IO port 0 - BSP_IO_PORT_01 = 0x0100, ///< IO port 1 - BSP_IO_PORT_02 = 0x0200, ///< IO port 2 - BSP_IO_PORT_03 = 0x0300, ///< IO port 3 - BSP_IO_PORT_04 = 0x0400, ///< IO port 4 - BSP_IO_PORT_05 = 0x0500, ///< IO port 5 - BSP_IO_PORT_06 = 0x0600, ///< IO port 6 - BSP_IO_PORT_07 = 0x0700, ///< IO port 7 - BSP_IO_PORT_08 = 0x0800, ///< IO port 8 - BSP_IO_PORT_09 = 0x0900, ///< IO port 9 - BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 - BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 - BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 - BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 - BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 -} bsp_io_port_t; - -/** Superset list of all possible IO port pins. */ -typedef enum e_bsp_io_port_pin_t -{ - BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 - BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port -} bsp_io_port_pin_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern volatile uint32_t g_protect_pfswe_counter; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Read the current input level of the pin. - * - * @param[in] pin The pin - * - * @retval Current input level - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) -{ - /* Read pin level. */ - return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; -} - -/*******************************************************************************************************************//** - * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS - * protection using R_BSP_PinAccessEnable() before calling this function. - * - * @param[in] pin The pin - * @param[in] level The level - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) -{ - /* Clear PMR, ASEL, ISEL and PODR bits. */ - uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; - pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; - - /* Set output level and pin direction to output. */ - uint32_t lvl = ((uint32_t) level | pfs_bits); -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); -#endif -} - -/*******************************************************************************************************************//** - * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling - * this function. - * - * @param[in] pin The pin - * @param[in] cfg Configuration for the pin (PmnPFS register setting) - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) -{ - /* Configure a pin. */ -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; -#endif -} - -/*******************************************************************************************************************//** - * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur - * via multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessEnable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** If this is first entry then allow writing of PFS. */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #endif - } - - /** Increment the protect counter */ - g_protect_pfswe_counter++; - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/*******************************************************************************************************************//** - * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via - * multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessDisable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** Is it safe to disable PFS register? */ - if (0 != g_protect_pfswe_counter) - { - /* Decrement the protect counter */ - g_protect_pfswe_counter--; - } - - /** Is it safe to disable writing of PFS? */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled - #endif - } - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/** @} (end addtogroup BSP_IO) */ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_irq.h deleted file mode 100644 index ad971f32e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_irq.h +++ /dev/null @@ -1,238 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_IRQ_H -#define BSP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @brief Sets the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @param[in] p_context ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - gp_renesas_isr_context[irq] = p_context; -} - -/*******************************************************************************************************************//** - * @brief Finds the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @return ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - return gp_renesas_isr_context[irq]; -} - -#if BSP_CFG_INLINE_IRQ_FUNCTIONS - - #if BSP_FEATURE_ICU_HAS_IELSR - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit - * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) -{ - /* Clear the IR bit in the selected IELSR register. */ - R_ICU->IELSR_b[irq].IR = 0U; - - /* Read back the IELSR register to ensure that the IR bit is cleared. - * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ - FSP_REGISTER_READ(R_ICU->IELSR[irq]); -} - - #endif - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) -{ - #if BSP_FEATURE_ICU_HAS_IELSR - - /* Clear the IR bit in the selected IELSR register. */ - R_BSP_IrqStatusClear(irq); - - /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ - __DMB(); - #endif - - /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context. - * - * @param[in] irq The IRQ to configure. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions - * every time a priority is configured in the NVIC. */ - #if (4U == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (33 == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (23 == __CORTEX_M) - NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); - #else - NVIC_SetPriority(irq, priority); - #endif - - /* Store the context. The context is recovered in the ISR. */ - R_FSP_IsrContextSet(irq, p_context); -} - -/*******************************************************************************************************************//** - * Enable the IRQ in the NVIC (Without clearing the pending bit). - * - * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex - * Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) -{ - /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions - * every time an interrupt is enabled in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - - __COMPILER_BARRIER(); - NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - __COMPILER_BARRIER(); -} - -/*******************************************************************************************************************//** - * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed - * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) -{ - /* Clear pending interrupts in the ICU and NVIC. */ - R_BSP_IrqClearPending(irq); - - /* Enable the IRQ in the NVIC. */ - R_BSP_IrqEnableNoClear(irq); -} - -/*******************************************************************************************************************//** - * Disables interrupts in the NVIC. - * - * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) -{ - /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - - __DSB(); - __ISB(); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. - * - * @param[in] irq Interrupt number. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - R_BSP_IrqCfg(irq, priority, p_context); - R_BSP_IrqEnable(irq); -} - -#else - #if BSP_FEATURE_ICU_HAS_IELSR -void R_BSP_IrqStatusClear(IRQn_Type irq); - - #endif -void R_BSP_IrqClearPending(IRQn_Type irq); -void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); -void R_BSP_IrqEnableNoClear(IRQn_Type const irq); -void R_BSP_IrqEnable(IRQn_Type const irq); -void R_BSP_IrqDisable(IRQn_Type const irq); -void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); - -#endif - -/*******************************************************************************************************************//** - * @internal - * @addtogroup BSP_MCU_PRV Internal BSP Documentation - * @ingroup RENESAS_INTERNAL - * @{ - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_irq_cfg(void); // Used internally by BSP - -/** @} (end addtogroup BSP_MCU_PRV) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_macl.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_macl.h deleted file mode 100644 index 416228d5c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_macl.h +++ /dev/null @@ -1,164 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_MACL -#define RENESAS_MACL - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include -#include "bsp_api.h" - -#if BSP_FEATURE_MACL_SUPPORTED - #if __has_include("arm_math_types.h") - -/* Ignore certain math warnings in ARM CMSIS DSP headers */ - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wsign-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" - #elif defined(__GNUC__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wfloat-conversion" - #endif - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_suppress=Pe223 - #endif - - #include "arm_math_types.h" - #include "dsp/basic_math_functions.h" - #include "dsp/matrix_functions.h" - #include "dsp/filtering_functions.h" - #include "dsp/support_functions.h" - #include "dsp/fast_math_functions.h" - - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_default=Pe223 - #endif - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - #pragma GCC diagnostic pop - #endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MACL - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Common macro used by MACL */ - #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) - #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) - - #define BSP_MACL_SHIFT_SIGN (0x80) - #define BSP_MACL_SHIFT_1_BIT (1U) - #define BSP_MACL_SHIFT_30_BIT (30U) - #define BSP_MACL_SHIFT_31_BIT (31U) - #define BSP_MACL_SHIFT_32_BIT (32U) - - #define BSP_MACL_32_BIT (32U) - - #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 - #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 - - #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 - #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 - - #define BSP_MACL_CLEAR_MULR_REG (0x0U) - - #define BSP_MACL_POSITIVE_NUM (0U) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, - const arm_matrix_instance_q31 * p_src_b, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); -void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, - q31_t scale_fract, - int32_t shift, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); -void R_BSP_MaclConvQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); -arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst, - uint32_t first_idx, - uint32_t num_points); - -void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); - -void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - q31_t * p_scratch_in, - uint32_t block_size); - -void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); - -/******************************************************************************************************************//** - * @} (end addtogroup BSP_MACL) - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - - #endif -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_api.h deleted file mode 100644 index efb9bc9f5..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_api.h +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MCU_API_H -#define BSP_MCU_API_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -typedef struct st_bsp_event_info -{ - IRQn_Type irq; - elc_event_t event; -} bsp_event_info_t; - -typedef enum e_bsp_clocks_octaclk_div -{ - BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 - BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 - BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 - BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 - BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 - BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 - BSP_CLOCKS_OCTACLK_DIV_5 ///< Divide OCTA source clock by 5 -} bsp_clocks_octaclk_div_t; - -typedef enum e_bsp_clocks_source -{ - BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. - BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. - BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. - BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. - BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. - BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. - BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. -} bsp_clocks_source_t; - -typedef struct st_bsp_octaclk_settings -{ - bsp_clocks_source_t source_clock; ///< OCTACLK source clock - bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider -} bsp_octaclk_settings_t; - -void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); -void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); -fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); -void R_BSP_OctaclkUp2025-07-24(bsp_octaclk_settings_t * p_octaclk_setting); -void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_pn_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index d32ee0b1e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5AG3CFP - #define BSP_MCU_FEATURE_SET ('A') - #define BSP_ROM_SIZE_BYTES (1572864) - #define BSP_RAM_SIZE_BYTES (524288) - #define BSP_DATA_FLASH_SIZE_BYTES (8192) - #define BSP_PACKAGE_LQFP - #define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_family_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_family_cfg.h deleted file mode 100644 index a4c302306..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,394 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - - #include "bsp_mcu_device_pn_cfg.h" - #include "bsp_mcu_device_cfg.h" - #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" - #include "bsp_clock_cfg.h" - #define BSP_MCU_GROUP_RA6M5 (1) - #define BSP_LOCO_HZ (32768) - #define BSP_MOCO_HZ (8000000) - #define BSP_SUB_CLOCK_HZ (32768) - #if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (16000000) - #elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - - #define BSP_CFG_FLL_ENABLE (0) - - #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) - #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) - - #if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (0) - #endif - - /* TrustZone Settings */ - #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) - #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) - #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - - /* CMSIS TrustZone Settings */ - #define SCB_CSR_AIRCR_INIT (1) - #define SCB_AIRCR_BFHFNMINS_VAL (0) - #define SCB_AIRCR_SYSRESETREQS_VAL (1) - #define SCB_AIRCR_PRIS_VAL (0) - #define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL - #define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL - #define FPU_FPCCR_TS_VAL (1U) -#endif - #define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL - #define FPU_FPCCR_CLRONRET_VAL (1) -#endif - - /* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE - #define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - - /* Type 1 Peripheral Security Attribution */ - - /* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - - /* Type 2 Peripheral Security Attribution */ - - /* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR - /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ -#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) -#define BSP_TZ_CFG_LVDSAR (0U) -#else -#define BSP_TZ_CFG_LVDSAR (3U) -#endif -#endif - - /* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif - /* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - - /* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFE0E402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - - /* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - - /* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - - /* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - - /* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - - /* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - - /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED - #define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - - /* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - - /* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ - #define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - - /* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR - #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - - /* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA - /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ - #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - - /* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA - #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif - /* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB - #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - - /* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK - #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - - - #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) - #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) - #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) - #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) - #define OFS_SEQ5 (1 << 28) | (1 << 30) - #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - - /* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) -#else - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - - #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - - /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ - #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - - /* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL - #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - - /* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 - #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif - /* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 - #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif - /* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 - #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif - /* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 - #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif - /* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 - #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif - /* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 - #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif - /* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 - #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif - /* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 - #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif - /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 - #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif - /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 - #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif - /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 - #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif - /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 - #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif - /* Security Attribution for Bank Select Register */ -#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL - #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT - #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_info.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_info.h deleted file mode 100644 index 53c1844b3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mcu_info.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup BSP_MCU - * @defgroup BSP_MCU_RA6M5 RA6M5 - * @includedoc config_bsp_ra6m5_fsp.html - * @{ - **********************************************************************************************************************/ - -/** @} (end defgroup BSP_MCU_RA6M5) */ - -#ifndef BSP_MCU_INFO_H -#define BSP_MCU_INFO_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* BSP MCU Specific Includes. */ -#include "bsp_elc.h" -#include "bsp_feature.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -typedef elc_event_t bsp_interrupt_event_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mmf.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mmf.h deleted file mode 100644 index 9b7f1b143..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_mmf.h +++ /dev/null @@ -1,141 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MMF_H -#define BSP_MMF_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MEMORY_MIRROR_REG_KEY (0xDBU) -#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes -#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) - -/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ -#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Enum for state of Memory Mirror Function. */ -typedef enum e_mmf_state -{ - MEMORY_MIRROR_DISABLED = 0, - MEMORY_MIRROR_ENABLED = 1, -} mmf_state_t; - -/** Status instance of Memory Mirror Function. */ -typedef struct st_mmf_status -{ - mmf_state_t mmf_state; // Current state of Memory Mirror Region. - uint32_t mmf_cur_addr; // Current address in register MMSFR. -} mmf_status_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Get the current status of Memory Mirror. - * - * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. - * - * @retval FSP_SUCCESS MMF status retrieved successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. - * - * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that variable for storing the status of MMF was provided. */ - if (NULL == p_mmf_status) - { - return FSP_ERR_ASSERTION; - } - #endif - - p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; - p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_mmf_status); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/*******************************************************************************************************************//** - * Set address for MMF region. - * - * @param[in] addr Address of memory region to be mirrored into MMF region. - * - * @retval FSP_SUCCESS Address is set successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. - * - * This function sets the memory address to be mirrored by MMF. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that requested address is in supported range and must align with 128 */ - if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) - { - return FSP_ERR_INVALID_ADDRESS; - } - #endif - - /* If MMF is enabled, disable MMF before updating the address register. - * For disabling MMF, write 0xDB00 to register MMEN. */ - if (1U == R_MMF->MMEN_b.EN) - { - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); - } - - R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); - - /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into - * MMF region. */ - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(addr); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif - -/** @} (end addtogroup BSP_MCU) */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_module_stop.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_module_stop.h deleted file mode 100644 index d7312cbe8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_module_stop.h +++ /dev/null @@ -1,371 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MODULE_H -#define BSP_MODULE_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* MSTPCRA is located in R_MSTP for Star devices. */ - #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) -#else - -/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ - #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) -#endif - -/*******************************************************************************************************************//** - * Cancels the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= \ - (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/*******************************************************************************************************************//** - * Enables the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/** @} (end addtogroup BSP_MCU) */ - -#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) - #else - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - - #if BSP_MCU_GROUP_RA2A2 - -/* RA2A2 has a combination of AGT and AGTW. - * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) - * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) - * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) - * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) - */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + \ - BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); - - #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #else - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t -#else - #if (2U == BSP_FEATURE_ELC_VERSION) - #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #elif BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ - (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - \ - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #endif -#endif - -#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); - -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t - -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t -#else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#if BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); -#else - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#endif -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t -#if (BSP_PERIPHERAL_DAC8_PRESENT) - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t -#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_pin_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_pin_cfg.h deleted file mode 100644 index 362e68c4b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_pin_cfg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_PIN_CFG_H_ -#define BSP_PIN_CFG_H_ -#include "r_ioport.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - - -extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5AG3CFP.pincfg */ - -void BSP_PinConfigSecurityInit(); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif /* BSP_PIN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_register_protection.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_register_protection.h deleted file mode 100644 index ca4b64c20..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_register_protection.h +++ /dev/null @@ -1,60 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_REGISTER_PROTECTION_H -#define BSP_REGISTER_PROTECTION_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/** The different types of registers that can be protected. */ -typedef enum e_bsp_reg_protect -{ - /** Enables writing to the registers related to the clock generation circuit. */ - BSP_REG_PROTECT_CGC = 0, - - /** Enables writing to the registers related to operating modes, low power consumption, and battery backup - * function. */ - BSP_REG_PROTECT_OM_LPC_BATT, - - /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, - * LVD2CR1, LVD2SR. */ - BSP_REG_PROTECT_LVD, - - /** Enables writing to the registers related to the security function. */ - BSP_REG_PROTECT_SAR, -} bsp_reg_protect_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_register_protect_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_sdram.h deleted file mode 100644 index 5ba56a638..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SDRAM_H -#define BSP_SDRAM_H - -#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_SdramInit(bool init_memory); -void R_BSP_SdramSelfRefreshEnable(void); -void R_BSP_SdramSelfRefreshDisable(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_security.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_security.h deleted file mode 100644 index 3ceb51f92..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_security.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SECURITY_H -#define BSP_SECURITY_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_NonSecureEnter(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_tfu.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_tfu.h deleted file mode 100644 index 98b09caee..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/bsp_tfu.h +++ /dev/null @@ -1,218 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_TFU -#define RENESAS_TFU - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* Mathematical Functions includes. */ -#ifdef __cplusplus - #include -#else - #include -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TFU_SUPPORTED - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - - #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f - - #ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) - -/* No form of inline is available, it happens only when -std=c89, gnu89 and - * above are OK */ - #warning \ - "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ - -/* gnu89 semantics of inline and extern inline are essentially the exact - * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) - #endif - #endif - #elif __ICCARM__ - #define BSP_TFU_INLINE - #else - #error "Compiler not supported!" - #endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Calculates sine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Sine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __sinf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - return R_TFU->SCDT1; -} - -/*******************************************************************************************************************//** - * Calculates cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __cosf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read cos from R_TFU->SCDT1 */ - return R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates sine and cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * @param[out] sin Sine value of an angle. - * @param[out] cos Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - *sin = R_TFU->SCDT1; - - /* Read sin from R_TFU->SCDT1 */ - *cos = R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-Axis cordinate value. - * @param[in] x_cord X-Axis cordinate value. - * - * @retval Arc tangent for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) -{ - /* Set X-cordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-cordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - return R_TFU->ATDT1; -} - -/*******************************************************************************************************************//** - * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * - * @retval Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * @param[out] atan2 Arc tangent for given values. - * @param[out] hypot Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - *atan2 = R_TFU->ATDT1; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - - #if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) - #endif - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif /* RENESAS_TFU */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_common_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_common_api.h deleted file mode 100644 index 208863b46..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_common_api.h +++ /dev/null @@ -1,380 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_COMMON_API_H -#define FSP_COMMON_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include -#include - -/* Includes FSP version macros. */ -#include "fsp_version.h" - -/*******************************************************************************************************************//** - * @ingroup RENESAS_COMMON - * @defgroup RENESAS_ERROR_CODES Common Error Codes - * All FSP modules share these common error codes. - * @{ - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing - * about using this implementation is that it does not take any extra RAM or ROM. */ - -#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) - -/** Determine if a C++ compiler is being used. - * If so, ensure that standard C is used to process the API information. */ -#if defined(__cplusplus) - #define FSP_CPP_HEADER extern "C" { - #define FSP_CPP_FOOTER } -#else - #define FSP_CPP_HEADER - #define FSP_CPP_FOOTER -#endif - -/** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically - * defined on the Secure side. */ -#define FSP_SECURE_ARGUMENT (NULL) - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Common error codes */ -typedef enum e_fsp_err -{ - FSP_SUCCESS = 0, - - FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed - FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location - FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter - FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist - FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode - FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API - FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open - FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy - FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h - FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked - FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP - FSP_ERR_OVERFLOW = 12, ///< Hardware overflow - FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow - FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration - FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result - FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason - FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met - FSP_ERR_ABORTED = 18, ///< An operation was aborted - FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled - FSP_ERR_TIMEOUT = 20, ///< Timeout error - FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied - FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied - FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation - FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed - FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed - FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made - FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition - FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU - FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state - FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed - FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed - FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete - FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found - FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback - FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer - FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed - - /* Start of RTOS only error codes */ - FSP_ERR_INTERNAL = 100, ///< Internal error - FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted - - /* Start of UART specific */ - FSP_ERR_FRAMING = 200, ///< Framing error occurs - FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects - FSP_ERR_PARITY = 202, ///< Parity error occurs - FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow - FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue - FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer - FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer - - /* Start of SPI specific */ - FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. - FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. - FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. - FSP_ERR_SPI_PARITY = 303, ///< Parity error. - FSP_ERR_OVERRUN = 304, ///< Overrun error. - - /* Start of CGC Specific */ - FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. - FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. - FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off - FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off - FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled - FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set - FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active - FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit - FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled - FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out - FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode - - /* Start of FLASH Specific */ - FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. - FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state - FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz - FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory - FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed - - /* Start of CAC Specific */ - FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate - - /* Start of IIRFA Specific */ - FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. - - /* Start of GLCD Specific */ - FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock - FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter - FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter - FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found - FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter - FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer - FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register up2025-07-24 - FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry - FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting - FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter - - /* Start of JPEG Specific */ - FSP_ERR_JPEG_ERR = 1100, ///< JPEG error - FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. - FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. - FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. - FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. - FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. - FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. - FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. - FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. - FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. - FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) - FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. - FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. - FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. - FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. - FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough - FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU - - /* Start of touch panel framework specific */ - FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed - - /* Start of IIRFA specific */ - FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected - FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected - - /* Start of IP specific */ - FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device - FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device - FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device - - /* Start of USB specific */ - FSP_ERR_USB_FAILED = 1500, - FSP_ERR_USB_BUSY = 1501, - FSP_ERR_USB_SIZE_SHORT = 1502, - FSP_ERR_USB_SIZE_OVER = 1503, - FSP_ERR_USB_NOT_OPEN = 1504, - FSP_ERR_USB_NOT_SUSPEND = 1505, - FSP_ERR_USB_PARAMETER = 1506, - - /* Start of Message framework specific */ - FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool - FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool - FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid - FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid - FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many - FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found - FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue - FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue - FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal - FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released - - /* Start of 2DG Driver specific */ - FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering - FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering - - /* Start of ETHER Driver specific */ - FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. - FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation - FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled - FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty - FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable - FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication - FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. - - /* Start of ETHER_PHY Driver specific */ - FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. - FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation - - /* Start of BYTEQ library specific */ - FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data - FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue - - /* Start of CTSU Driver specific */ - FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. - FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. - FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. - FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. - FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. - FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. - FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. - FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. - FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. - FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. - FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. - FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. - FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. - FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. - FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. - FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. - - /* Start of SDMMC specific */ - FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. - FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. - FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. - FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. - FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. - FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. - FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. - - /* Start of FX_IO specific */ - FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. - FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. - - /* Start of CAN specific */ - FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. - FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. - FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. - FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. - FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. - FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. - FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. - FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. - - /* Start of SF_WIFI Specific */ - FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. - FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. - FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed - FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode - FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. - FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. - FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point - FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error - FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter - FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value - FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result - FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured - FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure - FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure - FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error - - /* Start of SF_CELLULAR Specific */ - FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. - FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. - FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed - FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is upto2025-07-24 - FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed - FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. - FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. - FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed - - /* Start of SF_BLE specific */ - FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed - FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed - FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed - FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled - FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled - - /* Start of SF_BLE_ABS specific */ - FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. - FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. - - /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ - FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function - FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy - FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty - FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index - FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry - FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed - FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened - FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized - FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred - FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter - FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented - FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified - FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred - FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid - FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state - FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened - FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. - FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher - FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input 2025-07-24 is illegal. - FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. - - /* Start of Crypto RSIP specific (0x10100) */ - FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy - FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return - FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error - FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal - FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed - - /* Start of SF_CRYPTO specific */ - FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened - FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error - FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key - FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold - FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. - FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. - FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. - - /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. - * Refer to sf_cryoto_err.h for Crypto error codes. - */ - - /* Start of Sensor specific */ - FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. - FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. - FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. - - /* Start of COMMS specific */ - FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. -} fsp_err_t; - -/** @} */ - -/*********************************************************************************************************************** - * Function prototypes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_features.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_features.h deleted file mode 100644 index dd54197d7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_features.h +++ /dev/null @@ -1,297 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_FEATURES_H -#define FSP_FEATURES_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include - -/* Different compiler support. */ -#include "fsp_common_api.h" -#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Available modules. */ -typedef enum e_fsp_ip -{ - FSP_IP_CFLASH = 0, ///< Code Flash - FSP_IP_DFLASH = 1, ///< Data Flash - FSP_IP_RAM = 2, ///< RAM - FSP_IP_LVD = 3, ///< Low Voltage Detection - FSP_IP_CGC = 3, ///< Clock Generation Circuit - FSP_IP_LPM = 3, ///< Low Power Modes - FSP_IP_FCU = 4, ///< Flash Control Unit - FSP_IP_ICU = 6, ///< Interrupt Control Unit - FSP_IP_DMAC = 7, ///< DMA Controller - FSP_IP_DTC = 8, ///< Data Transfer Controller - FSP_IP_IOPORT = 9, ///< I/O Ports - FSP_IP_PFS = 10, ///< Pin Function Select - FSP_IP_ELC = 11, ///< Event Link Controller - FSP_IP_MPU = 13, ///< Memory Protection Unit - FSP_IP_MSTP = 14, ///< Module Stop - FSP_IP_MMF = 15, ///< Memory Mirror Function - FSP_IP_KEY = 16, ///< Key Interrupt Function - FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit - FSP_IP_DOC = 18, ///< Data Operation Circuit - FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator - FSP_IP_SCI = 20, ///< Serial Communications Interface - FSP_IP_IIC = 21, ///< I2C Bus Interface - FSP_IP_SPI = 22, ///< Serial Peripheral Interface - FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit - FSP_IP_SCE = 24, ///< Secure Cryptographic Engine - FSP_IP_SLCDC = 25, ///< Segment LCD Controller - FSP_IP_AES = 26, ///< Advanced Encryption Standard - FSP_IP_TRNG = 27, ///< True Random Number Generator - FSP_IP_FCACHE = 30, ///< Flash Cache - FSP_IP_SRAM = 31, ///< SRAM - FSP_IP_ADC = 32, ///< A/D Converter - FSP_IP_DAC = 33, ///< 12-Bit D/A Converter - FSP_IP_TSN = 34, ///< Temperature Sensor - FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit - FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator - FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator - FSP_IP_OPAMP = 38, ///< Operational Amplifier - FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter - FSP_IP_RTC = 40, ///< Real Time Clock - FSP_IP_WDT = 41, ///< Watch Dog Timer - FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer - FSP_IP_GPT = 43, ///< General PWM Timer - FSP_IP_POEG = 44, ///< Port Output Enable for GPT - FSP_IP_OPS = 45, ///< Output Phase Switch - FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer - FSP_IP_CAN = 48, ///< Controller Area Network - FSP_IP_IRDA = 49, ///< Infrared Data Association - FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface - FSP_IP_USBFS = 51, ///< USB Full Speed - FSP_IP_SDHI = 52, ///< SD/MMC Host Interface - FSP_IP_SRC = 53, ///< Sampling Rate Converter - FSP_IP_SSI = 54, ///< Serial Sound Interface - FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface - FSP_IP_ETHER = 64, ///< Ethernet MAC Controller - FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller - FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller - FSP_IP_PDC = 66, ///< Parallel Data Capture Unit - FSP_IP_GLCDC = 67, ///< Graphics LCD Controller - FSP_IP_DRW = 68, ///< 2D Drawing Engine - FSP_IP_JPEG = 69, ///< JPEG - FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter - FSP_IP_USBHS = 71, ///< USB High Speed - FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface - FSP_IP_CEC = 73, ///< HDMI CEC - FSP_IP_TFU = 74, ///< Trigonometric Function Unit - FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator - FSP_IP_CANFD = 76, ///< CAN-FD - FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT - FSP_IP_SAU = 78, ///< Serial Array Unit - FSP_IP_IICA = 79, ///< Serial Interface IICA - FSP_IP_UARTA = 80, ///< Serial Interface UARTA - FSP_IP_TAU = 81, ///< Timer Array Unit - FSP_IP_TML = 82, ///< 32-bit Interval Timer - FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator - FSP_IP_USBCC = 84, ///< USB Type-C Controller -} fsp_ip_t; - -/** Signals that can be mapped to an interrupt. */ -typedef enum e_fsp_signal -{ - FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH - FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH - FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END - FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B - FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A - FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B - FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ - FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ - FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A - FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B - FSP_SIGNAL_AGT_INT, ///< AGT INT - FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR - FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END - FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW - FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR - FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX - FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX - FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX - FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX - FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP - FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST - FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 - FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 - FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD - FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT - FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT - FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT - FSP_SIGNAL_CTSU_END = 0, ///< CTSU END - FSP_SIGNAL_CTSU_READ, ///< CTSU READ - FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE - FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI - FSP_SIGNAL_DALI_CLI, ///< DALI CLI - FSP_SIGNAL_DALI_SDI, ///< DALI SDI - FSP_SIGNAL_DALI_BPI, ///< DALI BPI - FSP_SIGNAL_DALI_FEI, ///< DALI FEI - FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI - FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT - FSP_SIGNAL_DOC_INT = 0, ///< DOC INT - FSP_SIGNAL_DRW_INT = 0, ///< DRW INT - FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE - FSP_SIGNAL_DTC_END, ///< DTC END - FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT - FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 - FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 - FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS - FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT - FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT - FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL - FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE - FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL - FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE - FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL - FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE - FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL - FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE - FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL - FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE - FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL - FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE - FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR - FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI - FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT - FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 - FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 - FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A - FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B - FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C - FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D - FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E - FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F - FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW - FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW - FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A - FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B - FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE - FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 - FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 - FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 - FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 - FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 - FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 - FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 - FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 - FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 - FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 - FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 - FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 - FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 - FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 - FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 - FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 - FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL - FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI - FSP_SIGNAL_IIC_RXI, ///< IIC RXI - FSP_SIGNAL_IIC_TEI, ///< IIC TEI - FSP_SIGNAL_IIC_TXI, ///< IIC TXI - FSP_SIGNAL_IIC_WUI, ///< IIC WUI - FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 - FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 - FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 - FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 - FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B - FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C - FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D - FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E - FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW - FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI - FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI - FSP_SIGNAL_KEY_INT = 0, ///< KEY INT - FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END - FSP_SIGNAL_PDC_INT, ///< PDC INT - FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY - FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT - FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT - FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM - FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD - FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY - FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY - FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY - FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG - FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY - FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 - FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 - FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK - FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY - FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 - FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 - FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 - FSP_SIGNAL_SCI_AM = 0, ///< SCI AM - FSP_SIGNAL_SCI_ERI, ///< SCI ERI - FSP_SIGNAL_SCI_RXI, ///< SCI RXI - FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI - FSP_SIGNAL_SCI_TEI, ///< SCI TEI - FSP_SIGNAL_SCI_TXI, ///< SCI TXI - FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI - FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND - FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND - FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS - FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD - FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ - FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO - FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI - FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE - FSP_SIGNAL_SPI_RXI, ///< SPI RXI - FSP_SIGNAL_SPI_TEI, ///< SPI TEI - FSP_SIGNAL_SPI_TXI, ///< SPI TXI - FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END - FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY - FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL - FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW - FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW - FSP_SIGNAL_SSI_INT = 0, ///< SSI INT - FSP_SIGNAL_SSI_RXI, ///< SSI RXI - FSP_SIGNAL_SSI_TXI, ///< SSI TXI - FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI - FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ - FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 - FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 - FSP_SIGNAL_USB_INT, ///< USB INT - FSP_SIGNAL_USB_RESUME, ///< USB RESUME - FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW - FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A - FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B - FSP_SIGNAL_ULPT_INT, ///< ULPT INT -} fsp_signal_t; - -typedef void (* fsp_vector_t)(void); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_version.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_version.h deleted file mode 100644 index 54b5c25ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/fsp_version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_VERSION_H - #define FSP_VERSION_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ - #include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup RENESAS_COMMON - * @{ - **********************************************************************************************************************/ - - #ifdef __cplusplus -extern "C" { - #endif - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** FSP pack major version. */ - #define FSP_VERSION_MAJOR (5U) - -/** FSP pack minor version. */ - #define FSP_VERSION_MINOR (8U) - -/** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) - -/** FSP pack version build number (currently unused). */ - #define FSP_VERSION_BUILD (0U) - -/** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.8.0") - -/** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.8.0") - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** FSP Pack version structure */ -typedef union st_fsp_pack_version -{ - /** Version id */ - uint32_t version_id; - - /** - * Code version parameters, little endian order. - */ - struct version_id_b_s - { - uint8_t build; ///< Build version of FSP Pack - uint8_t patch; ///< Patch version of FSP Pack - uint8_t minor; ///< Minor version of FSP Pack - uint8_t major; ///< Major version of FSP Pack - } version_id_b; -} fsp_pack_version_t; - -/** @} */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/instance/r_ioport.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/instance/r_ioport.h deleted file mode 100644 index 14abb229e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/instance/r_ioport.h +++ /dev/null @@ -1,522 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup IOPORT - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_H -#define R_IOPORT_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "r_ioport_api.h" -#if __has_include("r_ioport_cfg.h") - #include "r_ioport_cfg.h" -#endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ -typedef struct st_ioport_instance_ctrl -{ - uint32_t open; - void const * p_context; -} ioport_instance_ctrl_t; - -/* This typedef is here temporarily. See SWFLEX-144 for details. */ -/** Superset list of all possible IO port pins. */ -typedef enum e_ioport_port_pin_t -{ - IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 -} ioport_port_pin_t; - -#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #endif - - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an UARTA peripheral pin */ - IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; -#endif - -#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; -#endif - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const ioport_api_t g_ioport_on_ioport; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ - -fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); -fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); -fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); -fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); -fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); -fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); -fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t direction_values, - ioport_size_t mask); -fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); -fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t event_data, - ioport_size_t mask_value); -fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); -fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_IOPORT_H diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/periph/bsp_peripheral.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/periph/bsp_peripheral.h deleted file mode 100644 index bcaaf823c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/periph/bsp_peripheral.h +++ /dev/null @@ -1,211 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_PERIPHERAL_H -#define BSP_PERIPHERAL_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -// *UNCRUSTIFY-OFF* - -#define BSP_PERIPHERAL_ACMP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_PRESENT (1) -#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ADC_B_PRESENT (0) -#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_D_PRESENT (0) -#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AGT_PRESENT (1) -#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) -#define BSP_PERIPHERAL_AGTW_PRESENT (0) -#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AMI_PRESENT (0) -#define BSP_PERIPHERAL_ANALOG_PRESENT (1) -#define BSP_PERIPHERAL_BUS_PRESENT (1) -#define BSP_PERIPHERAL_CAC_PRESENT (1) -#define BSP_PERIPHERAL_CACHE_PRESENT (1) -#define BSP_PERIPHERAL_CAN_PRESENT (0) -#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_CANFD_PRESENT (1) -#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_CEC_PRESENT (1) -#define BSP_PERIPHERAL_CEU_PRESENT (0) -#define BSP_PERIPHERAL_CGC_PRESENT (1) -#define BSP_PERIPHERAL_CPSCU_PRESENT (1) -#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) -#define BSP_PERIPHERAL_CRC_PRESENT (1) -#define BSP_PERIPHERAL_CTSU_PRESENT (1) -#define BSP_PERIPHERAL_DAC_PRESENT (1) -#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DAC_B_PRESENT (0) -#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC8_PRESENT (0) -#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC12_PRESENT (1) -#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DEBUG_PRESENT (1) -#define BSP_PERIPHERAL_DMA_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) -#define BSP_PERIPHERAL_DOC_PRESENT (1) -#define BSP_PERIPHERAL_DOC_B_PRESENT (0) -#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) -#define BSP_PERIPHERAL_DRW_PRESENT (0) -#define BSP_PERIPHERAL_DSILINK_PRESENT (0) -#define BSP_PERIPHERAL_DTC_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ECCMB_PRESENT (1) -#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ELC_PRESENT (1) -#define BSP_PERIPHERAL_ELC_B_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_FACI_PRESENT (1) -#define BSP_PERIPHERAL_FCACHE_PRESENT (1) -#define BSP_PERIPHERAL_FLAD_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) -#define BSP_PERIPHERAL_GLCDC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_PRESENT (1) -#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) -#define BSP_PERIPHERAL_I3C_PRESENT (0) -#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ICU_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) -#define BSP_PERIPHERAL_IIC_PRESENT (1) -#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) -#define BSP_PERIPHERAL_IIC_B_PRESENT (0) -#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) -#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) -#define BSP_PERIPHERAL_IICA_PRESENT (0) -#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IPC_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_PRESENT (0) -#define BSP_PERIPHERAL_IRTC_PRESENT (0) -#define BSP_PERIPHERAL_IWDT_PRESENT (1) -#define BSP_PERIPHERAL_JPEG_PRESENT (0) -#define BSP_PERIPHERAL_KINT_PRESENT (0) -#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_MACL_PRESENT (0) -#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) -#define BSP_PERIPHERAL_MMF_PRESENT (0) -#define BSP_PERIPHERAL_MPU_PRESENT (1) -#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_MRMS_PRESENT (0) -#define BSP_PERIPHERAL_MRRGE_PRESENT (0) -#define BSP_PERIPHERAL_MSTP_PRESENT (1) -#define BSP_PERIPHERAL_OCD_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_OSPI_PRESENT (1) -#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) -#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) -#define BSP_PERIPHERAL_PDC_PRESENT (0) -#define BSP_PERIPHERAL_PFS_PRESENT (1) -#define BSP_PERIPHERAL_PFS_B_PRESENT (0) -#define BSP_PERIPHERAL_PMISC_PRESENT (0) -#define BSP_PERIPHERAL_PORGA_PRESENT (0) -#define BSP_PERIPHERAL_PORT_PRESENT (1) -#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) -#define BSP_PERIPHERAL_PSCU_PRESENT (1) -#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) -#define BSP_PERIPHERAL_QSPI_PRESENT (1) -#define BSP_PERIPHERAL_RADIO_PRESENT (0) -#define BSP_PERIPHERAL_RSIP_PRESENT (1) -#define BSP_PERIPHERAL_RTC_PRESENT (1) -#define BSP_PERIPHERAL_RTC_C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_PRESENT (0) -#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) -#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) -#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SCI_PRESENT (1) -#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_SCI_B_PRESENT (0) -#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDHI_PRESENT (1) -#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SLCDC_PRESENT (0) -#define BSP_PERIPHERAL_SPI_PRESENT (1) -#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_SPI_B_PRESENT (0) -#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SPMON_PRESENT (0) -#define BSP_PERIPHERAL_SRAM_PRESENT (1) -#define BSP_PERIPHERAL_SRC_PRESENT (0) -#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) -#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) -#define BSP_PERIPHERAL_TAU_PRESENT (0) -#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TFU_PRESENT (0) -#define BSP_PERIPHERAL_TML_PRESENT (0) -#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TRNG_PRESENT (0) -#define BSP_PERIPHERAL_TSD_PRESENT (1) -#define BSP_PERIPHERAL_TSN_PRESENT (1) -#define BSP_PERIPHERAL_TZF_PRESENT (1) -#define BSP_PERIPHERAL_UARTA_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ULPT_PRESENT (0) -#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_USB_PRESENT (1) -#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_USB_FS_PRESENT (1) -#define BSP_PERIPHERAL_USB_HS_PRESENT (1) -#define BSP_PERIPHERAL_USBCC_PRESENT (0) -#define BSP_PERIPHERAL_WDT_PRESENT (1) -#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_api.h deleted file mode 100644 index dcb104b06..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_SYSTEM_INTERFACES - * @defgroup IOPORT_API I/O Port Interface - * @brief Interface for accessing I/O ports and configuring I/O functionality. - * - * @section IOPORT_API_SUMMARY Summary - * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. - * Port and pin direction can be changed. - * - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_API_H -#define R_IOPORT_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common error codes and definitions. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -#ifndef BSP_OVERRIDE_IOPORT_SIZE_T - -/** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size -#endif - -/** Pin identifier and pin configuration value */ -typedef struct st_ioport_pin_cfg -{ - uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure - bsp_io_port_pin_t pin; ///< Pin identifier -} ioport_pin_cfg_t; - -/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ -typedef struct st_ioport_cfg -{ - uint16_t number_of_pins; ///< Number of pins for which there is configuration data - ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data - const void * p_extend; ///< Pointer to hardware extend configuration -} ioport_cfg_t; - -/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - */ -typedef void ioport_ctrl_t; - -/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ -typedef struct st_ioport_api -{ - /** Initialize internal driver data and initial pin configurations. Called during startup. Do - * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of - * multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Close the API. - * - * @param[in] p_ctrl Pointer to control structure. - **/ - fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); - - /** Configure multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Configure settings for an individual pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] cfg Configuration options for the pin. - */ - fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); - - /** Read the event input data of the specified pin and return the level. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_event Pointer to return the event data. - */ - fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); - - /** Write pin event data. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin event data is to be written to. - * @param[in] pin_value Level to be written to pin output event. - */ - fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); - - /** Read level of a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_value Pointer to return the pin level. - */ - fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); - - /** Write specified level to a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be written to. - * @param[in] level State to be written to the pin. - */ - fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); - - /** Set the direction of one or more pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port. - * @param[in] mask Mask controlling which pins on the port are to be configured. - */ - fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, - ioport_size_t mask); - - /** Read captured event data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_event_data Pointer to return the event data. - */ - fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); - - /** Write event output data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port event data will be written to. - * @param[in] event_data Data to be written as event data to specified port. - * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. - * being written to port. - */ - fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, - ioport_size_t mask_value); - - /** Read states of pins on the specified port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_port_value Pointer to return the port value. - */ - fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); - - /** Write to multiple pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be written to. - * @param[in] value Value to be written to the port. - * @param[in] mask Mask controlling which pins on the port are written to. - */ - fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); -} ioport_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_ioport_instance -{ - ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - ioport_api_t const * p_api; ///< Pointer to the API structure for this instance -} ioport_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT_API) - **********************************************************************************************************************/ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_cfg.h deleted file mode 100644 index d2688bf5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/r_ioport_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#ifdef __cplusplus -} -#endif -#endif /* R_IOPORT_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/renesas.h b/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/renesas.h deleted file mode 100644 index 41098a054..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/thirdparty/ra6m5ag/renesas.h +++ /dev/null @@ -1,154 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* Ensure Renesas MCU variation definitions are included to ensure MCU - * specific register variations are handled correctly. */ -#ifndef BSP_FEATURE_H - #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." -#endif - -/** @addtogroup Renesas - * @{ - */ - -/** @addtogroup RA - * @{ - */ - -#ifndef RA_H - #define RA_H - - #ifdef __cplusplus -extern "C" { - #endif - - #include "cmsis_compiler.h" - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - - #if BSP_MCU_GROUP_RA0E1 - #include "R7FA0E107.h" - #elif BSP_MCU_GROUP_RA2A1 - #include "R7FA2A1AB.h" - #elif BSP_MCU_GROUP_RA2A2 - #include "R7FA2A2AD.h" - #elif BSP_MCU_GROUP_RA2E1 - #include "R7FA2E1A9.h" - #elif BSP_MCU_GROUP_RA2E2 - #include "R7FA2E2A7.h" - #elif BSP_MCU_GROUP_RA2E3 - #include "R7FA2E307.h" - #elif BSP_MCU_GROUP_RA2L1 - #include "R7FA2L1AB.h" - #elif BSP_MCU_GROUP_RA4E1 - #include "R7FA4E10D.h" - #elif BSP_MCU_GROUP_RA4E2 - #include "R7FA4E2B9.h" - #elif BSP_MCU_GROUP_RA4M1 - #include "R7FA4M1AB.h" - #elif BSP_MCU_GROUP_RA4M2 - #include "R7FA4M2AD.h" - #elif BSP_MCU_GROUP_RA4M3 - #include "R7FA4M3AF.h" - #elif BSP_MCU_GROUP_RA4T1 - #include "R7FA4T1BB.h" - #elif BSP_MCU_GROUP_RA4W1 - #include "R7FA4W1AD.h" - #elif BSP_MCU_GROUP_RA4L1 - #include "R7FA4L1BD.h" - #elif BSP_MCU_GROUP_RA6E1 - #include "R7FA6E10F.h" - #elif BSP_MCU_GROUP_RA6E2 - #include "R7FA6E2BB.h" - #elif BSP_MCU_GROUP_RA6M1 - #include "R7FA6M1AD.h" - #elif BSP_MCU_GROUP_RA6M2 - #include "R7FA6M2AF.h" - #elif BSP_MCU_GROUP_RA6M3 - #include "R7FA6M3AH.h" - #elif BSP_MCU_GROUP_RA6M4 - #include "R7FA6M4AF.h" - #elif BSP_MCU_GROUP_RA6M5 - #include "R7FA6M5BH.h" - #elif BSP_MCU_GROUP_RA6T1 - #include "R7FA6T1AD.h" - #elif BSP_MCU_GROUP_RA6T2 - #include "R7FA6T2BD.h" - #elif BSP_MCU_GROUP_RA6T3 - #include "R7FA6T3BB.h" - #elif BSP_MCU_GROUP_RA8M1 - #include "R7FA8M1AH.h" - #elif BSP_MCU_GROUP_RA8D1 - #include "R7FA8D1BH.h" - #elif BSP_MCU_GROUP_RA8T1 - #include "R7FA8T1AH.h" - #elif BSP_MCU_GROUP_RA8E1 - #include "R7FA8E1AF.h" - #else - #if __has_include("renesas_internal.h") - #include "renesas_internal.h" - #else - #warning "Unsupported MCU" - #endif - #endif - -/* - * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB - * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 - * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: - * - * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | - * |-----------|------------|------------------------| - * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | - * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | - * - * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ - * - * IAR is currently the only toolchain producing the correct __ARM_ARCH value. - * - *- See https://github.com/ARM-software/CMSIS_6/issues/159 - */ - #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 - #undef __ARM_ARCH - #define __ARM_ARCH 801 - #endif - - #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M4 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) - #define RENESAS_CORTEX_M23 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M33 - #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M85 - #else - #warning Unsupported Architecture - #endif - - #ifdef __cplusplus -} - #endif - -#endif /* RA_H */ - -/** @} */ /* End of group RA */ - -/** @} */ /* End of group Renesas */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/R7FA6M5BH.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/R7FA6M5BH.h deleted file mode 100644 index a9dc40ce4..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/R7FA6M5BH.h +++ /dev/null @@ -1,29959 +0,0 @@ -/* - * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause - * - * @file ./out/R7FA6M5BH.h - * @brief CMSIS HeaderFile - * @version 1.10.08 - */ - -/** @addtogroup Renesas Electronics Corporation - * @{ - */ - -/** @addtogroup R7FA6M5BH - * @{ - */ - -#ifndef R7FA6M5BH_H - #define R7FA6M5BH_H - - #ifdef __cplusplus -extern "C" { - #endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ - #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ - #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ - #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ - #define __MPU_PRESENT 1 /*!< MPU present */ - #define __FPU_PRESENT 1 /*!< FPU present */ - #define __FPU_DP 0 /*!< Double Precision FPU */ - #define __DSP_PRESENT 1 /*!< DSP extension present */ - #define __SAUREGION_PRESENT 0 /*!< SAU region present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - - #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ - #include "system.h" /*!< R7FA6M5BH System */ - - #ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I - #endif - #ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O - #endif - #ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO - #endif - -/* ======================================== Start of section using anonymous unions ======================================== */ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined(__ICCARM__) - #pragma language=extended - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning 586 - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #else - #warning Not supported compiler type - #endif - -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - -/** - * @brief R_BUS_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ - - struct - { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; - }; - - union - { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ - - struct - { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; - }; - __IM uint32_t RESERVED1; -} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_CSb [CSb] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ - - struct - { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; - }; - __IM uint16_t RESERVED1[3]; - - union - { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ - - struct - { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; - }; - __IM uint16_t RESERVED2[2]; -} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ - - struct - { - __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint8_t : 3; - __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ - uint8_t : 2; - } SDCCR_b; - }; - - union - { - __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ - - struct - { - __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ - uint8_t : 7; - } SDCMOD_b; - }; - - union - { - __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ - - struct - { - __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ - uint8_t : 7; - } SDAMOD_b; - }; - __IM uint8_t RESERVED; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ - - struct - { - __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ - uint8_t : 7; - } SDSELF_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ - - struct - { - __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ - __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count - * Setting. ( REFW+1 Cycles ) */ - } SDRFCR_b; - }; - - union - { - __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ - - struct - { - __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ - uint8_t : 7; - } SDRFEN_b; - }; - __IM uint8_t RESERVED4; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ - - struct - { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ - - struct - { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; - - union - { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ - - struct - { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ - - struct - { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; - }; - - union - { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ - - struct - { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ - uint16_t : 1; - } SDMOD_b; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; - - union - { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ - - struct - { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; - }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ - -/** - * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ - } ADD_b; - }; - - union - { - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ - } STAT_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ - - struct - { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ - - struct - { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ - - struct - { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ - - struct - { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ - __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ - uint8_t : 2; - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - - struct - { - __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when - * a bus error occurs */ - uint32_t : 31; - } IRQEN_b; - }; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ - - struct - { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; - }; - }; - __IM uint32_t RESERVED3; -} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[36]; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ - - struct - { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } STAT_b; - }; - __IM uint8_t RESERVED1[7]; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ - - struct - { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } CLR_b; - }; -} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ - -/** - * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } MRE0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } FLBI_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S0BI_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S1BI_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S2BI_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S3BI_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } STBYSBI_b; - }; - __IM uint32_t RESERVED7; - - union - { - union - { - __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } ECBI_b; - }; - - union - { - __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI0BI_b; - }; - }; - __IM uint32_t RESERVED8; - - union - { - union - { - __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } EOBI_b; - }; - - union - { - __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI1BI_b; - }; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PBBI_b; - }; - __IM uint32_t RESERVED10; - - union - { - union - { - __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PABI_b; - }; - - union - { - __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU0SAHBI_b; - }; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PSBI_b; - }; -} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ - -/** - * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } FHBI_b; - }; - - union - { - __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } MRC0BI_b; - }; - }; - __IM uint32_t RESERVED[5]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S1BI_b; - }; -} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ - -/** - * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ - - struct - { - __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read - * Write. */ - - struct - { - __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write - * Status. */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - - struct - { - __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ - __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ - __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ - uint16_t : 13; - } BUSOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } BUSOADPT_b; - }; - __IM uint16_t RESERVED1[5]; - - union - { - __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection - * Register. */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ - } MSAOAD_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } MSAPT_b; - }; -} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ - -/** - * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ - - struct - { - __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ - __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ - __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ - __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ - __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ - __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ - __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ - __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ - __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ - __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ - __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ - __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ - __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ - __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ - __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ - __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ - __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ - __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ - __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ - __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ - __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ - __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ - __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ - __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ - __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ - __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ - __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ - __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ - __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ - __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ - __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ - __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ - } STAT_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ - - struct - { - __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ - __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ - __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ - __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ - __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ - __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ - __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ - __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ - __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ - __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ - __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ - __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ - __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ - __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ - __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ - __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ - __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ - __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ - __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ - __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ - __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ - __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ - __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ - __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ - __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ - __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ - __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ - __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ - __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ - __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ - __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ - __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ - } CLR_b; - }; -} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ - -/** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - - struct - { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ - uint16_t : 2; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ - uint16_t : 10; - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) - */ -typedef struct -{ - union - { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ - - struct - { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; - }; - - union - { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ - - struct - { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; - }; - - union - { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ - - struct - { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; - }; - - union - { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ - - struct - { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; - }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ - - struct - { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; - }; - - union - { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ - - struct - { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ - - struct - { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; - }; - - union - { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ - - struct - { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; - }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ - union - { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ - - struct - { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; - }; - - union - { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct - { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - - struct - { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - - struct - { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct - { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ - - struct - { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - - struct - { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - - struct - { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ - - struct - { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ - - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ - union - { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - - struct - { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; - }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ - union - { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ - - struct - { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; - }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) - */ -typedef struct -{ - union - { - __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ - uint16_t : 12; - } AC_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ - - struct - { - __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. - * NOTE: Some low-order bits are fixed to 0. */ - } S_b; - }; - - union - { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ - - struct - { - __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination. NOTE: Some low-order - * bits are fixed to 1. */ - } E_b; - }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } EN_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } ENPT_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_SEC_b; - }; - __IM uint16_t RESERVED3; - __IM uint32_t RESERVED4[60]; - __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ - __IM uint32_t RESERVED5[32]; -} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ - union - { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ - - struct - { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; - }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; - - union - { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union - { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union - { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; - - union - { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; - }; - __IM uint8_t RESERVED3[3]; - - union - { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; - - union - { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; - }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; - }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; - }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ - union - { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ - - struct - { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; - }; - - union - { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ - - struct - { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; - }; - - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; - - union - { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct - { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; - - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ - - struct - { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; - - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ - - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; - - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; - }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ - - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct - { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - - struct - { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ - - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct - { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ - - struct - { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED23[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ - - struct - { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; - }; - - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; - - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ - - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ - __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ - uint32_t : 2; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ - uint32_t : 27; - } MSSAR_b; - }; - - union - { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - - union - { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ - - struct - { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; - }; - - union - { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; - }; - - union - { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ - - struct - { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; - }; - - union - { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ - - struct - { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; - }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ - - union - { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - - union - { - __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ - }; - __IM uint32_t RESERVED4[58]; - - union - { - union - { - __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ - uint32_t : 31; - } BUSMABT_b; - }; - __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - }; - __IM uint32_t RESERVED5[46]; - - union - { - __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ - __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ - }; - __IM uint32_t RESERVED6[33]; - - union - { - __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ - - struct - { - __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ - uint32_t : 2; - __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ - uint32_t : 12; - __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ - uint32_t : 15; - } BUSDIVBYP_b; - }; - __IM uint32_t RESERVED7[63]; - - union - { - __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ - - struct - { - __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ - uint16_t : 15; - } BUSTHRPUT_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[255]; - __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED10[16]; - - union - { - __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address - * and Read/Write Status registers. */ - }; - __IM uint32_t RESERVED11[28]; - - union - { - __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ - __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ - }; - __IM uint32_t RESERVED12[16]; - __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED13[5]; - __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ -} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ - union - { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; - }; - - union - { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct - { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; - }; - - union - { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - - struct - { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; - - union - { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - - struct - { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; - }; - - union - { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ - - struct - { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - - union - { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; - }; - - union - { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ - - struct - { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; - }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; - }; - - union - { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - - struct - { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; - }; - - union - { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ - - struct - { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; - }; - - union - { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ - - struct - { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; - }; - - union - { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ - - struct - { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; - }; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - - struct - { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; - }; - - union - { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ - - struct - { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; - }; - - union - { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - - struct - { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; - }; - - union - { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; - }; - - union - { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; - }; - __IM uint32_t RESERVED3[18]; - - union - { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ - - struct - { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; - }; - __IM uint32_t RESERVED4[18]; - - union - { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ - - struct - { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; - }; - __IM uint32_t RESERVED5[18]; - - union - { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; - }; - __IM uint32_t RESERVED6[18]; - - union - { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct - { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; - }; - - union - { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; - }; - - union - { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ - - struct - { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; - }; - - union - { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; - }; - - union - { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; - }; - - union - { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ - - struct - { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; - }; - - union - { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ - - struct - { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; - }; - __IM uint32_t RESERVED7[2]; - - union - { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ - - struct - { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; - }; - __IM uint32_t RESERVED8[288]; - - union - { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ - - struct - { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; - }; - __IM uint32_t RESERVED9[288]; - - union - { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ - - struct - { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; - }; - __IM uint32_t RESERVED10[36]; - - union - { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ - - struct - { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; - }; - __IM uint32_t RESERVED11[36]; - - union - { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ - - struct - { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; - }; - __IM uint32_t RESERVED12[36]; - - union - { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ - - struct - { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; - }; - __IM uint32_t RESERVED13[36]; - - union - { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ - - struct - { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; - }; - __IM uint32_t RESERVED14[40]; - - union - { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; - }; - __IM uint32_t RESERVED15[6]; - - union - { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; - }; - __IM uint32_t RESERVED16[6]; - - union - { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; - }; - __IM uint32_t RESERVED17[6]; - - union - { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; - }; - __IM uint32_t RESERVED18[6]; - - union - { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; - }; - __IM uint32_t RESERVED19[6]; - - union - { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; - }; - __IM uint32_t RESERVED20[6]; - - union - { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; - }; - __IM uint32_t RESERVED21[6]; - - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; - - union - { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; - }; - __IM uint32_t RESERVED23[6]; - - union - { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; - }; - __IM uint32_t RESERVED24[6]; - - union - { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; - }; - __IM uint32_t RESERVED25[6]; - - union - { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; - }; - __IM uint32_t RESERVED26[6]; - - union - { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - - struct - { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; - }; - - union - { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ - - struct - { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; - }; - __IM uint32_t RESERVED27; - - union - { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; - }; - - union - { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ - - struct - { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; - }; - __IM uint32_t RESERVED28[24]; - - union - { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ - - struct - { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; - }; - __IM uint32_t RESERVED29[6]; - - union - { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ - - struct - { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; - }; - __IM uint32_t RESERVED30[6]; - - union - { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ - - struct - { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; - }; - __IM uint32_t RESERVED31[46]; - - union - { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ - - struct - { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; - }; - __IM uint32_t RESERVED32; - - union - { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ - - struct - { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; - }; - - union - { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ - - struct - { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; - }; - __IM uint32_t RESERVED33; - - union - { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ - - struct - { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; - }; - __IM uint32_t RESERVED34; - - union - { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ - - struct - { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; - }; - - union - { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ - - struct - { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ - - struct - { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ - - struct - { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; - - union - { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ - - struct - { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; - }; - - union - { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ - - struct - { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; - }; - __IM uint32_t RESERVED36[2]; - - union - { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ - - struct - { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; - }; - - union - { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ - - struct - { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; - }; - __IM uint32_t RESERVED37[2]; - - union - { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; - }; - __IM uint32_t RESERVED38[10]; - - union - { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ - - struct - { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; - }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; - - union - { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ - - struct - { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; - }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ - -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; - - union - { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - - struct - { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; - }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ - -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ - union - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - - struct - { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; - }; - - union - { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - - struct - { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; - }; - - union - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ - - struct - { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; - }; - - union - { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct - { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; - - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ - - struct - { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; - }; - - union - { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ - - struct - { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; - }; - - union - { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; - }; - - union - { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; - }; - - union - { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ - - struct - { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; - }; - - union - { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ - - struct - { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; - }; - - union - { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; - }; - - union - { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ - - struct - { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; - }; - - union - { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ - - struct - { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; - }; - - union - { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ - - struct - { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; - }; - - union - { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ - - struct - { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; - }; - - union - { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ - - struct - { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; - }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ - -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ - union - { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ - - struct - { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; - }; - - union - { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; - }; - - union - { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; - }; - - union - { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; - }; - - union - { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ - - struct - { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; - }; - - union - { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; - }; - - union - { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ - - struct - { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; - }; - __IM uint16_t RESERVED[9]; - - union - { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; - - union - { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ - - struct - { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ - union - { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct - { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct - { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 12; - __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ - __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; - __IM uint32_t RESERVED1[123]; - - union - { - __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ - - struct - { - __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ - __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ - uint32_t : 6; - __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ - uint32_t : 21; - } FSBLSTAT_b; - }; -} R_DEBUG_Type; /*!< Size = 516 (0x204) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ - -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ - union - { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ - - struct - { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ - - struct - { - __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ - uint8_t : 3; - __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ - uint8_t : 3; - } DMCTL_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[11]; - - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ - - struct - { - __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ - uint32_t : 4; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; - }; - __IM uint32_t RESERVED6[15]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ - union - { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ - - struct - { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; - }; - - union - { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ - - struct - { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; - }; - - union - { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; - }; - - union - { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; - }; - - union - { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ - - struct - { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ - - struct - { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; - }; - - union - { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ - - struct - { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-28 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-28 Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-28 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-28 Mode */ - } DMAMD_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ - - struct - { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-28 mode for transfer source or destination. */ - } DMOFR_b; - }; - - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ - - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - - union - { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ - - struct - { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; - }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ - - union - { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct - { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; - - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ - - struct - { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; - }; - - union - { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct - { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ - -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ - - struct - { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ - - struct - { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; - }; - - union - { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ - - struct - { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; - }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ - -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ - union - { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_b; - }; - - union - { - __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ - - struct - { - __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ - uint8_t : 7; - } DTCADMOD_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ - - struct - { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ - - struct - { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; - }; - - union - { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_SEC_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - - union - { - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_SEC_b; - }; - - union - { - __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ - - struct - { - __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ - } DTCDISP_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ - - struct - { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; - }; - - union - { - __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ - } DTCIBR_b; - }; - - union - { - __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ - - struct - { - __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ - uint8_t : 7; - } DTCOR_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ - - struct - { - __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ - uint16_t : 7; - __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ - } DTCSQE_b; - }; - __IM uint16_t RESERVED10; -} R_DTC_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ - union - { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; - }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; - - union - { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ - - struct - { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ - - struct - { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ - -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ -{ - union - { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ - - struct - { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ - - struct - { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ - - struct - { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ - - struct - { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ - - struct - { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ - - struct - { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; - }; - __IM uint32_t RESERVED5[5]; - - union - { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ - - struct - { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ - - struct - { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; - }; - - union - { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ - - struct - { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; - }; - - union - { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ - - struct - { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ - - struct - { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; - }; - - union - { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ - - struct - { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; - }; - __IM uint32_t RESERVED8[20]; - - union - { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ - - struct - { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ - - struct - { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ - - struct - { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ - - union - { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ - - struct - { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; - }; - - union - { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ - - struct - { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ - - struct - { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; - }; - - union - { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ - - struct - { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union - { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; - }; - - union - { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; - }; - - union - { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ - - struct - { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; - }; - - union - { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ - - struct - { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; - }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ - -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ -{ - union - { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ - - struct - { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ - - struct - { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ - - struct - { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ - - struct - { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ - - struct - { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ - - struct - { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ - - struct - { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; - }; - __IM uint32_t RESERVED11[2]; - - union - { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ - - struct - { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; - }; - - union - { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ - - struct - { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; - }; - - union - { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ - - struct - { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; - }; - - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ - - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ - - struct - { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; - }; - - union - { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ - - struct - { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; - }; - __IM uint32_t RESERVED13[18]; - - union - { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ - - struct - { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; - }; - - union - { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; - }; - __IM uint32_t RESERVED14; - - union - { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ - - struct - { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; - }; - - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ - union - { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ - -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ - - struct - { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; - - union - { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ - - struct - { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; - }; - - union - { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ - - struct - { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union - { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ - - struct - { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ - - struct - { - __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ - uint8_t : 5; - } FCNTSELR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR0_b; - }; - - union - { - __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR1_b; - }; - __IM uint32_t RESERVED12[9]; - - union - { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ - - struct - { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; - }; - __IM uint16_t RESERVED13; - - union - { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ - - struct - { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; - }; - __IM uint16_t RESERVED14; - - union - { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ - - struct - { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; - }; - - union - { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ - - struct - { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; - }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16; - - union - { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ - - struct - { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; - }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[4]; - - union - { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ - - struct - { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; - }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[11]; - - union - { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ - - struct - { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; - - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ - - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; - - union - { - union - { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ - - struct - { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; - }; - - union - { - __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ - - struct - { - __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address - * or the last blank checked address which is found in 'Blank - * Check' command execution. */ - uint32_t : 8; - } FBCADDR_b; - }; - }; - - union - { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ - - struct - { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; - }; - - union - { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ - - struct - { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ - - struct - { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ - - struct - { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; - }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; - - union - { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ - - struct - { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-28 Register */ - - struct - { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-28 Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; - - union - { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ - - struct - { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; - - union - { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ - - struct - { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ - uint16_t : 6; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ - __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ - uint16_t : 4; - __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ - } FSAR_b; - }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief General PWM Timer (R_GPT0) - */ - -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ - union - { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ - - struct - { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; - }; - - union - { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ - - struct - { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; - }; - - union - { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ - - struct - { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; - }; - - union - { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ - - struct - { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; - }; - - union - { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ - - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; - }; - - union - { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ - - struct - { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; - }; - - union - { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ - - struct - { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; - - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ - - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; - - union - { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ - - struct - { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ - uint32_t : 7; - } GTICASR_b; - }; - - union - { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ - - struct - { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ - uint32_t : 7; - } GTICBSR_b; - }; - - union - { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ - - struct - { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 3; - __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ - __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ - uint32_t : 2; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; - }; - - union - { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ - - struct - { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection - * timing setting */ - uint32_t : 3; - } GTUDDTYC_b; - }; - - union - { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ - - struct - { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-28.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-28.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; - }; - - union - { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ - - struct - { - __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; - }; - - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ - - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; - }; - - union - { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ - - struct - { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; - }; - - union - { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ - - struct - { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; - }; - - union - { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ - - struct - { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; - }; - - union - { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ - - struct - { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; - }; - - union - { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ - - struct - { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; - }; - - union - { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ - - struct - { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; - - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; - - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; - - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ - - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; - - union - { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; - }; - - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ - - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; - - union - { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; - }; - - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ - - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; - }; - - union - { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ - - struct - { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; - }; - - union - { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ - - struct - { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; - }; - - union - { - __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Control Register */ - - struct - { - __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter - * 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 - * Skipping Count Setting */ - __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping - * Counter 1 Initial Value */ - __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping - * Counter 1 */ - __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping - * 2 Skipping Count Setting */ - __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Initial Value */ - __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping - * Counter 2 */ - } GTADCMSC_b; - }; - - union - { - __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Setting Register */ - - struct - { - __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 9; - __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 9; - } GTADCMSS_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ - - struct - { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; - }; - - union - { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ - - struct - { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; - }; - __IM uint32_t RESERVED1[2]; - - union - { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ - - struct - { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; - }; - - union - { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ - - struct - { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; - }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ - -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ - union - { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ - - struct - { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; - }; - __IM uint32_t RESERVED[15]; - - union - { - __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection - * Register */ - - struct - { - __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ - uint16_t : 7; - __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ - } GTONCWP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling - * Register */ - - struct - { - __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ - uint16_t : 3; - __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ - __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ - uint16_t : 7; - } GTONCCR_b; - }; - __IM uint16_t RESERVED2; -} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ - -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ - union - { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ - - struct - { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 1; - __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; - }; - __IM uint32_t RESERVED[60]; - - union - { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - - struct - { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - - union - { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ - - struct - { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; - }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; - - union - { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ - - struct - { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; - }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; - - union - { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ - - struct - { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; - - union - { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - - struct - { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - - union - { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ - - struct - { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; - }; - - union - { - __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ - - struct - { - __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze - * Mode */ - uint32_t : 27; - } WUPEN2_b; - }; - __IM uint32_t RESERVED10[5]; - - union - { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ - - struct - { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; - }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; - __IM uint32_t RESERVED16[24]; - - union - { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ - - struct - { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; - }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ - union - { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ - - struct - { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; - }; - - union - { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ - - struct - { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; - }; - - union - { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ - - struct - { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; - }; - - union - { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ - - struct - { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; - }; - - union - { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ - - struct - { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; - }; - - union - { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ - - struct - { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; - }; - - union - { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ - - struct - { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; - }; - - union - { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ - - struct - { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; - }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ - - union - { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ - - struct - { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; - }; - - union - { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ - - struct - { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; - }; - - union - { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ - - struct - { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; - }; - - union - { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ - - struct - { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ - - struct - { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; - }; - - union - { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ - - struct - { - __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; - }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; - }; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; - - union - { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ - -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ - union - { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ - - struct - { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ - - struct - { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; - }; - - union - { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ - - struct - { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; - }; - - union - { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ - - struct - { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ - - struct - { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 2; - __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ - __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ - __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ - __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ - uint32_t : 3; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; - }; - - union - { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; - }; - - union - { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; - }; - - union - { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; - }; - - union - { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ - - struct - { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ - - struct - { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; - }; - __IM uint32_t RESERVED4[4]; - - union - { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ - - struct - { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ - - struct - { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; - }; - - union - { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ - - struct - { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ - uint32_t : 13; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; - }; - - union - { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ - - struct - { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; - }; - - union - { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ - - struct - { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; - }; - - union - { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ - - struct - { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; - }; - - union - { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ - - struct - { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; - }; - - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ - - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; - - union - { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ - - struct - { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; - }; - - union - { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ - - struct - { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; - }; - - union - { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ - - struct - { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ - - struct - { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ - - struct - { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; - }; - - union - { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ - - struct - { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; - }; - __IM uint32_t RESERVED9[2]; - - union - { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ - - struct - { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; - }; - __IM uint32_t RESERVED10[3]; - - union - { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ - - struct - { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; - }; - __IM uint32_t RESERVED11[23]; - - union - { - __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ - - struct - { - __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ - uint32_t : 31; - } STCTL_b; - }; - - union - { - __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ - - struct - { - __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ - __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ - __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ - uint32_t : 5; - __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ - uint32_t : 16; - } ATCTL_b; - }; - - union - { - __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ - - struct - { - __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ - uint32_t : 31; - } ATTRG_b; - }; - - union - { - __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ - - struct - { - __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, - * SC2. */ - uint32_t : 31; - } ATCCNTE_b; - }; - __IM uint32_t RESERVED12[4]; - - union - { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ - - struct - { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; - }; - __IM uint32_t RESERVED13[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED14[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - - union - { - __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ - - struct - { - __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ - } HCMDQP_b; - }; - - union - { - __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ - - struct - { - __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ - } HRSPQP_b; - }; - - union - { - __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ - - struct - { - __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ - } HTDTBP_b; - }; - - union - { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; - }; - - union - { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; - }; - __IM uint32_t RESERVED15[10]; - - union - { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ - - struct - { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; - }; - - union - { - __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ - uint32_t : 16; - } HQTHCTL_b; - }; - - union - { - __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold - * Control Register */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ - uint32_t : 5; - } HTBTHCTL_b; - }; - __IM uint32_t RESERVED16; - - union - { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ - - struct - { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 3; - __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ - uint32_t : 7; - } BST_b; - }; - - union - { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ - - struct - { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ - uint32_t : 7; - } BSTE_b; - }; - - union - { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ - - struct - { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ - uint32_t : 7; - } BIE_b; - }; - - union - { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ - - struct - { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 3; - __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ - uint32_t : 7; - } BSTFC_b; - }; - - union - { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; - }; - - union - { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; - }; - - union - { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; - }; - - union - { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; - }; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ - __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ - uint32_t : 1; - __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ - uint32_t : 22; - } HTST_b; - }; - - union - { - __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ - __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ - uint32_t : 22; - } HTSTE_b; - }; - - union - { - __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ - __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ - uint32_t : 22; - } HTIE_b; - }; - - union - { - __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ - __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ - uint32_t : 1; - __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ - uint32_t : 22; - } HTSTFC_b; - }; - - union - { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ - - struct - { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; - }; - - union - { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - - struct - { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ - uint32_t : 13; - } SVST_b; - }; - - union - { - __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ - - struct - { - __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; - }; - - union - { - __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ - - struct - { - __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ - } MRCCPT_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; - }; - __IM uint32_t RESERVED19; - - union - { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; - }; - __IM uint32_t RESERVED20; - - union - { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; - }; - __IM uint32_t RESERVED21; - - union - { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; - }; - __IM uint32_t RESERVED22; - - union - { - __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS4_b; - }; - __IM uint32_t RESERVED23; - - union - { - __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS5_b; - }; - __IM uint32_t RESERVED24; - - union - { - __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS6_b; - }; - __IM uint32_t RESERVED25; - - union - { - __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS7_b; - }; - __IM uint32_t RESERVED26[16]; - - union - { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - - struct - { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; - }; - __IM uint32_t RESERVED27[3]; - - union - { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; - }; - - union - { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; - }; - - union - { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; - }; - __IM uint32_t RESERVED28[5]; - - union - { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; - }; - - union - { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; - }; - - union - { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; - }; - - union - { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; - }; - - union - { - __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT4_b; - }; - - union - { - __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT5_b; - }; - - union - { - __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT6_b; - }; - - union - { - __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT7_b; - }; - __IM uint32_t RESERVED29[12]; - - union - { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - - struct - { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; - }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED30; - - union - { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; - }; - - union - { - __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD1_b; - }; - - union - { - __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD2_b; - }; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ - - struct - { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; - }; - - union - { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - - struct - { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; - }; - - union - { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ - - struct - { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; - }; - - union - { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ - - struct - { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; - }; - - union - { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - - struct - { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; - }; - - union - { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ - - struct - { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; - }; - - union - { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ - - struct - { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; - }; - - union - { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ - - struct - { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; - }; - - union - { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ - - struct - { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; - }; - - union - { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ - - struct - { - __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ - __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ - __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ - uint32_t : 5; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; - }; - - union - { - __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) - * Register */ - - struct - { - __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ - __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ - uint32_t : 4; - __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ - uint32_t : 24; - } CETSS_b; - }; - - union - { - __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ - - struct - { - __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ - __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ - __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ - uint32_t : 29; - } CGHDRCAP_b; - }; - - union - { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ - - struct - { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; - }; - __IM uint32_t RESERVED32[4]; - - union - { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; - }; - - union - { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; - }; - __IM uint32_t RESERVED33[9]; - - union - { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ - - struct - { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; - }; - - union - { - __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ - uint32_t : 16; - } HQSTLV_b; - }; - - union - { - __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ - uint32_t : 16; - } HDBSTLV_b; - }; - - union - { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - - struct - { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; - }; - - union - { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ - - struct - { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; - __IM uint32_t RESERVED34[3]; - - union - { - __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ - - struct - { - __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ - uint32_t : 16; - } SC1CPT_b; - }; - - union - { - __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ - - struct - { - __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ - uint32_t : 16; - } SC2CPT_b; - }; -} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OADPT_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[62]; - __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ - - struct - { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; - }; - - union - { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ - - struct - { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; - }; - - union - { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ - - struct - { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; - }; - - union - { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; - }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ - -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ - union - { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; - - struct - { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; - }; - - union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; - }; - - union - { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; - - struct - { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; - - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ - - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; - }; - - union - { - union - { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ - - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; - - struct - { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; - - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; - }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ - -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-MISC (R_PMISC) - */ - -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ - union - { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; - }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ - union - { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct - { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; - - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - - struct - { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; - - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; - - union - { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct - { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - - struct - { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; - - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ - - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; - }; - - union - { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct - { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct - { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ - __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using - * time error adjustment function inlow-consumption clock - * mode. */ - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; - }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; - - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; - - union - { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; - - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; - }; - __IM uint8_t RESERVED9; - - union - { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; - - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; - }; - __IM uint8_t RESERVED10; - - union - { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; - - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; - }; - __IM uint8_t RESERVED11; - - union - { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; - - union - { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; - }; - __IM uint8_t RESERVED12; - - union - { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; - - union - { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; - }; - - union - { - union - { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; - - union - { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ - - struct - { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; - }; - - union - { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - - struct - { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; - }; - - union - { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ - - struct - { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; - }; - __IM uint8_t RESERVED19; - - union - { - __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ - - struct - { - uint16_t : 5; - __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ - } RADJ2_b; - }; - __IM uint16_t RESERVED20[7]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ - -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ - union - { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; - - union - { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; - - union - { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; - - union - { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct - { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; - - union - { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF - * = 0, and MMR.MANEN = 1) */ - - struct - { - __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_MANC_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - union - { - __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ - __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ - uint16_t : 2; - __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ - uint16_t : 3; - } TDRHL_MAN_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - union - { - __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ - uint16_t : 2; - __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ - uint16_t : 3; - } RDRHL_MAN_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ - - struct - { - __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ - __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ - __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ - uint8_t : 1; - __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ - __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ - __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ - __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ - } MMR_b; - }; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; - }; - - union - { - __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ - __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ - uint8_t : 2; - } TMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ - - struct - { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; - }; - - union - { - __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ - __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ - uint8_t : 2; - } RMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ - - struct - { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; - }; - - union - { - __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ - - struct - { - __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ - __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ - uint8_t : 5; - } MESR_b; - }; - }; - - union - { - union - { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ - - struct - { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; - }; - - union - { - __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ - - struct - { - __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ - __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ - uint8_t : 5; - } MECR_b; - }; - }; - - union - { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ - - struct - { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; - }; - - union - { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ - - struct - { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; - - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct - { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ - - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ - - struct - { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ - - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ - - struct - { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ - - struct - { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; - - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct - { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ - __IM uint16_t RESERVED1[4]; - - union - { - __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ - - struct - { - __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ - uint8_t : 7; - } SCIMSKEN_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_SCI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ - -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ - union - { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ - - struct - { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ - - struct - { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; - }; - - union - { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - - struct - { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; - }; - - union - { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - - struct - { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; - }; - - union - { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - - struct - { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; - }; - - union - { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - - struct - { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; - }; - - union - { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - - struct - { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; - }; - - union - { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ - - struct - { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; - }; - - union - { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - - struct - { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; - }; - - union - { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ - - struct - { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; - }; - - union - { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - - struct - { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; - }; - - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ - - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; - - union - { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - - struct - { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; - }; - - union - { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; - }; - - union - { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ - - struct - { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; - }; - - union - { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; - }; - - union - { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct - { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; - }; - - union - { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct - { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; - }; - - union - { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ - - struct - { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; - }; - - union - { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - - struct - { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ - - struct - { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; - }; - - union - { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - - struct - { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; - }; - - union - { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ - - struct - { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - - struct - { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; - }; - __IM uint32_t RESERVED3[79]; - - union - { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ - - struct - { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; - }; - __IM uint32_t RESERVED4[3]; - - union - { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ - - struct - { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; - }; - __IM uint32_t RESERVED6[4]; - - union - { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ - - struct - { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; - }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ - - struct - { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; - }; - - union - { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - - struct - { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; - }; - - union - { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ - - struct - { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; - }; - - union - { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - - struct - { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ - }; - - union - { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ - - struct - { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; - }; - - union - { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - - struct - { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; - }; - - union - { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ - - struct - { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; - }; - - union - { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ - - struct - { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; - }; - - union - { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ - - struct - { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; - }; - - union - { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ - - struct - { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; - }; - - union - { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ - - struct - { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; - }; - - union - { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ - - struct - { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; - }; - - union - { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ - - struct - { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; - }; - - union - { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ - - struct - { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; - }; - - union - { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ - - struct - { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; - }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ - -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ - union - { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ - - struct - { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; - }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; - - union - { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ - - struct - { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; - }; - __IM uint8_t RESERVED3[179]; - - union - { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ - - struct - { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; - }; - - union - { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; - }; - - union - { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-28 Enable Register */ - - struct - { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-28 Enable */ - uint8_t : 7; - } ECC1STSEN_b; - }; - - union - { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; - }; - - union - { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; - }; - __IM uint8_t RESERVED4[11]; - - union - { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; - }; - __IM uint8_t RESERVED5[3]; - - union - { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ - - struct - { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; - }; - __IM uint8_t RESERVED6[3]; - - union - { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; - }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ -{ - union - { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ - - struct - { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; - }; - - union - { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ - - struct - { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ - - struct - { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 3; - __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ - uint32_t : 4; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; - }; - - union - { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ - - struct - { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; - }; - - union - { - union - { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - - struct - { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; - }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - - union - { - union - { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - - struct - { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; - }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - }; - - union - { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ - - struct - { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; - }; - - union - { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ - - struct - { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; - }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System Pins (R_SYSTEM) - */ - -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ - - struct - { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; - }; - - union - { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; - }; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ - - struct - { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ - - struct - { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; - }; - - union - { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ - - struct - { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; - }; - - union - { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ - - struct - { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ - - struct - { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; - }; - - union - { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ - - struct - { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; - }; - - union - { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; - }; - - union - { - __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register - * 2 */ - - struct - { - __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ - uint8_t : 1; - __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ - uint8_t : 2; - } HOCOCR2_b; - }; - - union - { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; - }; - - union - { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ - - struct - { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; - }; - - union - { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ - - struct - { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; - }; - - union - { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ - - struct - { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ - uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ - uint8_t : 1; - } OSCSF_b; - }; - __IM uint8_t RESERVED8; - - union - { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ - - struct - { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; - }; - - union - { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ - - struct - { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; - }; - - union - { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ - - struct - { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; - }; - - union - { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ - - struct - { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; - }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; - - union - { - __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ - - struct - { - __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ - uint16_t : 2; - } PLL2CCR_b; - }; - - union - { - __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ - - struct - { - __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ - uint8_t : 7; - } PLL2CR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ - - struct - { - __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock - * (valid only when LPOPTEN = 1) */ - __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ - __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W - * clock (valid only when LPOPT.LPOPTEN = 1) */ - uint8_t : 3; - __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ - } LPOPT_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ - - struct - { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ - - struct - { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; - }; - - union - { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ - - struct - { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; - }; - __IM uint32_t RESERVED15[3]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO - * trimming bits */ - } MOCOUTCR_b; - }; - - union - { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; - }; - __IM uint8_t RESERVED17; - __IM uint32_t RESERVED18[2]; - - union - { - __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ - - struct - { - __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ - uint8_t : 5; - } USBCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ - uint8_t : 5; - } OCTACKDIVCR_b; - }; - - union - { - __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ - uint8_t : 5; - } SCISPICKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ - - struct - { - __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ - uint8_t : 5; - } CANFDCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - - struct - { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; - }; - - union - { - __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ - - struct - { - __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ - uint8_t : 5; - } USB60CKDIVCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - - struct - { - __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ - uint8_t : 5; - } CECCKDIVCR_b; - }; - - union - { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ - - struct - { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ - - struct - { - __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ - uint8_t : 5; - } I3CCKDIVCR_b; - }; - __IM uint16_t RESERVED19; - - union - { - __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ - __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ - } USBCKCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ - - struct - { - __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ - uint8_t : 3; - __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ - __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ - } OCTACKCR_b; - }; - - union - { - __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ - - struct - { - __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ - uint8_t : 3; - __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ - __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ - } SCISPICKCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ - - struct - { - __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ - __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ - } CANFDCKCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - - struct - { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; - }; - - union - { - __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ - - struct - { - __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ - uint8_t : 2; - __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ - __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ - } USB60CKCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ - - struct - { - __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ - __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ - } CECCKCR_b; - }; - - union - { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ - - struct - { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ - - struct - { - __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ - uint8_t : 3; - __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ - __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ - } I3CCKCR_b; - }; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ - uint32_t : 29; - } SNZREQCR1_b; - }; - __IM uint32_t RESERVED22; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ - - struct - { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; - }; - __IM uint8_t RESERVED24; - - union - { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ - - struct - { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; - }; - - union - { - __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ - - struct - { - __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ - uint8_t : 7; - } SNZEDCR1_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ - - struct - { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; - }; - - union - { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ - - struct - { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; - }; - - union - { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ - - struct - { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; - }; - __IM uint8_t RESERVED27; - - union - { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ - - struct - { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; - }; - __IM uint8_t RESERVED28[2]; - - union - { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ - - struct - { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; - }; - __IM uint16_t RESERVED29[2]; - - union - { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ - - struct - { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; - }; - __IM uint8_t RESERVED30; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ - - struct - { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ - uint16_t : 1; - __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ - } RSTSR1_b; - }; - __IM uint16_t RESERVED32; - __IM uint32_t RESERVED33[3]; - - union - { - __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_ALT_b; - }; - - union - { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ - - struct - { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; - }; - __IM uint16_t RESERVED34; - __IM uint32_t RESERVED35[3]; - - union - { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; - }; - - union - { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; - }; - - union - { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; - }; - - union - { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; - }; - __IM uint32_t RESERVED36[183]; - - union - { - __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute - * Register */ - - struct - { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ - __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ - __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ - __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ - __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ - __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ - __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ - __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ - __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ - __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ - __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ - __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ - } CGFSAR_b; - }; - __IM uint32_t RESERVED37; - - union - { - __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - uint32_t : 1; - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 1; - __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - uint32_t : 3; - __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - uint32_t : 22; - } LPMSAR_b; - }; - - union - { - union - { - __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - uint32_t : 30; - } LVDSAR_b; - }; - - union - { - __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 29; - } RSTSAR_b; - }; - }; - - union - { - __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 13; - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - uint32_t : 8; - } BBFSAR_b; - }; - __IM uint32_t RESERVED38[3]; - - union - { - __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution - * Register */ - - struct - { - __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit - * 0 */ - __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit - * 1 */ - __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit - * 2 */ - __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit - * 3 */ - __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit - * 4 */ - __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit - * 5 */ - __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit - * 6 */ - __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit - * 7 */ - __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit - * 8 */ - __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit - * 9 */ - __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit - * 10 */ - __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit - * 11 */ - __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit - * 12 */ - __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit - * 13 */ - __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit - * 14 */ - __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit - * 15 */ - __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit - * 16 */ - __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit - * 17 */ - __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit - * 18 */ - __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit - * 19 */ - __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit - * 20 */ - uint32_t : 3; - __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit - * 24 */ - uint32_t : 1; - __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit - * 26 */ - __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit - * 27 */ - uint32_t : 4; - } DPFSAR_b; - }; - __IM uint32_t RESERVED39[6]; - __IM uint16_t RESERVED40; - - union - { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ - - struct - { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ - uint16_t : 3; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; - }; - - union - { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ - - struct - { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; - }; - - union - { - __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ - - struct - { - __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ - uint8_t : 2; - } DPSWCR_b; - }; - - union - { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ - - struct - { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; - }; - - union - { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ - - struct - { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; - }; - - union - { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ - - struct - { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; - }; - - union - { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 4; - } DPSIER3_b; - }; - - union - { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ - - struct - { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; - }; - - union - { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ - - struct - { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; - }; - - union - { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ - - struct - { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; - }; - - union - { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ - uint8_t : 4; - } DPSIFR3_b; - }; - - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; - }; - - union - { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; - }; - - union - { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ - - struct - { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; - }; - __IM uint8_t RESERVED41; - - union - { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ - - struct - { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; - }; - - union - { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ - - struct - { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; - }; - - union - { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ - - struct - { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; - }; - - union - { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ - - struct - { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; - }; - __IM uint8_t RESERVED42; - - union - { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; - }; - __IM uint16_t RESERVED43; - - union - { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ - - struct - { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; - }; - - union - { - union - { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; - }; - - union - { - __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 2; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ - } LVD1CMPCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - - struct - { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; - }; - - union - { - __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 4; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ - } LVD2CMPCR_b; - }; - }; - __IM uint8_t RESERVED44; - - union - { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; - }; - - union - { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; - }; - __IM uint8_t RESERVED45; - - union - { - __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select - * Register */ - - struct - { - __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ - uint8_t : 7; - } VBATTMNSELR_b; - }; - - union - { - __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ - - struct - { - __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ - uint8_t : 7; - } VBATTMONR_b; - }; - - union - { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ - - struct - { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; - }; - __IM uint32_t RESERVED46[8]; - - union - { - union - { - __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ - - struct - { - __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ - __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ - uint8_t : 2; - __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ - __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ - __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ - __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ - } DCDCCTL_b; - }; - - union - { - __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ - - struct - { - __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ - __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ - uint8_t : 6; - } LDOSCR_b; - }; - }; - - union - { - __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ - - struct - { - __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ - uint8_t : 6; - } VCCSEL_b; - }; - __IM uint16_t RESERVED47; - - union - { - __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ - - struct - { - __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ - uint8_t : 7; - } PL2LDOSCR_b; - }; - __IM uint8_t RESERVED48; - __IM uint16_t RESERVED49; - __IM uint32_t RESERVED50[14]; - - union - { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; - }; - - union - { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ - - struct - { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; - }; - - union - { - __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ - - struct - { - __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ - uint8_t : 6; - } SOMRG_b; - }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[3]; - - union - { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; - }; - __IM uint8_t RESERVED53; - - union - { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; - }; - __IM uint8_t RESERVED54; - __IM uint32_t RESERVED55[7]; - - union - { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; - }; - - union - { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ - - struct - { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; - }; - - union - { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ - - struct - { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; - }; - __IM uint8_t RESERVED56; - - union - { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ - - struct - { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; - }; - __IM uint8_t RESERVED57; - - union - { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ - - struct - { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; - }; - __IM uint8_t RESERVED58; - - union - { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; - }; - - union - { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ - - struct - { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; - }; - - union - { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ - - struct - { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; - }; - - union - { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ - - struct - { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; - }; - - union - { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ - - struct - { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; - }; - - union - { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ - - struct - { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; - }; - - union - { - __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ - uint8_t : 4; - } VBTBER_b; - }; - __IM uint8_t RESERVED59; - __IM uint16_t RESERVED60; - __IM uint32_t RESERVED61[15]; - - union - { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ - - struct - { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; - }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ - -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ - union - { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ - - struct - { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; - }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ - -typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ -{ - union - { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; - }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ - -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } DVCHGR_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ - uint16_t : 4; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - - union - { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - - struct - { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; - - union - { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ - - struct - { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ - - struct - { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; - - union - { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ - - struct - { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct - { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED23[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED25[5]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - __IM uint32_t RESERVED26[165]; - - union - { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ - - struct - { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union - { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ - - struct - { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ - -typedef struct /*!< (@ 0x40083400) R_WDT Structure */ -{ - union - { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ - - struct - { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; - }; - - union - { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; - }; - - union - { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/** - * @brief TrustZone Filter (R_TZF) - */ - -typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ -{ - union - { - __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFPT_b; - }; -} R_TZF_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief R_CACHE (R_CACHE) - */ - -typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ -{ - union - { - __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ - - struct - { - __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ - uint32_t : 31; - } CCACTL_b; - }; - - union - { - __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ - uint32_t : 31; - } CCAFCT_b; - }; - - union - { - __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ - uint32_t : 30; - } CCALCF_b; - }; - __IM uint32_t RESERVED[13]; - - union - { - __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ - - struct - { - __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ - uint32_t : 31; - } SCACTL_b; - }; - - union - { - __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ - uint32_t : 31; - } SCAFCT_b; - }; - - union - { - __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ - uint32_t : 30; - } SCALCF_b; - }; - __IM uint32_t RESERVED1[109]; - - union - { - __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection - * Register */ - - struct - { - __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint32_t : 31; - } CAPOAD_b; - }; - - union - { - __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ - - struct - { - __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ - __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ - uint32_t : 24; - } CAPRCR_b; - }; -} R_CACHE_Type; /*!< Size = 520 (0x208) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU System Security Control Unit (R_CPSCU) - */ - -typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ -{ - union - { - __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ - - struct - { - __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ - __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ - __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ - uint32_t : 29; - } CSAR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ - - struct - { - __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ - __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection - * 2 */ - __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ - uint32_t : 29; - } SRAMSAR_b; - }; - - union - { - __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ - - struct - { - __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ - uint32_t : 28; - } STBRAMSAR_b; - }; - __IM uint32_t RESERVED1[6]; - - union - { - __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ - uint32_t : 31; - } DTCSAR_b; - }; - - union - { - __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ - uint32_t : 31; - } DMACSAR_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ - - struct - { - __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ - uint32_t : 16; - } ICUSARA_b; - }; - - union - { - __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ - - struct - { - __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ - uint32_t : 31; - } ICUSARB_b; - }; - - union - { - __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ - - struct - { - __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ - uint32_t : 24; - } ICUSARC_b; - }; - - union - { - __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ - - struct - { - __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ - uint32_t : 31; - } ICUSARD_b; - }; - - union - { - __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ - - struct - { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 2; - __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ - } ICUSARE_b; - }; - - union - { - __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ - - struct - { - __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ - __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ - __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ - __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 3; - __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ - __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ - __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ - __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ - __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ - __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ - __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ - __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ - uint32_t : 17; - } ICUSARF_b; - }; - - union - { - __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ - - struct - { - __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ - __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ - __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ - __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ - __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ - __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ - __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ - uint32_t : 25; - } ICUSARM_b; - }; - __IM uint32_t RESERVED3[5]; - - union - { - __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ - } ICUSARG_b; - }; - - union - { - __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ - } ICUSARH_b; - }; - - union - { - __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ - } ICUSARI_b; - }; - __IM uint32_t RESERVED4[33]; - - union - { - __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ - - struct - { - __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ - uint32_t : 31; - } BUSSARA_b; - }; - - union - { - __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ - - struct - { - __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ - uint32_t : 31; - } BUSSARB_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ - - struct - { - __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ - uint32_t : 31; - } BUSSARC_b; - }; - - union - { - __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ - - struct - { - __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ - uint32_t : 31; - } BUSPARC_b; - }; - __IM uint32_t RESERVED6[6]; - - union - { - __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution - * Register A */ - - struct - { - __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ - uint32_t : 24; - } MMPUSARA_b; - }; - - union - { - __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution - * Register B */ - - struct - { - __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ - uint32_t : 31; - } MMPUSARB_b; - }; - __IM uint32_t RESERVED7[18]; - - union - { - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; - - union - { - __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ - - struct - { - __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ - uint32_t : 31; - } DEBUGSAR_b; - }; - }; - __IM uint32_t RESERVED8[7]; - - union - { - __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ - - struct - { - __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ - uint32_t : 24; - } DMACCHSAR_b; - }; - __IM uint32_t RESERVED9[3]; - - union - { - __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ - - struct - { - __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ - uint32_t : 31; - } CPUDSAR_b; - }; - __IM uint32_t RESERVED10[147]; - - union - { - __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register - * 0 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR0_b; - }; - - union - { - __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register - * 1 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR1_b; - }; - __IM uint32_t RESERVED11[126]; - - union - { - __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ - - struct - { - __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn - * and ELCSRn */ - uint32_t : 31; - } TEVTRCR_b; - }; -} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Consumer Electronics Control (R_CEC) - */ - -typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ -{ - union - { - __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ - - struct - { - __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ - __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device - * 1) */ - __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device - * 2) */ - __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ - __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ - __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ - __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ - __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ - __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ - __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device - * 3) */ - __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ - __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device - * 3) */ - __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ - __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ - __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ - uint16_t : 1; - } CADR_b; - }; - - union - { - __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ - - struct - { - __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ - __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing - * Select */ - __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ - __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ - __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ - __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ - } CECCTL1_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ - - struct - { - __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ - uint16_t : 7; - } STATB_b; - }; - - union - { - __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ - uint16_t : 7; - } STATL_b; - }; - - union - { - __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ - uint16_t : 7; - } LGC0L_b; - }; - - union - { - __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ - uint16_t : 7; - } LGC1L_b; - }; - - union - { - __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ - - struct - { - __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ - uint16_t : 7; - } DATB_b; - }; - - union - { - __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ - - struct - { - __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ - uint16_t : 7; - } NOMT_b; - }; - - union - { - __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ - uint16_t : 7; - } STATLL_b; - }; - - union - { - __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATLH_b; - }; - - union - { - __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ - uint16_t : 7; - } STATBL_b; - }; - - union - { - __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATBH_b; - }; - - union - { - __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LL_b; - }; - - union - { - __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LH_b; - }; - - union - { - __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ - uint16_t : 7; - } LGC1LL_b; - }; - - union - { - __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ - uint16_t : 7; - } LGC1LH_b; - }; - - union - { - __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ - uint16_t : 7; - } DATBL_b; - }; - - union - { - __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ - uint16_t : 7; - } DATBH_b; - }; - - union - { - __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ - - struct - { - __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ - uint16_t : 7; - } NOMP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ - __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ - uint8_t : 1; - __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ - } CECEXMD_b; - }; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ - - struct - { - __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ - __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ - uint8_t : 6; - } CECEXMON_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[10]; - __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ - __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ - - union - { - __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ - - struct - { - __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ - __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ - __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ - __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ - __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ - __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ - __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ - uint8_t : 1; - } CECES_b; - }; - - union - { - __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ - - struct - { - __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ - __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ - __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ - __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ - __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ - uint8_t : 2; - __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ - } CECS_b; - }; - - union - { - __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ - - struct - { - __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ - __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ - __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ - __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ - __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ - __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ - __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ - uint8_t : 1; - } CECFC_b; - }; - - union - { - __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ - - struct - { - __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ - __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ - __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ - __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ - __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ - __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ - } CECCTL0_b; - }; -} R_CEC_Type; /*!< Size = 70 (0x46) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Octa Serial Peripheral Interface (R_OSPI) - */ - -typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ -{ - union - { - __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ - - struct - { - __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ - __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ - uint32_t : 16; - } DCR_b; - }; - - union - { - __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ - - struct - { - __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ - __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ - __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ - __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ - } DAR_b; - }; - - union - { - __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ - - struct - { - __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ - __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ - uint32_t : 3; - __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ - __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ - __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ - __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ - __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ - __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ - __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ - uint32_t : 2; - } DCSR_b; - }; - - union - { - __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ - - struct - { - __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ - __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ - } DSR_b[2]; - }; - - union - { - __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ - - struct - { - __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ - __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ - __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ - __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ - __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ - uint32_t : 4; - } MDTR_b; - }; - - union - { - __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ - - struct - { - __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ - } ACTR_b; - }; - - union - { - __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ - - struct - { - __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ - } ACAR_b[2]; - }; - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ - __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ - __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ - __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ - __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DRCSTR_b; - }; - - union - { - __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ - __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ - __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ - __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ - __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DWCSTR_b; - }; - - union - { - __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ - __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ - __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ - uint32_t : 16; - } DCSTR_b; - }; - - union - { - __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ - - struct - { - __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ - __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ - __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ - __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ - uint32_t : 4; - __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device - * 0 */ - __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device - * 1 */ - __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ - uint32_t : 17; - __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ - } CDSR_b; - }; - - union - { - __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ - - struct - { - __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ - __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ - __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ - __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ - } MDLR_b; - }; - - union - { - __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ - - struct - { - __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ - __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ - __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ - __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ - } MRWCR_b[2]; - }; - - union - { - __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ - - struct - { - __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ - __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ - __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ - __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ - __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ - __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ - __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ - uint32_t : 1; - __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ - __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ - __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ - __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ - __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ - __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ - __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ - uint32_t : 1; - } MRWCSR_b; - }; - - union - { - __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ - - struct - { - __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ - __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ - uint32_t : 16; - } ESR_b; - }; - - union - { - __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ - - struct - { - __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ - } CWNDR_b; - }; - - union - { - __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ - - struct - { - __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ - __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ - __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ - __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ - } CWDR_b; - }; - - union - { - __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ - - struct - { - __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ - __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ - __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ - __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ - } CRR_b; - }; - - union - { - __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ - - struct - { - __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ - __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ - uint32_t : 26; - } ACSR_b; - }; - __IM uint32_t RESERVED1[5]; - - union - { - __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ - - struct - { - __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are - * Low in single continuous write of OctaRAM. */ - uint32_t : 7; - __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 - * are Low in single continuous read of OctaRAM. */ - uint32_t : 7; - } DCSMXR_b; - }; - - union - { - __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating - * size Register */ - - struct - { - __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single - * continuous write of device 0. */ - uint32_t : 5; - __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single - * continuous write of device 1. */ - uint32_t : 5; - } DWSCTSR_b; - }; -} R_OSPI_Type; /*!< Size = 132 (0x84) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 High-Speed Module (R_USB_HS0) - */ - -typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ - uint16_t : 7; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller - * Operation */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit - * when switching from device B to device A in OTGmode. If - * the HNPBTOA bit is 1, the internal function controlremains - * in the Suspend state until the HNP processing endseven - * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } CFIFO_b; - }; - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } D0FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write - * transmit data to the FIFO buffer by accessing these bits. */ - } D1FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-28 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be - * set only in the initial setting (before communications).The - * setting cannot be changed once communication starts. */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency - * can be improved by setting this bit to 1 if no low-speed - * device is connected directly or via FS-HUB to the USB port. */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ - - struct - { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected - * : read-only Host controller selected : read-write */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected - * : read-only Host controller selected : read-write */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected - * : read-only Host controller selected : read-write */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected - * : read-only Host controller selected : read-write */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected - * : read-only Host controller selected : read-write */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * destination function device for control transfer when the - * host controller function is selected. */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - - union - { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ - - struct - { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number - * of the selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - uint16_t : 1; - } PIPEBUF_b; - }; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the selected pipe.A size - * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * peripheral device when the host controller function is - * selected. */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the - * transfer interval timing for the selected pipe as n-th - * power of 2 of the frame timing. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for - * the next transaction of the relevant pipe. */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe - * is being used for the USB bus */ - __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is set for DATA1 */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is cleared to DATA0 */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto - * buffer clear mode for the relevant pipe */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto - * response mode for the relevant pipe. */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO - * buffer status for the relevant pipe in the transmitting - * direction. */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status - * for the relevant pipe. */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED14[11]; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED15[7]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED16[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED17; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ - - struct - { - __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset - * value for adjusting the terminating resistance. */ - uint16_t : 1; - } PHYTRIM1_b; - }; - - union - { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ - - struct - { - __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ - uint16_t : 1; - } PHYTRIM2_b; - }; - __IM uint32_t RESERVED19[3]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; -} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGTX0) - */ - -typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ -{ - union - { - __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ - __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ - }; -} R_AGTX0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CANFD ECC (R_ECCMB0) - */ - -typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ -{ - union - { - __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ - - struct - { - __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ - __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ - __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ - __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ - __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ - __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ - __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ - uint32_t : 2; - __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag - * Clear */ - __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ - __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ - uint32_t : 2; - __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ - __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ - __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ - uint32_t : 14; - } EC710CTL_b; - }; - - union - { - __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ - uint16_t : 5; - __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ - uint16_t : 6; - __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ - } EC710TMC_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ - - struct - { - __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ - } EC710TED_b; - }; - - union - { - __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ - - struct - { - __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ - uint32_t : 22; - } EC710EAD0_b; - }; -} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Flash (R_FLAD) - */ - -typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ -{ - __IM uint8_t RESERVED[64]; - - union - { - __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ - - struct - { - __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ - } FCKMHZ_b; - }; -} R_FLAD_Type; /*!< Size = 65 (0x41) */ - -/** @} */ /* End of group Device_Peripheral_peripherals */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ADC0_BASE 0x40170000UL - #define R_ADC1_BASE 0x40170200UL - #define R_PSCU_BASE 0x400E0000UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40083600UL - #define R_CANFD_BASE 0x400B0000UL - #define R_CRC_BASE 0x40108000UL - #define R_CTSU_BASE 0x400D0000UL - #define R_DAC_BASE 0x40171000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40109000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40082000UL - #define R_ETHERC0_BASE 0x40114100UL - #define R_ETHERC_EDMAC_BASE 0x40114000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GPT0_BASE 0x40169000UL - #define R_GPT1_BASE 0x40169100UL - #define R_GPT2_BASE 0x40169200UL - #define R_GPT3_BASE 0x40169300UL - #define R_GPT4_BASE 0x40169400UL - #define R_GPT5_BASE 0x40169500UL - #define R_GPT6_BASE 0x40169600UL - #define R_GPT7_BASE 0x40169700UL - #define R_GPT8_BASE 0x40169800UL - #define R_GPT9_BASE 0x40169900UL - #define R_GPT10_BASE 0x40169A00UL - #define R_GPT11_BASE 0x40169B00UL - #define R_GPT12_BASE 0x40169C00UL - #define R_GPT13_BASE 0x40169D00UL - #define R_GPT_OPS_BASE 0x40169A00UL - #define R_GPT_POEG0_BASE 0x4008A000UL - #define R_GPT_POEG1_BASE 0x4008A100UL - #define R_GPT_POEG2_BASE 0x4008A200UL - #define R_GPT_POEG3_BASE 0x4008A300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x4009F000UL - #define R_IIC1_BASE 0x4009F100UL - #define R_IIC2_BASE 0x4009F200UL - #define R_IWDT_BASE 0x40083200UL - #define R_I3C0_BASE 0x4011F000UL - #define R_I3C1_BASE 0x4011F400UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40084000UL - #define R_PORT0_BASE 0x40080000UL - #define R_PORT1_BASE 0x40080020UL - #define R_PORT2_BASE 0x40080040UL - #define R_PORT3_BASE 0x40080060UL - #define R_PORT4_BASE 0x40080080UL - #define R_PORT5_BASE 0x400800A0UL - #define R_PORT6_BASE 0x400800C0UL - #define R_PORT7_BASE 0x400800E0UL - #define R_PORT8_BASE 0x40080100UL - #define R_PORT9_BASE 0x40080120UL - #define R_PORT10_BASE 0x40080140UL - #define R_PORT11_BASE 0x40080160UL - #define R_PORT12_BASE 0x40080180UL - #define R_PORT13_BASE 0x400801A0UL - #define R_PORT14_BASE 0x400801C0UL - #define R_PFS_BASE 0x40080800UL - #define R_PMISC_BASE 0x40080D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40083000UL - #define R_SCI0_BASE 0x40118000UL - #define R_SCI1_BASE 0x40118100UL - #define R_SCI2_BASE 0x40118200UL - #define R_SCI3_BASE 0x40118300UL - #define R_SCI4_BASE 0x40118400UL - #define R_SCI5_BASE 0x40118500UL - #define R_SCI6_BASE 0x40118600UL - #define R_SCI7_BASE 0x40118700UL - #define R_SCI8_BASE 0x40118800UL - #define R_SCI9_BASE 0x40118900UL - #define R_SDHI0_BASE 0x40092000UL - #define R_SDHI1_BASE 0x40092400UL - #define R_SPI0_BASE 0x4011A000UL - #define R_SPI1_BASE 0x4011A100UL - #define R_SPI2_BASE 0x40072200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SSI0_BASE 0x4009D000UL - #define R_SSI1_BASE 0x4009D100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x400F3000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_WDT_BASE 0x40083400UL - #define R_TZF_BASE 0x40000E00UL - #define R_CACHE_BASE 0x40007000UL - #define R_CPSCU_BASE 0x40008000UL - #define R_CEC_BASE 0x400AC000UL - #define R_OSPI_BASE 0x400A6000UL - #define R_USB_HS0_BASE 0x40111000UL - #define R_AGTX0_BASE 0x400E8000UL - #define R_AGTX1_BASE 0x400E8100UL - #define R_AGTX2_BASE 0x400E8200UL - #define R_AGTX3_BASE 0x400E8300UL - #define R_AGTX4_BASE 0x400E8400UL - #define R_AGTX5_BASE 0x400E8500UL - #define R_AGTX6_BASE 0x400E8600UL - #define R_AGTX7_BASE 0x400E8700UL - #define R_AGTX8_BASE 0x400E8800UL - #define R_AGTX9_BASE 0x400E8900UL - #define R_ECCMB0_BASE 0x4036F200UL - #define R_ECCMB1_BASE 0x4036F300UL - #define R_FLAD_BASE 0x407FC000UL - #define R_WDT1_BASE 0x40044300UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) - #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) - #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) - #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - #define R_TZF ((R_TZF_Type *) R_TZF_BASE) - #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) - #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) - #define R_CEC ((R_CEC_Type *) R_CEC_BASE) - #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) - #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) - #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) - #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) - #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) - #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) - #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) - #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) - #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) - #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) - #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) - #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) - #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) - #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - -/* ========================================= End of section using anonymous unions ========================================= */ - #if defined(__CC_ARM) - #pragma pop - #elif defined(__ICCARM__) - -/* leave anonymous unions enabled */ - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning restore - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #endif - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_clusters - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ SDRAM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SDCCR ========================================================= */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCMOD ========================================================= */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDAMOD ========================================================= */ - #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ - #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDSELF ========================================================= */ - #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ - #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDRFCR ========================================================= */ - #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ - #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ -/* ======================================================== SDRFEN ========================================================= */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ -/* ========================================================= SDICR ========================================================= */ - #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ - #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SDIR ========================================================== */ - #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ - #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ - #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ - #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ -/* ========================================================= SDADR ========================================================= */ - #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ - #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ -/* ========================================================= SDTR ========================================================== */ - #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ - #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ - #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ - #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ - #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ - #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ -/* ========================================================= SDMOD ========================================================= */ - #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ - #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ -/* ========================================================= SDSR ========================================================== */ - #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ - #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ - #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ - #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= IRQEN ========================================================= */ - #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ - #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ DMACDTCERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FLBI ========================================================== */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== MRE0BI ========================================================= */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S2BI ========================================================== */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S3BI ========================================================== */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== STBYSBI ======================================================== */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= ECBI ========================================================== */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= EOBI ========================================================== */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI0BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI1BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PBBI ========================================================== */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PABI ========================================================== */ - #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PIBI ========================================================== */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PSBI ========================================================== */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU0SAHBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT1 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FHBI ========================================================== */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ======================================================== MRC0BI ========================================================= */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ BMSAERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ - #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ OAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BUSOAD ========================================================= */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSOADPT ======================================================== */ - #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== MSAOAD ========================================================= */ - #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= MSAPT ========================================================= */ - #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ MBWERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ - #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ - #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ - #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ ELSEGR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== BY =========================================================== */ - #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ - #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ - #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ - #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ ELSR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== HA =========================================================== */ - #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ - #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ SAR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== L =========================================================== */ - #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ - #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ -/* =========================================================== U =========================================================== */ - #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ - #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ - #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ REGION ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AC =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ -/* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ GROUP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== EN =========================================================== */ - #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= ENPT ========================================================== */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== RPT ========================================================== */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== RPT_SEC ======================================================== */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================== CTL ========================================================== */ - #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ - #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== SA =========================================================== */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== EA =========================================================== */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ PIN ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= PmnPFS_BY ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ======================================================= PmnPFS_HA ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ -/* ======================================================== PmnPFS ========================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PORT ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PMSAR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PMSAR ========================================================= */ - -/* =========================================================================================================================== */ -/* ================ RTCCR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RTCCR ========================================================= */ - #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ - #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ - #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ - #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RSEC ========================================================== */ - #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ - #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMIN ========================================================== */ - #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ - #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ -/* ========================================================== RHR ========================================================== */ - #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ - #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RDAY ========================================================== */ - #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ - #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMON ========================================================== */ - #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= AGTCR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTMR1 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ -/* ======================================================== AGTMR2 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ -/* ===================================================== AGTIOSEL_ALT ====================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ -/* ======================================================== AGTIOC ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTISR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTCMSR ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ -/* ======================================================= AGTIOSEL ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ AGT16 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ AGT32 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ - -/** @} */ /* End of group PosMask_clusters */ - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ADCSR ========================================================= */ - #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ - #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ - #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ - #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ - #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ - #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ - #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ - #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ - #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ - #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSA ========================================================= */ - #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ - #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADS ========================================================= */ - #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ - #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADC ========================================================= */ - #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ - #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ - #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ -/* ========================================================= ADCER ========================================================= */ - #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ - #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ - #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ - #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ - #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ - #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ - #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ - #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ - #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSTRGR ======================================================== */ - #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ - #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ - #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ - #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ -/* ======================================================== ADEXICR ======================================================== */ - #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ - #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ - #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ - #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ - #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ - #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ - #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ - #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ - #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSB ========================================================= */ - #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ - #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADDBLDR ======================================================== */ - #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ - #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADTSDR ========================================================= */ - #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ - #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADOCDR ========================================================= */ - #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ - #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADRD_RIGHT ======================================================= */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ -/* ======================================================= ADRD_LEFT ======================================================= */ - #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ - #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ========================================================= ADDR ========================================================== */ - #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ - #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADSHCR ========================================================= */ - #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ - #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ - #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ - #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ - #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ -/* ======================================================== ADDISCR ======================================================== */ - #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ - #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ - #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADSHMSR ======================================================== */ - #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ - #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADACSR ========================================================= */ - #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ - #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ -/* ======================================================== ADGSPCR ======================================================== */ - #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ - #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ - #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ - #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ -/* ========================================================= ADICR ========================================================= */ - #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ - #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ -/* ======================================================= ADDBLDRA ======================================================== */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADDBLDRB ======================================================== */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADHVREFCNT ======================================================= */ - #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= ADWINMON ======================================================== */ - #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ - #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ - #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ - #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPCR ======================================================== */ - #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ - #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ - #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ - #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ - #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ - #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ - #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCMPANSER ======================================================= */ - #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ - #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPLER ======================================================== */ - #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ - #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPANSR ======================================================= */ - #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ - #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPLR ======================================================== */ - #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ - #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPDR0 ======================================================== */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPDR1 ======================================================== */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADCMPSR ======================================================== */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPSER ======================================================== */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPBNSR ======================================================= */ - #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ - #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ -/* ======================================================= ADWINLLB ======================================================== */ - #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ - #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADWINULB ======================================================== */ - #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ - #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPBSR ======================================================== */ - #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ - #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSSTRL ======================================================== */ - #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRT ======================================================== */ - #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRO ======================================================== */ - #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTR ========================================================= */ - #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADPGACR ======================================================== */ - #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ - #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ - #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ - #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ - #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ - #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ - #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ - #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ - #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ - #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ - #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ - #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ - #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ - #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ - #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ - #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ - #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADRD ========================================================== */ - #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ -/* ========================================================= ADRST ========================================================= */ - #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ====================================================== VREFAMPCNT ======================================================= */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ - #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCALEXE ======================================================== */ - #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ - #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ - #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANIM ========================================================= */ - #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ - #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGAGS0 ======================================================== */ - #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ - #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= ADPGADCR0 ======================================================= */ - #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ - #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ - #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ - #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ - #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ - #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ - #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ - #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ - #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADREF ========================================================= */ - #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ - #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ - #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ -/* ======================================================== ADEXREF ======================================================== */ - #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ - #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADAMPOFF ======================================================== */ - #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ - #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ -/* ======================================================== ADTSTPR ======================================================== */ - #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ - #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ - #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================= ADDDACER ======================================================== */ - #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ - #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ - #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ - #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADEXTSTR ======================================================== */ - #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ - #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ - #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ - #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ -/* ======================================================== ADTSTRA ======================================================== */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ - #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ - #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADTSTRB ======================================================== */ - #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ - #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ -/* ======================================================== ADTSTRC ======================================================== */ - #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ - #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ - #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ADTSTRD ======================================================== */ - #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ - #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR0 ======================================================= */ - #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ - #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR1 ======================================================= */ - #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ - #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR2 ======================================================= */ - #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ - #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSWCR ========================================================= */ - #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ - #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ - #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ -/* ======================================================== ADGSCS ========================================================= */ - #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ - #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ - #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ -/* ========================================================= ADSER ========================================================= */ - #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ - #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ -/* ======================================================== ADBUF0 ========================================================= */ - #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF1 ========================================================= */ - #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF2 ========================================================= */ - #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF3 ========================================================= */ - #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF4 ========================================================= */ - #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF5 ========================================================= */ - #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF6 ========================================================= */ - #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF7 ========================================================= */ - #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF8 ========================================================= */ - #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF9 ========================================================= */ - #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF10 ======================================================== */ - #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF11 ======================================================== */ - #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF12 ======================================================== */ - #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF13 ======================================================== */ - #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF14 ======================================================== */ - #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF15 ======================================================== */ - #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUFEN ======================================================== */ - #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ - #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADBUFPTR ======================================================== */ - #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ - #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ - #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS0 ======================================================= */ - #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS1 ======================================================= */ - #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADREFMON ======================================================== */ - #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ - #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ - #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ - #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ - #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ - #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ - #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ - #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ - #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ - #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ - #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ - #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ - #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ - #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ - #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ - #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ - #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ - #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ - #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ - #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ - #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ - #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ - #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ - #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ - #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ - #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ - #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ - #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ - #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ -/* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ - #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ - #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ - #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ -/* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ -/* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ -/* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ - #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ -/* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ - #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSMABT ======================================================== */ - #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSDIVBYP ======================================================= */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSTHRPUT ======================================================= */ - #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ - #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CACR0 ========================================================= */ - #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ - #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR1 ========================================================= */ - #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ - #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ - #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ - #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR2 ========================================================= */ - #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ - #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ - #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ - #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ - #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ -/* ========================================================= CAICR ========================================================= */ - #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ - #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ - #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ - #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ - #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ - #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ - #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ -/* ========================================================= CASTR ========================================================= */ - #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ - #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ - #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ - #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ -/* ======================================================== CAULVR ========================================================= */ - #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ - #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CALLVR ========================================================= */ - #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ - #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CACNTBR ======================================================== */ - #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ - #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CRCCR0 ========================================================= */ - #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ - #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ - #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ - #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ -/* ======================================================== CRCCR1 ========================================================= */ - #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ - #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ - #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CRCDIR ========================================================= */ - #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ - #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDIR_BY ======================================================= */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCDOR ========================================================= */ - #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ - #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDOR_HA ======================================================= */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ -/* ======================================================= CRCDOR_BY ======================================================= */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCSAR ========================================================= */ - #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ - #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTSUCR0 ======================================================== */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ -/* ======================================================== CTSUCR1 ======================================================== */ - #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ - #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ - #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUSDPRS ======================================================= */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSST ======================================================== */ - #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ - #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ -/* ======================================================= CTSUMCH0 ======================================================== */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUMCH1 ======================================================== */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUCHAC ======================================================== */ - #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUCHTRC ======================================================= */ - #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUDCLKC ======================================================= */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== CTSUST ========================================================= */ - #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ - #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ - #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ - #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ - #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ - #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ -/* ======================================================== CTSUSSC ======================================================== */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSO0 ======================================================== */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ - #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ - #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ -/* ======================================================== CTSUSO1 ======================================================== */ - #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ - #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ -/* ======================================================== CTSUSC ========================================================= */ - #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ - #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ -/* ======================================================== CTSURC ========================================================= */ - #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ - #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ -/* ======================================================= CTSUERRS ======================================================== */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUTRMR ======================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DACR ========================================================== */ - #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ - #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ - #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ - #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ -/* ========================================================= DADR ========================================================== */ - #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ - #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DADPR ========================================================= */ - #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ - #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADSCR ======================================================== */ - #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ - #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ -/* ======================================================= DAVREFCR ======================================================== */ - #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ - #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ -/* ========================================================= DAPC ========================================================== */ - #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ - #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== DAAMPCR ======================================================== */ - #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ - #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DAASWCR ======================================================== */ - #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ - #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ - #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ - #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== DBGSTR ========================================================= */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ -/* ======================================================= DBGSTOPCR ======================================================= */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ -/* ======================================================= FSBLSTAT ======================================================== */ - #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ - #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ -/* ======================================================== DMECHR ========================================================= */ - #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ - #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ - #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ - #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ - #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ -/* ========================================================= DELSR ========================================================= */ - #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMSAR ========================================================= */ - #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ - #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMDAR ========================================================= */ - #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ - #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCRA ========================================================= */ - #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ - #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ - #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ - #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMCRB ========================================================= */ - #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ - #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ - #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMTMD ========================================================= */ - #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ - #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ - #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ - #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ - #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ - #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ -/* ========================================================= DMINT ========================================================= */ - #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ - #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ - #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ - #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ - #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ - #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMAMD ========================================================= */ - #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ - #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ - #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ - #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ - #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ - #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ - #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ -/* ========================================================= DMOFR ========================================================= */ - #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ - #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCNT ========================================================= */ - #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ - #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMREQ ========================================================= */ - #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ - #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ - #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSTS ========================================================= */ - #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ - #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ - #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ - #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSRR ========================================================= */ -/* ========================================================= DMDRR ========================================================= */ -/* ========================================================= DMSBS ========================================================= */ - #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ - #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ - #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMDBS ========================================================= */ - #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ - #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ - #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMBWR ========================================================= */ - #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ - #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DOCR ========================================================== */ - #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ - #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ - #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ - #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ - #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ -/* ========================================================= DODIR ========================================================= */ - #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ - #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DODSR ========================================================= */ - #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ - #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= DTCADMOD ======================================================== */ - #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ - #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ -/* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ -/* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ====================================================== DTCVBR_SEC ======================================================= */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DTCDISP ======================================================== */ - #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ - #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCIBR ========================================================= */ - #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ - #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ -/* ========================================================= DTCOR ========================================================= */ - #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ - #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSQE ========================================================= */ - #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ - #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARA ======================================================== */ - #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ - #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ - #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ - #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARB ======================================================== */ - #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ - #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ - #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ - #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ - #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ - #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ - #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ - #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ - #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ - #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ - #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ - #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ - #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ - #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ - #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ - #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ - #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARC ======================================================== */ - #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ - #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ - #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ - #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ECMR ========================================================== */ - #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ - #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ - #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ - #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ - #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ - #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ - #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ - #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ - #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ - #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ - #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ - #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ - #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ -/* ========================================================= RFLR ========================================================== */ - #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ - #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ - #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ - #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ - #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ - #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ - #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ -/* ======================================================== ECSIPR ========================================================= */ - #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ - #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ - #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ - #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ -/* ========================================================== PIR ========================================================== */ - #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ - #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ - #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ - #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ - #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ -/* ========================================================== PSR ========================================================== */ - #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ - #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ -/* ========================================================= RDMLR ========================================================= */ - #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ - #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ -/* ========================================================= IPGR ========================================================== */ - #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ - #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ -/* ========================================================== APR ========================================================== */ - #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ - #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ -/* ========================================================== MPR ========================================================== */ - #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ - #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFCF ========================================================== */ - #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ - #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ -/* ======================================================== TPAUSER ======================================================== */ - #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ - #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ -/* ======================================================= TPAUSECR ======================================================== */ -/* ========================================================= BCFRR ========================================================= */ - #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ - #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ -/* ========================================================= MAHR ========================================================== */ - #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ - #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MALR ========================================================== */ - #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ - #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ -/* ========================================================= TROCR ========================================================= */ - #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ - #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CDCR ========================================================== */ -/* ========================================================= LCCR ========================================================== */ - #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ - #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CNDCR ========================================================= */ - #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ - #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CEFCR ========================================================= */ - #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ - #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= FRECR ========================================================= */ - #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ - #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TSFRCR ========================================================= */ - #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ - #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TLFRCR ========================================================= */ - #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ - #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RFCR ========================================================== */ - #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ - #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MAFCR ========================================================= */ - #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ - #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= EDMR ========================================================== */ - #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ - #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ - #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDTRR ========================================================= */ - #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ - #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDRRR ========================================================= */ - #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ - #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ -/* ========================================================= TDLAR ========================================================= */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDLAR ========================================================= */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= EESR ========================================================== */ - #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ - #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ - #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ - #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ - #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ - #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ - #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ - #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ - #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ - #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ - #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ - #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ - #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ - #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ - #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ - #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ - #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ -/* ======================================================== EESIPR ========================================================= */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ -/* ======================================================== TRSCER ========================================================= */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ -/* ========================================================= RMFCR ========================================================= */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= TFTR ========================================================== */ - #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ - #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ -/* ========================================================== FDR ========================================================== */ - #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ - #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ - #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ - #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ -/* ========================================================= RMCR ========================================================== */ - #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ - #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ -/* ========================================================= TFUCR ========================================================= */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFOCR ========================================================= */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ -/* ========================================================= IOSR ========================================================== */ - #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ - #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ -/* ========================================================= FCFTR ========================================================= */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ -/* ======================================================== RPADIR ========================================================= */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ -/* ========================================================= TRIMD ========================================================= */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ -/* ========================================================= RBWAR ========================================================= */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDFAR ========================================================= */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TBRAR ========================================================= */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TDFAR ========================================================= */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/* ====================================================== FACI_CMD16 ======================================================= */ -/* ======================================================= FACI_CMD8 ======================================================= */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ -/* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FMEPROT ======================================================== */ - #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ - #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT0 ======================================================== */ - #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ - #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT1 ======================================================== */ - #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ - #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ - #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ - #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ - #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ -/* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ -/* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ -/* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ -/* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ -/* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ -/* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== FBCADDR ======================================================== */ - #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ - #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ -/* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ -/* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ -/* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ -/* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ -/* ======================================================= FCNTSELR ======================================================== */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ -/* ====================================================== FCNTDATAR0 ======================================================= */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FCNTDATAR1 ======================================================= */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ -/* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ -/* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ -/* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ - #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ - #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ - #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ - #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= GTWP ========================================================== */ - #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ - #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ - #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ - #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ - #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTR ========================================================= */ - #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ - #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTP ========================================================= */ - #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ - #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCLR ========================================================= */ - #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ - #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSSR ========================================================= */ - #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ - #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ - #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ - #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ - #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ - #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ - #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ - #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ - #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ - #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ - #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ - #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ - #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTPSR ========================================================= */ - #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ - #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ - #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ - #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ - #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ - #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ - #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ - #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ - #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ - #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ - #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ - #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ - #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCSR ========================================================= */ - #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ - #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ - #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ - #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ - #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ - #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ - #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ - #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ - #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ - #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ - #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ - #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ - #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ - #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ - #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTUPSR ========================================================= */ - #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ - #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ - #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ - #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ - #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ - #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ - #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ - #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ - #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ - #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ - #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ - #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ - #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTDNSR ========================================================= */ - #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ - #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ - #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ - #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ - #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ - #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ - #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ - #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ - #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ - #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ - #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ - #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ - #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICASR ======================================================== */ - #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ - #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ - #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ - #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ - #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ - #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ - #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ - #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ - #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ - #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ - #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ - #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ - #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICBSR ======================================================== */ - #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ - #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ - #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ - #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ - #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ - #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ - #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ - #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ - #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ - #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ - #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ - #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ - #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ - #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ - #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ - #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ - #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ - #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ - #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ - #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ - #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ - #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ - #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ -/* ======================================================= GTUDDTYC ======================================================== */ - #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ - #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ - #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ - #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ - #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ - #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ - #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ - #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ -/* ========================================================= GTIOR ========================================================= */ - #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ - #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ - #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ - #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ - #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ - #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ - #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ - #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ - #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ - #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ - #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ - #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ - #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ - #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ - #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ - #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ - #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ - #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ - #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTINTAD ======================================================== */ - #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ - #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ - #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ - #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ - #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ - #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ - #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ - #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ - #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ - #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ - #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ - #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTST ========================================================== */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ - #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ - #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ - #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ - #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ - #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ - #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ - #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ - #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ - #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ - #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ - #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ - #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ - #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ - #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ - #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ - #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ - #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ - #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTBER ========================================================= */ - #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ - #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ - #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ - #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ - #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ - #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ - #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ - #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ - #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ - #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ - #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ - #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ - #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ - #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ -/* ========================================================= GTITC ========================================================= */ - #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ - #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ - #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ - #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ - #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ - #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ - #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ - #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ - #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ - #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ - #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCNT ========================================================= */ - #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ - #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTCCR ========================================================= */ - #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ - #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPR ========================================================== */ - #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ - #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPBR ========================================================= */ - #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ - #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTPDBR ========================================================= */ - #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ - #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRA ======================================================== */ - #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ - #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRB ======================================================== */ - #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ - #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRA ======================================================== */ - #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ - #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRB ======================================================== */ - #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ - #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRA ======================================================= */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRB ======================================================= */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTDTCR ========================================================= */ - #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ - #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ - #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ - #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ - #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ -/* ========================================================= GTDVU ========================================================= */ - #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDVD ========================================================= */ - #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ - #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBU ========================================================= */ - #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBD ========================================================= */ - #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ - #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTSOS ========================================================= */ - #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ - #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ -/* ======================================================== GTSOTR ========================================================= */ - #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ - #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTADSMR ======================================================== */ - #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ - #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ - #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ - #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ - #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTEITC ========================================================= */ - #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ - #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ - #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ - #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ - #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ - #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ - #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ - #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= GTEITLI1 ======================================================== */ - #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ - #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ - #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ - #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ - #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ - #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ - #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ - #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ - #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ -/* ======================================================= GTEITLI2 ======================================================== */ - #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ - #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ - #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ -/* ======================================================== GTEITLB ======================================================== */ - #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ - #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ - #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ - #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ - #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ - #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ - #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ - #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ -/* ======================================================== GTICLF ========================================================= */ - #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ - #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ - #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ - #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ - #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ - #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ -/* ========================================================= GTPC ========================================================== */ - #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ - #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ - #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ - #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ -/* ======================================================= GTADCMSC ======================================================== */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ - #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ - #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ -/* ======================================================= GTADCMSS ======================================================== */ - #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ - #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ -/* ======================================================== GTSECSR ======================================================== */ - #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ - #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ - #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ - #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ - #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ - #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ - #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ - #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ - #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ - #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ - #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTSECR ========================================================= */ - #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ - #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ - #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ - #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ - #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ - #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ - #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ - #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ - #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ - #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ - #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ - #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ - #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ -/* ======================================================== GTBER2 ========================================================= */ - #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ - #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ - #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ - #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ - #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ - #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ - #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ - #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ - #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ - #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ - #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ - #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ - #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ - #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ - #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ - #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ - #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ - #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ - #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ - #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ - #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ -/* ======================================================== GTOLBR ========================================================= */ - #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ - #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ - #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTICCR ========================================================= */ - #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ - #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ - #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ - #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ - #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ - #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ - #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ - #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ - #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ - #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ - #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ - #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ - #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ - #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ - #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ - #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ - #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ - #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ - #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ - #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ - #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= OPSCR ========================================================= */ - #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ - #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ - #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ - #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ - #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ - #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ - #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ - #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ - #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ - #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ - #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ - #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ - #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ - #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ - #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ -/* ======================================================== GTONCWP ======================================================== */ - #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== GTONCCR ======================================================== */ - #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ - #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ - #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ - #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ - #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ - #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ -/* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ -/* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ -/* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ -/* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ -/* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN2 ========================================================= */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ICCR1 ========================================================= */ - #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ - #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ - #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ - #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ - #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ - #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ - #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ - #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ - #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ -/* ========================================================= ICCR2 ========================================================= */ - #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ - #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ - #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ - #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ - #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ - #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ - #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR1 ========================================================= */ - #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ - #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ - #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ - #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ -/* ========================================================= ICMR2 ========================================================= */ - #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ - #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ - #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ - #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ - #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ - #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR3 ========================================================= */ - #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ - #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ - #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ - #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ - #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ - #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ - #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ - #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ -/* ========================================================= ICFER ========================================================= */ - #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ - #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ - #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ - #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ - #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ - #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ - #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ - #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ - #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSER ========================================================= */ - #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ - #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ - #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ - #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ - #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ - #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ - #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ -/* ========================================================= ICIER ========================================================= */ - #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ - #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ - #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ - #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ - #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ - #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ - #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ - #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR1 ========================================================= */ - #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ - #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ - #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ - #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ - #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ - #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ - #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR2 ========================================================= */ - #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ - #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ - #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ - #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ - #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ - #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ - #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ -/* ========================================================= ICBRL ========================================================= */ - #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ - #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICBRH ========================================================= */ - #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ - #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICDRT ========================================================= */ - #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ - #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ -/* ========================================================= ICDRR ========================================================= */ - #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ - #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ -/* ========================================================= ICWUR ========================================================= */ - #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ - #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ - #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ - #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ - #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ - #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICWUR2 ========================================================= */ - #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ - #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ - #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ - #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== IWDTRR ========================================================= */ - #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ - #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ -/* ======================================================== IWDTCR ========================================================= */ - #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ======================================================== IWDTSR ========================================================= */ - #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== IWDTRCR ======================================================== */ - #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= IWDTCSTPR ======================================================= */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PRTS ========================================================== */ - #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ - #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ -/* ========================================================= CECTL ========================================================= */ - #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ - #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ -/* ========================================================= BCTL ========================================================== */ - #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ - #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ - #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ - #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ - #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ - #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ - #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSDVAD ========================================================= */ - #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ - #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ - #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTCTL ========================================================= */ - #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ - #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ - #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ - #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ - #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ - #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ - #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ - #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ - #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ - #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ - #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ - #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ - #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ -/* ========================================================= PRSST ========================================================= */ - #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ - #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ - #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ - #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ -/* ========================================================= INST ========================================================== */ - #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ - #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ -/* ========================================================= INSTE ========================================================= */ - #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ - #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ -/* ========================================================= INIE ========================================================== */ - #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ - #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== INSTFC ========================================================= */ - #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ - #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= DVCT ========================================================== */ - #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ - #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ -/* ======================================================== IBINCTL ======================================================== */ - #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ - #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ - #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ -/* ========================================================= BFCTL ========================================================= */ - #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ - #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ - #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ - #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ - #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ - #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ - #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ - #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ -/* ========================================================= SVCTL ========================================================= */ - #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ - #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ - #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ - #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ - #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ -/* ======================================================= REFCKCTL ======================================================== */ - #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ - #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ -/* ========================================================= STDBR ========================================================= */ - #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ - #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ - #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ - #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ - #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ - #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ -/* ========================================================= EXTBR ========================================================= */ - #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ - #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ - #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ - #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ - #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ -/* ======================================================== BFRECDT ======================================================== */ - #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ - #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BAVLCDT ======================================================== */ - #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ - #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BIDLCDT ======================================================== */ - #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ - #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== OUTCTL ========================================================= */ - #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ - #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ - #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ - #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ - #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ - #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ - #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ - #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ -/* ========================================================= INCTL ========================================================= */ - #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ - #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ - #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ - #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ -/* ======================================================== TMOCTL ========================================================= */ - #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ - #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ - #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ - #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ - #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ - #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ -/* ========================================================= WUCTL ========================================================= */ - #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ - #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ - #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ - #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ - #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ -/* ======================================================== ACKCTL ========================================================= */ - #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ - #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ - #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ - #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTRCTL ======================================================== */ - #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ - #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ - #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTLCTL ======================================================== */ - #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ - #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ - #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ - #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ - #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ - #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ - #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SVTDLG0 ======================================================== */ - #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ - #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= STCTL ========================================================= */ - #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ - #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ATCTL ========================================================= */ - #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ - #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ - #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ - #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ - #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ -/* ========================================================= ATTRG ========================================================= */ - #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ - #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== ATCCNTE ======================================================== */ - #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ - #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ -/* ======================================================== CNDCTL ========================================================= */ - #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ - #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ - #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ - #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ -/* ======================================================== NCMDQP ========================================================= */ -/* ======================================================== NRSPQP ========================================================= */ -/* ======================================================== NTDTBP0 ======================================================== */ -/* ======================================================== NIBIQP ========================================================= */ -/* ========================================================= NRSQP ========================================================= */ -/* ======================================================== HCMDQP ========================================================= */ - #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ - #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HRSPQP ========================================================= */ - #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ - #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HTDTBP ========================================================= */ - #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ - #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== NQTHCTL ======================================================== */ - #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ - #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= NTBTHCTL0 ======================================================= */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ======================================================= NRQTHCTL ======================================================== */ - #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ - #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ -/* ======================================================== HQTHCTL ======================================================== */ - #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= HTBTHCTL ======================================================== */ - #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ========================================================== BST ========================================================== */ - #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ - #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ - #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ - #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ - #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ - #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ - #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ - #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ - #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTE ========================================================== */ - #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ - #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ - #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ - #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ - #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ - #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ - #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ - #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ - #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ -/* ========================================================== BIE ========================================================== */ - #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ - #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ - #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ - #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ - #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ - #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ - #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ - #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ - #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTFC ========================================================= */ - #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ - #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ - #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ - #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ - #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ - #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ - #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ - #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ - #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= NTST ========================================================== */ - #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ - #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ - #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ - #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ - #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ -/* ========================================================= NTSTE ========================================================= */ - #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ - #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ - #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ - #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ - #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ -/* ========================================================= NTIE ========================================================== */ - #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ - #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ - #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ - #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ - #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ -/* ======================================================== NTSTFC ========================================================= */ - #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ - #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ - #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ - #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ -/* ========================================================= HTST ========================================================== */ - #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ - #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ - #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ -/* ========================================================= HTSTE ========================================================= */ - #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ - #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ - #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ -/* ========================================================= HTIE ========================================================== */ - #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ - #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ - #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== HTSTFC ========================================================= */ - #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ - #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ - #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= BCST ========================================================== */ - #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ - #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ - #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ - #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ -/* ========================================================= SVST ========================================================== */ - #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ - #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ - #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ - #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ - #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ -/* ========================================================= WUST ========================================================== */ - #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ - #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ -/* ======================================================== MRCCPT ========================================================= */ - #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ - #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DATBAS0 ======================================================== */ - #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS1 ======================================================== */ - #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS2 ======================================================== */ - #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS3 ======================================================== */ - #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS4 ======================================================== */ - #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS5 ======================================================== */ - #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS6 ======================================================== */ - #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS7 ======================================================== */ - #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= EXDATBAS ======================================================== */ - #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ - #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ - #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ - #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ - #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= SDATBAS0 ======================================================== */ - #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS1 ======================================================== */ - #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS2 ======================================================== */ - #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================== MSDCT0 ========================================================= */ - #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT1 ========================================================= */ - #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT2 ========================================================= */ - #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT3 ========================================================= */ - #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT4 ========================================================= */ - #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT5 ========================================================= */ - #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT6 ========================================================= */ - #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT7 ========================================================= */ - #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ========================================================= SVDCT ========================================================= */ - #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ - #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ - #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ - #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ - #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ - #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ - #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ - #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================= SDCTPIDL ======================================================== */ -/* ======================================================= SDCTPIDH ======================================================== */ -/* ======================================================== SVDVAD0 ======================================================== */ - #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD1 ======================================================== */ - #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD2 ======================================================== */ - #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== CSECMD ========================================================= */ - #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ - #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ - #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ - #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ -/* ======================================================== CEACTST ======================================================== */ - #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ - #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CMWLG ========================================================= */ - #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ - #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= CMRLG ========================================================= */ - #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ - #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ - #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ - #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ -/* ======================================================== CETSTMD ======================================================== */ - #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ - #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ -/* ======================================================== CGDVST ========================================================= */ - #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ - #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ - #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ - #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ - #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ - #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ - #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ -/* ======================================================== CMDSPW ========================================================= */ - #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ - #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPR ========================================================= */ - #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ - #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ - #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ - #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPT ========================================================= */ - #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ - #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ - #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ - #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ -/* ========================================================= CETSM ========================================================= */ - #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ - #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ - #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ - #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ - #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ - #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ - #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ -/* ========================================================= CETSS ========================================================= */ - #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ - #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ - #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ - #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ - #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ -/* ======================================================= CGHDRCAP ======================================================== */ - #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ - #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ - #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ - #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BITCNT ========================================================= */ - #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ - #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ - #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ - #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ -/* ======================================================== NQSTLV ========================================================= */ - #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ - #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ - #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ - #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================= NDBSTLV0 ======================================================== */ - #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================= NRSQSTLV ======================================================== */ - #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ - #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HQSTLV ========================================================= */ - #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ - #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HDBSTLV ======================================================== */ - #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================== PRSTDBG ======================================================== */ - #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ - #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ - #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ - #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ - #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ -/* ======================================================= MSERRCNT ======================================================== */ - #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ - #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ -/* ======================================================== SC1CPT ========================================================= */ - #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ - #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ -/* ======================================================== SC2CPT ========================================================= */ - #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ - #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= OADPT ========================================================= */ - #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== MSTPCRA ======================================================== */ - #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRB ======================================================== */ - #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ - #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRC ======================================================== */ - #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ - #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRD ======================================================== */ - #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ - #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRE ======================================================== */ - #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ - #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ -/* ======================================================= LSMRWDIS ======================================================== */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ - #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PODR ========================================================== */ - #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ========================================================== PDR ========================================================== */ - #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EIDR ========================================================== */ - #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ - #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ -/* ========================================================= PIDR ========================================================== */ - #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PORR ========================================================== */ - #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ - #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ -/* ========================================================= POSR ========================================================== */ - #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EORR ========================================================== */ - #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ - #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ -/* ========================================================= EOSR ========================================================== */ - #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PFENET ========================================================= */ - #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ - #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ - #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ - #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================== PRWCNTR ======================================================== */ - #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ - #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SFMSMD ========================================================= */ - #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ - #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ - #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ - #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ - #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ - #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ - #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ - #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ - #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ - #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ - #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ -/* ======================================================== SFMSSC ========================================================= */ - #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ - #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ - #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ - #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSKC ========================================================= */ - #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ - #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ - #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMSST ========================================================= */ - #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ - #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ - #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ - #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMCOM ========================================================= */ - #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ - #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMCMD ========================================================= */ - #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ - #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCST ========================================================= */ - #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ - #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ - #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMSIC ========================================================= */ - #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ - #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMSAC ========================================================= */ - #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ - #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ - #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMSDC ========================================================= */ - #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ - #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ - #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ - #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ - #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ - #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSPC ========================================================= */ - #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ - #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ - #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMPMD ========================================================= */ - #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ - #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCNT1 ======================================================== */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ - #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ - #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ - #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECCNT ======================================================== */ - #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ - #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINCNT ======================================================== */ - #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ - #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ -/* ======================================================== RHRCNT ========================================================= */ - #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ - #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ -/* ======================================================== RWKCNT ========================================================= */ - #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================== RDAYCNT ======================================================== */ - #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RMONCNT ======================================================== */ - #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RYRCNT ========================================================= */ - #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT0AR ======================================================== */ - #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ - #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECAR ========================================================= */ - #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT1AR ======================================================== */ - #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ - #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINAR ========================================================= */ - #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT2AR ======================================================== */ - #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ - #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RHRAR ========================================================= */ - #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT3AR ======================================================== */ - #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ - #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RWKAR ========================================================= */ - #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================= BCNT0AER ======================================================== */ - #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RDAYAR ========================================================= */ - #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT1AER ======================================================== */ - #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RMONAR ========================================================= */ - #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT2AER ======================================================== */ - #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ========================================================= RYRAR ========================================================= */ - #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT3AER ======================================================== */ - #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RYRAREN ======================================================== */ - #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR1 ========================================================== */ - #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ - #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ - #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ - #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ - #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ - #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ - #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR2 ========================================================== */ - #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ - #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ - #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ - #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ - #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ - #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ - #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ - #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ - #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR4 ========================================================== */ - #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ - #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ - #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRH ========================================================== */ - #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ - #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRL ========================================================== */ - #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= RADJ ========================================================== */ - #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ - #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ - #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ - #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ -/* ========================================================= RADJ2 ========================================================= */ - #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ - #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SMR ========================================================== */ - #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ - #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ - #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ - #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ======================================================= SMR_SMCI ======================================================== */ - #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ - #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ - #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ - #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ - #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ========================================================== BRR ========================================================== */ - #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ - #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ -/* ========================================================== SCR ========================================================== */ - #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ======================================================= SCR_SMCI ======================================================== */ - #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ========================================================== TDR ========================================================== */ - #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ - #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ -/* ========================================================== SSR ========================================================== */ - #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_FIFO ======================================================== */ - #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ - #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ - #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_MANC ======================================================== */ - #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ - #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_SMCI ======================================================== */ - #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ - #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ========================================================== RDR ========================================================== */ - #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ - #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ -/* ========================================================= SCMR ========================================================== */ - #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ - #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ - #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ - #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ - #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ - #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ -/* ========================================================= SEMR ========================================================== */ - #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ - #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ - #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ - #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ - #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ - #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ - #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ - #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ - #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= SNFR ========================================================== */ - #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ - #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ -/* ========================================================= SIMR1 ========================================================= */ - #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ - #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ - #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ - #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR2 ========================================================= */ - #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ - #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ - #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ - #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR3 ========================================================= */ - #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ - #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ - #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ - #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ - #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ - #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SISR ========================================================== */ - #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ - #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ -/* ========================================================= SPMR ========================================================== */ - #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ - #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ - #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ - #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ - #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ - #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ - #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ - #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ -/* ========================================================= TDRHL ========================================================= */ - #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ - #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FTDRHL ========================================================= */ - #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ -/* ========================================================= FTDRH ========================================================= */ - #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ - #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ - #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FTDRL ========================================================= */ - #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ - #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= RDRHL ========================================================= */ - #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ - #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FRDRHL ========================================================= */ - #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ - #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ - #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ - #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ - #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ - #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ -/* ======================================================= TDRHL_MAN ======================================================= */ - #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ -/* ======================================================= RDRHL_MAN ======================================================= */ - #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRH ========================================================= */ - #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ - #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ - #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRL ========================================================= */ - #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ - #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= MDDR ========================================================== */ - #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ - #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ -/* ========================================================= DCCR ========================================================== */ - #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ - #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ - #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ - #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ - #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ - #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ -/* ========================================================== FCR ========================================================== */ - #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ - #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ - #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ - #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ - #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ - #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ - #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ - #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ -/* ========================================================== FDR ========================================================== */ - #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ - #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ - #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ - #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ -/* ========================================================== LSR ========================================================== */ - #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ - #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ - #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ - #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ -/* ========================================================== CDR ========================================================== */ - #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ - #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ -/* ========================================================= SPTR ========================================================== */ - #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ - #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ - #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ - #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ - #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ - #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ - #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ - #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ACTR ========================================================== */ - #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ - #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ - #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ - #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ - #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ - #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ -/* ========================================================= ESMER ========================================================= */ - #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ - #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR0 ========================================================== */ - #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ - #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ - #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ - #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR1 ========================================================== */ - #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ - #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ - #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ - #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ - #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ - #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ -/* ========================================================== CR2 ========================================================== */ - #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ - #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ - #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ - #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ - #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ -/* ========================================================== CR3 ========================================================== */ - #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ - #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ -/* ========================================================== PCR ========================================================== */ - #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ - #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ - #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ - #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ -/* ========================================================== ICR ========================================================== */ - #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ - #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ - #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ - #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ - #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ - #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ - #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ - #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ - #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ - #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ - #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ - #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ - #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ -/* ========================================================= STCR ========================================================== */ - #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ - #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ - #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ - #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ - #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ - #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ - #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0DR ========================================================= */ -/* ========================================================= CF0CR ========================================================= */ - #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ - #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ - #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ - #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ - #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ - #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ - #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ - #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ - #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0RR ========================================================= */ -/* ======================================================== PCF1DR ========================================================= */ -/* ======================================================== SCF1DR ========================================================= */ -/* ========================================================= CF1CR ========================================================= */ - #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ - #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ - #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ - #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ - #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ - #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ - #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ - #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ - #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF1RR ========================================================= */ -/* ========================================================== TCR ========================================================== */ - #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ - #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ -/* ========================================================== TMR ========================================================== */ - #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ - #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ - #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ - #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ - #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ -/* ========================================================= TPRE ========================================================== */ -/* ========================================================= TCNT ========================================================== */ -/* ======================================================= SCIMSKEN ======================================================== */ - #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ - #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== MMR ========================================================== */ - #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ - #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ - #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ - #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ - #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ - #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ - #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ - #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ -/* ========================================================= TMPR ========================================================== */ - #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ - #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ - #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= RMPR ========================================================== */ - #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ - #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ - #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= MESR ========================================================== */ - #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ - #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ - #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ - #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ -/* ========================================================= MECR ========================================================== */ - #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ - #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ - #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ - #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SD_CMD ========================================================= */ - #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ - #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ - #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ - #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ - #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ - #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ - #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ - #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ -/* ======================================================== SD_ARG ========================================================= */ - #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ - #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_ARG1 ======================================================== */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== SD_STOP ======================================================== */ - #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ - #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ - #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_SECCNT ======================================================= */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SD_RSP10 ======================================================== */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP1 ======================================================== */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP32 ======================================================== */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP3 ======================================================== */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP54 ======================================================== */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP5 ======================================================== */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP76 ======================================================== */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ -/* ======================================================== SD_RSP7 ======================================================== */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ -/* ======================================================= SD_INFO1 ======================================================== */ - #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ - #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ - #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ - #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_INFO2 ======================================================== */ - #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ - #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ - #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ - #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ - #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ - #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ - #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ - #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ - #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ - #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ - #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ - #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO1_MASK ===================================================== */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO2_MASK ===================================================== */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_CLK_CTRL ====================================================== */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ -/* ======================================================== SD_SIZE ======================================================== */ - #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ - #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= SD_OPTION ======================================================= */ - #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ - #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ - #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ - #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ - #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ -/* ====================================================== SD_ERR_STS1 ====================================================== */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_ERR_STS2 ====================================================== */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SD_BUF0 ======================================================== */ - #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ - #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SDIO_MODE ======================================================= */ - #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ - #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ - #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ - #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SDIO_INFO1 ======================================================= */ - #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ -/* ==================================================== SDIO_INFO1_MASK ==================================================== */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_DMAEN ======================================================== */ - #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ - #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ -/* ======================================================= SOFT_RST ======================================================== */ - #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ - #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ -/* ======================================================= SDIF_MODE ======================================================= */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ -/* ======================================================= EXT_SWAP ======================================================== */ - #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ - #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SPCR ========================================================== */ - #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ - #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ - #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ - #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ - #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ - #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ - #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ - #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ - #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ -/* ========================================================= SSLP ========================================================== */ - #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ - #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ - #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ - #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ - #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ - #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ - #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ - #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ - #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPCR ========================================================= */ - #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ - #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ - #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ - #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ - #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSR ========================================================== */ - #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ - #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ - #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ - #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ - #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ - #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ - #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ - #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ - #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ -/* ========================================================= SPDR ========================================================== */ -/* ======================================================== SPDR_HA ======================================================== */ -/* ======================================================== SPDR_BY ======================================================== */ -/* ========================================================= SPSCR ========================================================= */ - #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ - #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ -/* ========================================================= SPBR ========================================================== */ - #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ - #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ -/* ========================================================= SPDCR ========================================================= */ - #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ - #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ - #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ - #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ - #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ - #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= SPCKD ========================================================= */ - #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ - #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SSLND ========================================================= */ - #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ - #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPND ========================================================== */ - #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ - #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR2 ========================================================= */ - #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ - #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ - #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ - #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ - #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ - #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ - #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCMD ========================================================= */ - #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ - #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ - #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ - #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ - #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ - #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ - #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ - #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ - #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ - #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ - #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ - #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ -/* ======================================================== SPDCR2 ========================================================= */ - #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ - #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ - #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSSR ========================================================= */ - #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ - #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ - #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR3 ========================================================= */ - #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ - #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ - #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ - #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPR ========================================================== */ - #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ - #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ - #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ - #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PARIOAD ======================================================== */ - #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR ======================================================== */ - #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMWTSC ======================================================== */ -/* ======================================================== ECCMODE ======================================================== */ - #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ - #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== ECC2STS ======================================================== */ - #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ - #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECC1STSEN ======================================================= */ - #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ - #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ECC1STS ======================================================== */ - #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ - #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCPRCR ======================================================== */ - #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECCPRCR2 ======================================================== */ - #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ - #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCETST ======================================================== */ - #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ - #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCOAD ========================================================= */ - #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR2 ======================================================= */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ - #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SSICR ========================================================= */ - #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ - #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ - #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ - #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ - #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ - #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ - #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ - #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ - #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ - #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ - #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ - #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ - #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ - #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ - #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ - #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ - #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ - #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ - #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ - #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ - #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ - #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ -/* ========================================================= SSISR ========================================================= */ - #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ - #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ - #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ - #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ - #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ - #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ - #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ - #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ - #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ - #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ - #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFCR ========================================================= */ - #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ - #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ - #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ - #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ - #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ - #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ - #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ - #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ - #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ - #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFSR ========================================================= */ - #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ - #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ - #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ - #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ - #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFTDR ======================================================== */ - #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ - #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFTDR16 ======================================================= */ -/* ======================================================= SSIFTDR8 ======================================================== */ -/* ======================================================== SSIFRDR ======================================================== */ - #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ - #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFRDR16 ======================================================= */ -/* ======================================================= SSIFRDR8 ======================================================== */ -/* ======================================================== SSIOFR ========================================================= */ - #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ - #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ - #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ - #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== SSISCR ========================================================= */ - #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ - #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ - #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ - #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ -/* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ -/* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ -/* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ -/* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ -/* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ -/* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR2 ======================================================== */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ -/* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ -/* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ -/* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ -/* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ -/* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ -/* ========================================================= LPOPT ========================================================= */ - #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ - #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ - #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ -/* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ -/* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ -/* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ -/* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ -/* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ -/* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ -/* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ -/* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ -/* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ -/* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ -/* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ -/* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ -/* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ -/* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LDOSCR ========================================================= */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ -/* ======================================================= PL2LDOSCR ======================================================= */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ -/* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ -/* ========================================================= SOMRG ========================================================= */ - #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ - #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ -/* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ -/* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ -/* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ -/* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ -/* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== SCISPICKDIVCR ===================================================== */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== CANFDCKDIVCR ====================================================== */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== GPTCKDIVCR ======================================================= */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== USB60CKDIVCR ====================================================== */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== CECCKDIVCR ======================================================= */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== I3CCKDIVCR ======================================================= */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== IICCKDIVCR ======================================================= */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ -/* ====================================================== SCISPICKCR ======================================================= */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= CANFDCKCR ======================================================= */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== GPTCKCR ======================================================== */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= USB60CKCR ======================================================= */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCKCR ======================================================== */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== IICCKCR ======================================================== */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== I3CCKCR ======================================================== */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ - #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ -/* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ -/* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ -/* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCDR ========================================================= */ - #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ - #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCR ========================================================== */ - #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ - #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ - #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ - #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ - #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ - #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ========================================================= CFIFO ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DVCHGR ========================================================= */ - #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ - #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ - #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ - #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ====================================================== USBBCCTRL0 ======================================================= */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ -/* ======================================================== UCKSEL ========================================================= */ - #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ - #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ -/* ========================================================= USBMC ========================================================= */ - #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ - #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ - #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSLEW ======================================================== */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR0R_FS ======================================================= */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR1R_FS ======================================================= */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= WDTRR ========================================================= */ - #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ - #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ -/* ========================================================= WDTCR ========================================================= */ - #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ========================================================= WDTSR ========================================================= */ - #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== WDTRCR ========================================================= */ - #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= WDTCSTPR ======================================================== */ - #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFOAD ========================================================= */ - #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ========================================================= TZFPT ========================================================= */ - #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CCACTL ========================================================= */ - #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ - #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCAFCT ========================================================= */ - #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ - #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCALCF ========================================================= */ - #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ - #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ -/* ======================================================== SCACTL ========================================================= */ - #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ - #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCAFCT ========================================================= */ - #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCALCF ========================================================= */ - #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ -/* ======================================================== CAPOAD ========================================================= */ - #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================== CAPRCR ========================================================= */ - #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ - #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ - #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CSAR ========================================================== */ - #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ - #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ - #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ - #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ -/* ======================================================== SRAMSAR ======================================================== */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ -/* ======================================================= STBRAMSAR ======================================================= */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DTCSAR ========================================================= */ - #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ - #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACSAR ======================================================== */ - #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ - #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARA ======================================================== */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ -/* ======================================================== ICUSARB ======================================================== */ - #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ - #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARC ======================================================== */ - #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ - #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ -/* ======================================================== ICUSARD ======================================================== */ - #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ - #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARE ======================================================== */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARF ======================================================== */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARG ======================================================== */ - #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARH ======================================================== */ - #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARI ======================================================== */ - #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARM ======================================================== */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARA ======================================================== */ - #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ - #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARB ======================================================== */ - #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ - #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARC ======================================================== */ - #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ - #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSPARC ======================================================== */ - #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ - #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MMPUSARA ======================================================== */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ -/* ======================================================= MMPUSARB ======================================================== */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGSAR ======================================================== */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DMACCHSAR ======================================================= */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ -/* ======================================================== CPUDSAR ======================================================== */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SRAMSABAR0 ======================================================= */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ====================================================== SRAMSABAR1 ======================================================= */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ======================================================== TEVTRCR ======================================================== */ - #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ - #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CADR ========================================================== */ - #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ - #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ - #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ - #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ - #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ - #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ - #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ - #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ - #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ - #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ - #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ - #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ - #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ - #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ - #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ - #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL1 ======================================================== */ - #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ - #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ - #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ - #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ - #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ - #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ - #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= STATB ========================================================= */ - #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ - #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= STATL ========================================================= */ - #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ - #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC0L ========================================================= */ - #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ - #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC1L ========================================================= */ - #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ - #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATB ========================================================== */ - #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ - #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMT ========================================================== */ - #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ - #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLL ========================================================= */ - #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ - #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLH ========================================================= */ - #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ - #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBL ========================================================= */ - #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ - #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBH ========================================================= */ - #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ - #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LL ========================================================= */ - #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ - #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LH ========================================================= */ - #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ - #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LL ========================================================= */ - #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ - #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LH ========================================================= */ - #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ - #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBL ========================================================= */ - #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ - #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBH ========================================================= */ - #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ - #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMP ========================================================== */ - #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ - #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CECEXMD ======================================================== */ - #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ - #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ - #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= CECEXMON ======================================================== */ - #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ - #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ - #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ -/* ========================================================= CTXD ========================================================== */ -/* ========================================================= CRXD ========================================================== */ -/* ========================================================= CECES ========================================================= */ - #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ - #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ - #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ - #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ - #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ - #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ - #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ - #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ -/* ========================================================= CECS ========================================================== */ - #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ - #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ - #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ - #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ - #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ - #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ - #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ -/* ========================================================= CECFC ========================================================= */ - #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ - #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ - #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ - #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ - #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ - #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ - #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ - #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL0 ======================================================== */ - #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ - #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ - #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ - #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ - #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ - #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ - #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ - #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DCR ========================================================== */ - #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ - #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ - #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ -/* ========================================================== DAR ========================================================== */ - #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ - #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ - #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ - #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ - #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= DCSR ========================================================== */ - #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ - #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ - #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ - #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ - #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ - #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ - #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ - #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ - #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ - #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ -/* ========================================================== DSR ========================================================== */ - #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ - #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ - #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ - #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ -/* ========================================================= MDTR ========================================================== */ - #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ - #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ - #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ - #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ - #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ - #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ -/* ========================================================= ACTR ========================================================== */ - #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ - #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ACAR ========================================================== */ - #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ - #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DRCSTR ========================================================= */ - #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ - #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ - #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ - #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ - #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ - #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ - #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ - #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ - #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ -/* ======================================================== DWCSTR ========================================================= */ - #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ - #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ - #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ - #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ - #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ - #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ - #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ - #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ - #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ - #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ - #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ -/* ========================================================= DCSTR ========================================================= */ - #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ - #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ - #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ - #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ -/* ========================================================= CDSR ========================================================== */ - #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ - #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ - #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ - #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ - #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ - #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ - #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ - #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ - #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ -/* ========================================================= MDLR ========================================================== */ - #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ - #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ - #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ - #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ - #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ -/* ========================================================= MRWCR ========================================================= */ - #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ - #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ - #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ - #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ - #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ -/* ======================================================== MRWCSR ========================================================= */ - #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ - #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ - #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ - #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ - #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ - #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ - #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ - #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ - #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ - #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ - #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ - #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ - #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ - #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ - #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ -/* ========================================================== ESR ========================================================== */ - #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ - #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ - #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ - #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ -/* ========================================================= CWNDR ========================================================= */ - #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ - #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CWDR ========================================================== */ - #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ - #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ - #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ - #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ - #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ -/* ========================================================== CRR ========================================================== */ - #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ - #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ - #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ - #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ - #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= ACSR ========================================================== */ - #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ - #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ - #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ -/* ======================================================== DCSMXR ========================================================= */ - #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ - #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ - #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ - #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== DWSCTSR ======================================================== */ - #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ - #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ - #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ - #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ - #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CFIFO ========================================================= */ - #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ - #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ - #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPEBUF ======================================================== */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================= PHYTRIM1 ======================================================== */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ -/* ======================================================= PHYTRIM2 ======================================================== */ - #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ - #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ - #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ - #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= EC710CTL ======================================================== */ - #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ - #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ - #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ - #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ - #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ - #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ - #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ - #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ -/* ======================================================= EC710TMC ======================================================== */ - #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ - #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ - #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ -/* ======================================================= EC710TED ======================================================== */ - #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ - #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= EC710EAD0 ======================================================= */ - #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ - #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCKMHZ ========================================================= */ - #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ - #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ - -/** @} */ /* End of group PosMask_peripherals */ - - #ifdef __cplusplus -} - #endif - -#endif /* R7FA6M5BH_H */ - -/** @} */ /* End of group R7FA6M5BH */ - -/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_cfg.h deleted file mode 100644 index 825f8cd32..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BOARD_CFG_H_ -#define BOARD_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - void bsp_init(void * p_args); - - #ifdef __cplusplus - } - #endif -#endif /* BOARD_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_sdram.h deleted file mode 100644 index 2d5eb7405..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/board_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BOARD_SDRAM_H -#define BOARD_SDRAM_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. - * It is only present if the new support has not been enabled. */ -#if 1 != BSP_CFG_SDRAM_ENABLED - #define bsp_sdram_init() R_BSP_SdramInit(true) -#endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_api.h deleted file mode 100644 index d912bc0ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_api.h +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_API_H -#define BSP_API_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* FSP Common Includes. */ -#include "fsp_common_api.h" - -/* Gets MCU configuration information. */ -#include "bsp_cfg.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic push - -/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. - * We are not modifying these files so we will ignore these warnings temporarily. */ - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" -#endif - -/* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_exceptions.h" -#include "vector_data.h" - -/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ -#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" -#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic pop -#endif - -#if defined(BSP_API_OVERRIDE) - #include BSP_API_OVERRIDE -#else - -/* BSP Common Includes. */ - #include "../../src/bsp/mcu/all/bsp_common.h" - -/* BSP MCU Specific Includes. */ - #include "../../src/bsp/mcu/all/bsp_register_protection.h" - #include "../../src/bsp/mcu/all/bsp_irq.h" - #include "../../src/bsp/mcu/all/bsp_io.h" - #include "../../src/bsp/mcu/all/bsp_group_irq.h" - #include "../../src/bsp/mcu/all/bsp_clocks.h" - #include "../../src/bsp/mcu/all/bsp_module_stop.h" - #include "../../src/bsp/mcu/all/bsp_security.h" - -/* Factory MCU information. */ - #include "../../inc/fsp_features.h" - -/* BSP Common Includes (Other than bsp_common.h) */ - #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" - - #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") - #include "../../src/bsp/mcu/all/internal/bsp_internal.h" - #endif - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_cfg.h deleted file mode 100644 index 8074418ad..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_cfg.h +++ /dev/null @@ -1,61 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - #include "bsp_clock_cfg.h" - #include "bsp_mcu_family_cfg.h" - #include "board_cfg.h" - #define RA_NOT_DEFINED 0 - #ifndef BSP_CFG_RTOS - #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else - #define BSP_CFG_RTOS (0) - #endif - #endif - #ifndef BSP_CFG_RTC_USED - #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) - #endif - #undef RA_NOT_DEFINED - #if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif - #define BSP_CFG_MCU_VCC_MV (3300) - #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0) - #define BSP_CFG_PARAM_CHECKING_ENABLE (0) - #define BSP_CFG_ASSERT (0) - - #define BSP_CFG_PFS_PROTECT ((1)) - - #define BSP_CFG_C_RUNTIME_INIT ((1)) - #define BSP_CFG_EARLY_INIT ((0)) - - #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED - #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - #endif - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE - #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE - #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS - #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - #endif - - #ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_clocks.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_clocks.h deleted file mode 100644 index f9c5fac41..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_clocks.h +++ /dev/null @@ -1,1727 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_CLOCKS_H -#define BSP_CLOCKS_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_clock_cfg.h" -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match SCKCR.CKSEL values. */ -#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. - #endif - #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. - #endif - #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. - #endif -#else - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ - #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. - #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. - -/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ - #define BSP_PRV_OSTC_OFFSET (0x7FU) - -#endif - -/* PLLs are not supported in the following scenarios: - * - When using low voltage mode - * - When using an MCU that does not have a PLL - * - When the PLL only accepts the main oscillator as a source and XTAL is not used - */ -#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) - #define BSP_PRV_PLL_SUPPORTED (1) - #if BSP_FEATURE_CGC_HAS_PLL2 - #define BSP_PRV_PLL2_SUPPORTED (1) - #else - #define BSP_PRV_PLL2_SUPPORTED (0) - #endif -#else - #define BSP_PRV_PLL_SUPPORTED (0) - #define BSP_PRV_PLL2_SUPPORTED (0) -#endif - -/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency - * calculated here is also used to initialize the g_clock_freq array. */ -#if BSP_PRV_PLL_SUPPORTED - #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ - (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif -#if BSP_PRV_PLL2_SUPPORTED - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif - -#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) - -/* Frequencies of clocks with fixed freqencies. */ -#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz -#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz - -#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #endif - #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ - (BSP_CFG_PLL_DIV + 1U)) - #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ - (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) - #endif -#endif - -/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ -#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) -#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) -#else - #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) -#endif - -#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) -#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) -#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) -#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) -#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) -#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) -#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) -#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) - -/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have - * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ -#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) -#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) -#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) -#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) -#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) -#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) -#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) -#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) -#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) -#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) - -/* System clock divider options. */ -#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. -#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. -#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. -#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. -#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. -#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. -#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. -#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). -#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. -#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. -#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. -#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. - -/* USB clock divider options. */ -#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 -#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 -#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 -#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 -#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 -#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 -#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 -#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 -#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 -#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 - -/* USB60 clock divider options. */ -#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 -#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 -#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 -#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 -#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 -#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 -#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 -#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 -#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 -#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 - -/* GLCD clock divider options. */ -#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 -#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 -#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 -#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 -#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 -#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 -#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 -#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 -#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 -#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 - -/* OCTA clock divider options. */ -#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 - -/* CANFD clock divider options. */ -#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 - -/* SCI clock divider options. */ -#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 -#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 -#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 -#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 -#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 -#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 -#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 -#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 -#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 -#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 - -/* SPI clock divider options. */ -#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 -#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 -#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 -#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 -#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 -#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 -#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 -#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 -#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 -#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 - -/* SCISPI clock divider options. */ -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 - -/* GPT clock divider options. */ -#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 -#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 -#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 -#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 -#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 -#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 -#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 -#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 -#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 -#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 - -/* IIC clock divider options. */ -#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 -#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 -#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 -#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 -#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 - -/* CEC clock divider options. */ -#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 -#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 - -/* I3C clock divider options. */ -#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 -#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 -#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 -#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 -#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 -#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 -#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 -#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 -#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 -#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 - -/* ADC clock divider options. */ -#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 -#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 -#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 -#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 -#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 -#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 -#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 -#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 -#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 -#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 - -/* SAU clock divider options. */ -#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 -#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 -#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 -#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 -#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 -#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 - -/* Extra peripheral 0 clock divider options. */ -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 - -/* PLL divider options. */ -#define BSP_CLOCKS_PLL_DIV_1 (0) -#define BSP_CLOCKS_PLL_DIV_2 (1) -#define BSP_CLOCKS_PLL_DIV_3 (2) -#define BSP_CLOCKS_PLL_DIV_4 (3) -#define BSP_CLOCKS_PLL_DIV_5 (4) -#define BSP_CLOCKS_PLL_DIV_6 (5) -#define BSP_CLOCKS_PLL_DIV_8 (7) -#define BSP_CLOCKS_PLL_DIV_9 (8) -#define BSP_CLOCKS_PLL_DIV_1_5 (9) -#define BSP_CLOCKS_PLL_DIV_16 (15) - -/* PLL multiplier options. */ -#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - -/* Offset from decimal multiplier to register value for PLLCCR type 4. */ - #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) - -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) - -#else - - #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U))) - -#endif - -/* Configuration option used to disable clock output. */ -#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) - -/* HOCO cycles per microsecond. */ -#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) - -/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ -#if BSP_HOCO_HZ < 48000000U - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) -#else - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) -#endif - -/* Create a mask of valid bits in SCKDIVCR. */ -#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) -#else - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) -#else - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) -#else - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) -#else - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB - #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) -#else - #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#else - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) -#else - #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) -#endif -#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ - BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ - BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ - BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) - -/* FLL is only used when enabled, present and the subclock is populated. */ -#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_PRV_HOCO_USE_FLL (1) - #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US - #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) - #endif -#else - #define BSP_PRV_HOCO_USE_FLL (0) - #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) -#endif - -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR - #define BSP_PRV_RTC_RESET_DELAY_US (200) -#endif - -/* Operating power control modes. */ -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed -#else - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed - #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed -#endif -#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -typedef struct -{ - uint32_t pll_freq; -} bsp_clock_up2025-07-28_callback_args_t; - - #if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_up2025-07-28_callback_t)(bsp_clock_up2025-07-28_callback_args_t * - p_callback_args); - #elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_up2025-07-28_callback_t)(bsp_clock_up2025-07-28_callback_args_t * - p_callback_args); - #endif - -#endif - -/** PLL multiplier values */ -typedef enum e_cgc_pll_mul -{ - CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 - CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 - CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 - CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 - CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 - CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 - CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 - CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 - CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 - CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 - CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 - CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 - CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 - CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 - CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 - CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 - CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 - CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 - CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 - CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 - CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 - CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 - CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 - CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 - CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 - CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 - CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 - CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 - CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 - CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 - CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 - CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 - CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 - CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 - CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 - CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 - CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 - CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 - CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 - CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 - CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 - CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 - CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 - CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 - CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 - CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 - CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 - CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 - CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 - CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 - CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 - CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 - CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 - CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 - CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 - CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 - CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 - CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 - CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 - CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 - CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 - CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 - CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 - CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 - CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 - CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 - CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 - CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 - CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 - CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 - CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 - CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 - CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 - CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 - CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 - CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 - CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 - CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 - CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 - CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 - CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 - CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 - CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 - CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 - CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 - CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 - CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 - CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 - CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 - CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 - CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 - CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 - CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 - CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 - CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 - CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 - CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 - CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 - CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 - CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 - CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 - CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 - CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 - CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 - CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 - CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 - CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 - CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 - CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 - CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 - CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 - CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 - CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 - CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 - CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 - CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 - CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 - CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 - CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 - CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 - CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 - CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 - CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 - CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 - CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 - CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 - CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 - CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 - CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 - CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 - CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 - CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 - CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 - CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 - CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 - CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 - CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 - CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 - CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 - CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 - CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 - CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 - CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 - CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 - CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 - CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 - CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 - CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 - CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 - CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 - CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 - CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 - CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 - CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 - CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 - CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 - CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 - CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 - CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 - CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 - CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 - CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 - CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 - CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 - CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 - CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 - CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 - CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 - CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 - CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 - CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 - CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 - CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 - CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 - CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 - CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 - CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 - CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 - CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 - CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 - CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 - CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 - CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 - CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 - CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 - CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 - CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 - CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 - CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 - CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 - CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 - CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 - CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 - CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 - CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 - CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 - CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 - CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 - CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 - CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 - CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 - CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 - CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 - CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 - CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 - CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 - CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 - CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 - CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 - CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 - CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 - CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 - CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 - CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 - CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 - CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 - CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 - CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 - CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 - CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 - CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 - CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 - CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 - CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 - CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 - CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 - CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 - CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 - CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 - CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 - CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 - CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 - CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 - CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 - CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 - CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 - CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 - CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 - CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 - CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 - CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 - CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 - CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 - CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 - CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 - CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 - CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 - CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 - CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 - CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 - CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 - CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 - CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 - CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 - CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 - CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 - CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 - CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 - CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 - CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 - CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 - CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 - CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 - CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 - CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 - CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 - CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 - CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 - CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 - CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 - CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 - CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 - CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 - CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 - CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 - CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 - CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 - CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 - CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 - CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 - CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 - CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 - CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 - CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 - CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 - CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 - CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 - CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 - CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 - CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 - CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 - CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 - CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 - CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 - CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 - CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 - CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 - CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 - CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 - CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 - CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 - CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 - CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 - CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 - CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 - CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 - CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 - CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 - CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 - CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 - CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 - CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 - CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 - CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 - CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 - CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 - CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 - CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 - CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 - CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 - CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 - CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 - CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 - CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 - CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 - CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 - CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 - CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 - CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 - CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 - CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 - CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 - CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 - CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 - CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 - CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 - CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 - CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 - CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 - CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 - CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 - CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 - CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 - CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 - CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 - CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 - CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 - CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 - CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 - CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 - CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 - CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 - CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 - CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 - CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 - CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 - CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 - CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 - CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 - CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 - CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 - CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 - CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 - CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 - CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 - CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 - CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 - CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 - CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 - CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 - CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 - CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 - CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 - CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 - CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 - CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 - CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 - CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 - CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 - CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 - CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 - CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 - CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 - CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 - CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 - CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 - CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 - CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 - CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 - CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 - CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 - CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 - CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 - CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 - CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 - CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 - CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 - CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 - CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 - CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 - CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 - CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 - CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 - CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 - CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 - CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 - CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 - CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 - CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 - CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 - CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 - CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 - CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 - CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 - CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 - CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 - CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 - CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 - CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 - CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 - CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 - CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 - CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 - CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 - CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 - CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 - CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 - CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 - CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 - CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 - CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 - CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 - CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 - CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 - CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 - CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 - CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 - CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 - CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 - CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 - CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 - CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 - CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 - CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 - CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 - CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 - CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 - CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 - CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 - CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 - CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 - CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 - CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 - CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 - CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 - CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 - CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 - CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 - CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 - CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 - CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 - CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 - CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 - CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 - CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 - CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 - CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 - CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 - CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 - CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 - CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 - CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 - CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 - CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 - CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 - CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 - CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 - CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 - CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 - CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 - CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 - CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 - CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 - CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 - CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 - CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 - CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 - CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 - CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 - CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 - CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 - CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 - CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 - CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 - CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 - CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 - CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 - CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 - CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 - CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 - CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 - CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 - CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 - CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 - CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 - CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 - CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 - CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 - CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 - CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 - CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 - CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 - CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 - CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 - CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 - CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 - CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 - CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 - CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 - CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 - CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 - CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 - CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 - CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 - CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 - CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 - CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 - CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 - CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 - CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 - CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 - CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 - CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 - CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 - CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 - CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 - CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 - CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 - CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 - CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 - CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 - CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 - CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 - CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 - CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 - CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 - CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 - CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 - CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 - CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 - CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 - CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 - CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 - CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 - CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 - CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 - CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 - CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 - CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 - CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 - CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 - CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 - CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 - CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 - CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 - CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 - CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 - CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 - CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 - CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 - CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 - CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 - CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 - CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 - CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 - CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 - CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 - CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 - CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 - CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 - CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 - CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 - CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 - CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 - CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 - CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 - CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 - CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 - CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 - CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 - CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 - CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 - CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 - CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 - CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 - CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 - CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 - CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 - CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 - CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 - CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 - CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 - CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 - CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 - CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 - CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 - CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 - CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 - CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 - CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 - CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 - CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 - CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 - CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 - CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 - CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 - CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 - CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 - CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 - CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 - CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 - CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 - CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 - CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 - CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 - CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 - CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 - CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 - CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 - CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 - CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 - CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 - CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 - CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 - CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 - CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 - CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 - CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 - CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 - CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 - CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 - CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 - CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 - CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 - CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 - CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 - CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 - CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 - CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 - CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 - CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 - CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 - CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 - CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 - CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 - CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 - CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 - CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 - CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 - CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 - CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 - CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 - CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 - CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 - CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 - CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 - CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 - CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 - CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 - CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 - CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 - CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 - CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 - CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 - CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 - CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 - CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 - CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 - CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 - CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 - CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 - CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 - CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 - CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 - CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 - CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 - CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 - CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 - CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 - CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 - CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 - CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 - CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 - CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 - CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 - CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 - CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 - CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 - CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 - CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 - CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 - CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 - CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 - CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 - CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 - CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 - CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 - CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 - CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 - CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 - CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 - CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 - CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 - CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 - CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 - CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 - CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 - CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 - CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 - CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 - CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 - CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 - CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 - CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 - CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 - CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 - CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 - CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 - CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 - CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 - CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 - CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 - CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 - CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 - CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 - CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 - CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 - CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 - CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 - CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 - CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 - CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 - CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 - CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 - CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 - CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 - CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 - CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 - CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 - CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 - CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 - CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 - CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 - CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 - CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 - CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 - CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 - CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 - CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 - CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 - CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 - CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 - CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 - CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 - CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 - CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 - CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 - CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 - CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 - CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 - CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 - CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 - CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 - CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 - CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 - CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 - CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 - CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 - CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 - CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 - CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 - CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 - CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 - CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 - CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 - CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 - CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 - CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 - CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 - CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 - CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 - CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 - CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 - CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 - CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 - CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 - CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 - CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 - CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 - CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 - CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 - CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 - CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 - CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 - CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 - CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 - CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 - CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 - CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 - CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 - CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 - CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 - CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 - CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 - CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 - CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 - CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 - CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 - CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 - CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 - CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 - CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 - CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 - CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 - CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 - CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 - CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 - CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 - CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 - CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 - CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 - CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 - CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 - CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 - CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 - CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 - CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 - CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 - CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 - CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 - CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 - CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 - CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 - CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 - CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 - CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 - CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 - CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 - CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 - CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 - CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 - CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 - CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 - CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 - CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 - CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 - CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 - CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 - CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 - CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 - CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 - CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 - CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 - CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 - CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 - CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 - CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 - CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 - CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 - CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 - CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 - CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 - CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 - CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 - CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 - CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 - CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 - CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 - CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 - CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 - CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 - CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 - CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 - CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 - CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 - CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 - CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 - CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 - CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 - CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 - CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 - CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 - CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 - CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 - CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 - CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 - CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 - CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 - CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 - CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 - CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 - CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 - CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 - CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 - CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 - CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 - CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 - CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 - CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 - CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 - CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 - CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 - CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 - CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 - CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 - CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 - CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 - CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 - CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 - CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 - CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 - CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 - CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 - CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 - CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 - CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 - CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 - CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 - CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 - CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 - CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 - CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 - CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 - CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 - CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 - CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 - CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 - CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 - CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 - CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 - CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 - CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 - CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 - CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 - CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 - CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 - CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 - CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 - CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 - CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 - CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 - CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 - CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 - CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 - CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 - CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 - CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 - CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 - CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 - CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 - CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 - CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 - CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 - CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 - CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 - CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 - CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 - CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 - CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 - CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 - CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 - CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 - CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 - CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 - CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 - CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 - CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 - CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 - CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 - CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 - CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 - CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 - CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 - CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 - CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 - CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 - CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 - CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 - CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 - CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 - CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 - CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 - CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 - CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 - CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 - CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 - CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 - CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 - CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 - CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 - CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 - CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 - CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 - CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 - CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 - CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 - CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 - CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 - CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 - CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 - CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 - CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 - CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 - CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 - CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 - CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 - CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 - CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 - CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 - CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 - CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 - CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 - CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 - CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 - CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 - CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 - CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 - CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 - CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 - CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 - CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 - CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 - CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 - CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 - CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 - CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 - CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 - CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 - CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 - CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 - CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 - CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 - CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 - CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 - CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 - CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 - CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 - CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 - CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 - CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 - CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 - CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 - CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 - CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 - CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 - CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 - CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 - CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 - CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 - CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 - CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 - CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 - CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 - CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 - CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 - CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 - CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 - CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 - CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 - CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 - CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 - CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 - CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 - CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 - CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 - CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 - CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 - CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 - CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 - CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 - CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 - CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 - CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 - CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 - CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 - CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 - CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 - CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 - CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 - CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 - CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 - CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 - CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 - CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 - CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 - CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 - CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 - CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 - CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 - CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 - CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 - CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 - CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 - CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 - CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 - CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 - CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 - CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 - CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 - CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 - CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 - CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 - CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 - CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 - CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 - CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 - CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 - CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 - CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 - CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 - CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 - CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 - CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 - CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 - CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 - CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 - CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 - CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 - CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 - CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 - CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 - CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 - CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 - CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 - CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 - CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 - CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 - CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 - CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 - CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 - CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 - CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 - CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 - CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 - CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 - CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 -} cgc_pll_mul_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_clock_init(void); // Used internally by BSP - -#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD -void bsp_clock_freq_var_init(void); // Used internally by BSP - -#endif - -#if BSP_TZ_SECURE_BUILD -void r_bsp_clock_up2025-07-28_callback_set(bsp_clock_up2025-07-28_callback_t p_callback, - bsp_clock_up2025-07-28_callback_args_t * p_callback_memory); - -#endif - -/* Used internally by CGC */ - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE -void bsp_prv_operating_mode_set(uint8_t operating_mode); - -#endif - -#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED -uint32_t bsp_prv_power_change_mstp_set(void); -void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); - -#endif - -void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); - -#if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); - -#else -void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); -uint32_t bsp_prv_clock_source_get(void); - -#endif - -/* RTC Initialization */ -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR -void R_BSP_Init_RTC(void); - -#endif - -#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE -bool bsp_prv_rtc_register_clock_set(bool enable); - -#endif - -#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE -bool bsp_prv_clock_prepare_pre_sleep(void); -void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); - -#endif - -/* The public function is used to get state or initialize the sub-clock. */ -#if BSP_FEATURE_RTC_IS_IRTC -fsp_err_t R_BSP_SubclockStatusGet(); -fsp_err_t R_BSP_SubclockInitialize(); - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_common.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_common.h deleted file mode 100644 index f796e2a93..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_common.h +++ /dev/null @@ -1,623 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_COMMON_H -#define BSP_COMMON_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include -#include - -/* Different compiler support. */ -#include "../../inc/api/fsp_common_api.h" -#include "bsp_compiler_support.h" - -/* BSP TFU Includes. */ -#include "../../src/bsp/mcu/all/bsp_tfu.h" - -#include "../../src/bsp/mcu/all/bsp_sdram.h" - -/* BSP MMF Includes. */ -#include "../../src/bsp/mcu/all/bsp_mmf.h" - -#include "bsp_cfg.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** Used to signify that an ELC event is not able to be used as an interrupt. */ -#define BSP_IRQ_DISABLED (0xFFU) - -/* Version of this module's code and API. */ - -#if 1 == BSP_CFG_RTOS /* ThreadX */ - #include "tx_user.h" - #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) - #include "tx_port.h" - #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); - #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); - #else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE - #endif -#else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE -#endif - -/** Macro that can be defined in order to enable logging in FSP modules. */ -#ifndef FSP_LOG_PRINT - #define FSP_LOG_PRINT(X) -#endif - -/** Macro to log and return error without an assertion. */ -#ifndef FSP_RETURN - - #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ - return err; -#endif - -/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in - * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ -#if (1 == BSP_CFG_ASSERT) - - #ifndef FSP_ERROR_LOG - #define FSP_ERROR_LOG(err) \ - fsp_error_log((err), __FILE__, __LINE__); - #endif -#else - - #define FSP_ERROR_LOG(err) -#endif - -/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP - * functions. */ -#if (3 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) -#elif (2 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) {assert(a);} -#else - #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) -#endif // ifndef FSP_ASSERT - -/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used - * to identify runtime errors in FSP functions. */ - -#define FSP_ERROR_RETURN(a, err) \ - { \ - if ((a)) \ - { \ - (void) 0; /* Do nothing */ \ - } \ - else \ - { \ - FSP_ERROR_LOG(err); \ - return err; \ - } \ - } - -/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register up2025-07-28s. - * This macro can be redefined to add a timeout if necessary. */ -#ifndef FSP_HARDWARE_REGISTER_WAIT - #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} -#endif - -#ifndef FSP_REGISTER_READ - -/* Read a register and discard the result. */ - #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); -#endif - -/**************************************************************** - * - * This check is performed to select suitable ASM API with respect to core - * - * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so - * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ - -#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) - #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) - #endif -#else - #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #endif - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) -#endif - -/* This macro defines a variable for saving previous mask value */ -#ifndef FSP_CRITICAL_SECTION_DEFINE - - #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U -#endif - -/* These macros abstract methods to save and restore the interrupt state for different architectures. */ -#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK - #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) -#else - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI - #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ - (8U - __NVIC_PRIO_BITS))) -#endif - -/** This macro temporarily saves the current interrupt state and disables interrupts. */ -#ifndef FSP_CRITICAL_SECTION_ENTER - #define FSP_CRITICAL_SECTION_ENTER \ - old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ - FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) -#endif - -/** This macro restores the previously saved interrupt state, reenabling interrupts. */ -#ifndef FSP_CRITICAL_SECTION_EXIT - #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) -#endif - -/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ -#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) - -/** Used to signify that the requested IRQ vector is not defined in this system. */ -#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) - -/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ -#if (BSP_CFG_MCU_PART_SERIES == 8) - #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) -#else - #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) -#endif - -/* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE - #define FSP_PRIV_TZ_USE_SECURE_REGS (1) -#else - #define FSP_PRIV_TZ_USE_SECURE_REGS (0) -#endif - -/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ -#if BSP_CFG_EARLY_INIT - #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) -#else - #define BSP_SECTION_EARLY_INIT -#endif - -#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 -BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); - -#endif - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/* - * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register - * from the secure application using the provided non-secure callable functions. - */ - #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) - #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) - #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) -#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/*******************************************************************************************************************//** - * Read a non-secure 8-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) -{ - p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 16-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) -{ - p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 32-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) -{ - p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/* - * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register - * using the non-secure aliased address. - */ - #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) - #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) - #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) -#else - #define FSP_STYPE3_REG8_READ(X, S) (X) - #define FSP_STYPE3_REG16_READ(X, S) (X) - #define FSP_STYPE3_REG32_READ(X, S) (X) -#endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Different warm start entry locations in the BSP. */ -typedef enum e_bsp_warm_start_event -{ - BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. - BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. - BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up -} bsp_warm_start_event_t; - -/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ -typedef enum e_fsp_priv_clock -{ - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_PCLKE = 20, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, - FSP_PRIV_CLOCK_CPUCLK = 32, -} fsp_priv_clock_t; - -/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ -typedef enum e_fsp_priv_source_clock -{ - FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator - FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator - FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator - FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator - FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator - FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output - FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output - FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output - FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output - FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output - FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output - FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output - FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output -} fsp_priv_source_clock_t; - -typedef struct st_bsp_unique_id -{ - union - { - uint32_t unique_id_words[4]; - uint8_t unique_id_bytes[16]; - }; -} bsp_unique_id_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); - -/*********************************************************************************************************************** - * Global variables (defined in other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Return active interrupt vector number value - * - * @return Active interrupt vector number value - **********************************************************************************************************************/ -__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) -{ - xPSR_Type xpsr_value; - xpsr_value.w = __get_xPSR(); - - return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); -} - -/*******************************************************************************************************************//** - * Gets the frequency of a system clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) -{ -#if !BSP_FEATURE_CGC_REGISTER_SET_B - uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; - - #if BSP_FEATURE_CGC_HAS_CPUCLK - if (FSP_PRIV_CLOCK_CPUCLK == clock) - { - return SystemCoreClock; - } - - /* Get CPUCLK divisor */ - uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; - - /* Determine if either divisor is a multiple of 3 */ - if ((cpuclk_div | clock_div) & 8U) - { - /* Convert divisor settings to their actual values */ - cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); - clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); - - /* Calculate clock with multiplication and division instead of shifting */ - return (SystemCoreClock * cpuclk_div) / clock_div; - } - else - { - return (SystemCoreClock << cpuclk_div) >> clock_div; - } - - #else - uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; - - return (SystemCoreClock << iclk_div) >> clock_div; - #endif -#else - FSP_PARAMETER_NOT_USED(clock); - - return SystemCoreClock; -#endif -} - -/*******************************************************************************************************************//** - * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). - * - * @return Clock Divider - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) -{ - if (2U >= ckdivcr) - { - - /* clock_div: - * - Clock Divided by 1: 0 - * - Clock Divided by 2: 1 - * - Clock Divided by 4: 2 - */ - return 1U << ckdivcr; - } - else if (3U == ckdivcr) - { - - /* Clock Divided by 6 */ - return 6U; - } - else if (4U == ckdivcr) - { - - /* Clock Divided by 8 */ - return 8U; - } - else if (5U == ckdivcr) - { - - /* Clock Divided by 3 */ - return 3U; - } - else if (6U == ckdivcr) - { - - /* Clock Divided by 5 */ - return 5; - } - else if (7U == ckdivcr) - { - - /* Clock Divided by 10 */ - return 10; - } - else - { - /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ - } - - /* Clock Divided by 16 */ - return 16U; -} - -#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI/SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) -{ - uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; - uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; - - return R_BSP_SourceClockHzGet(scispicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) -{ - uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = - (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> - R_SYSTEM_SPICKCR_CKSEL_Pos); - - return R_BSP_SourceClockHzGet(spicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SCI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) -{ - uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = - (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> - R_SYSTEM_SCICKCR_SCICKSEL_Pos); - - return R_BSP_SourceClockHzGet(scicksel) / clock_div; -} - -#endif - -/*******************************************************************************************************************//** - * Get unique ID for this device. - * - * @return A pointer to the unique identifier structure - **********************************************************************************************************************/ -__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) -{ -#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 - - return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); -#else - - return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; -#endif -} - -/*******************************************************************************************************************//** - * Disables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheDisable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 - - /* Writeback and flush cache when disabling - * MREF_INTERNAL_12 */ - if (R_CACHE->CCAWTA_b.WT) - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; - } - else - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; - } - - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #else - - /* Disable the C-Cache. */ - R_CACHE->CCACTL = 0U; - #endif -#endif -} - -/*******************************************************************************************************************//** - * Enables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheEnable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invali2025-07-28 the flash cache and wait until it is invali2025-07-28d. (See section 55.3.2.2 "Operation" of the Flash Cache - * in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 - - /* Configure the C-Cache line size. */ - R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; - #else - - /* Check that no flush or writeback are ongoing before enabling - * MREF_INTERNAL_13 */ - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #endif - - /* Enable the C-Cache. */ - R_CACHE->CCACTL = 1U; -#endif -} - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -#if (1 == BSP_CFG_ASSERT) - -/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ -void fsp_error_log(fsp_err_t err, const char * file, int32_t line); - -#endif - -/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will - * alert the user of the error. The user can override this default behavior by defining their own - * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. - */ -#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) - - #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_compiler_support.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_compiler_support.h deleted file mode 100644 index 39f752c3c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_compiler_support.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_COMPILER_SUPPORT_H - #define BSP_COMPILER_SUPPORT_H - - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - #include "arm_cmse.h" - #endif - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - #if defined(__ARMCC_VERSION) /* AC6 compiler */ - -/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load - * memory (ROM) is reserved unnecessarily. */ - #define BSP_UNINIT_SECTION_PREFIX ".bss" - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__GNUC__) /* GCC compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__ICCARM__) /* IAR compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP "HEAP" - #endif - #define BSP_DONT_REMOVE __root - #define BSP_ATTRIBUTE_STACKLESS __stackless - #define BSP_FORCE_INLINE _Pragma("inline=forced") - #endif - - #ifndef BSP_SECTION_STACK - #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" - #endif - #ifndef BSP_SECTION_FLASH_GAP - #define BSP_SECTION_FLASH_GAP - #endif - #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" - #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - #define BSP_SECTION_ROM_REGISTERS ".rom_registers" - #define BSP_SECTION_ID_CODE ".id_code" - -/* Compiler neutral macros. */ - #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - - #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) - - #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED - - #define BSP_WEAK_REFERENCE __attribute__((weak)) - -/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ - #define BSP_STACK_ALIGNMENT (8) - -/*********************************************************************************************************************** - * TrustZone definitions - **********************************************************************************************************************/ - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) - #if defined(__ICCARM__) /* IAR compiler */ - #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call - #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry - #else - #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) - #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) - #endif - #else - #define BSP_CMSE_NONSECURE_CALL - #define BSP_CMSE_NONSECURE_ENTRY - #endif - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/** @} (end of addtogroup BSP_MCU) */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_delay.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_delay.h deleted file mode 100644 index 94a13ccff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_delay.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_DELAY_H -#define BSP_DELAY_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "bsp_compiler_support.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The number of cycles required per software delay loop. */ -#ifndef BSP_DELAY_LOOP_CYCLES - #if defined(RENESAS_CORTEX_M85) - -/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for - * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in - * this case. */ - #if defined(__ICCARM__) - #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) - #else - #define BSP_DELAY_LOOP_CYCLES (1) - #endif - #else - #define BSP_DELAY_LOOP_CYCLES (4) - #endif -#endif - -/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle - * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures - * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count - * of 0. */ -#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) - -/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ -typedef enum -{ - BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds - BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds - BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds -} bsp_delay_units_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_elc.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_elc.h deleted file mode 100644 index 9a2207791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_elc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_ELC_H -#define BSP_ELC_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU_RA6M5 - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* UNCRUSTIFY-OFF */ - -/** Sources of event signals to be linked to other peripherals or the CPU - * @note This list is device specific. - * */ -typedef enum e_elc_event_ra6m5 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end - ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end - ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end - ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end - ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end - ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete - ELC_EVENT_DTC_END = (0x02A), // DTC transfer end - ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode - ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt - ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt - ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry - ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B - ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt - ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A - ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B - ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt - ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A - ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B - ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt - ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A - ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B - ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt - ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A - ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt - ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt - ELC_EVENT_CAN_GLERR = (0x05A), // Global error - ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 - ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 - ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 - ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 - ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 - ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 - ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 - ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 - ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt - ELC_EVENT_CAN0_CHERR = (0x064), // Channel error - ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt - ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request - ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt - ELC_EVENT_CAN1_CHERR = (0x068), // Channel error - ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt - ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request - ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x073), // Receive data full - ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x075), // Transmit end - ELC_EVENT_IIC0_ERI = (0x076), // Transfer error - ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x078), // Receive data full - ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x080), // Transfer error - ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request - ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full - ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt - ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt - ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt - ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow - ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow - ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow - ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow - ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch - ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt - ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x180), // Receive data full - ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x182), // Transmit end - ELC_EVENT_SCI0_ERI = (0x183), // Receive error - ELC_EVENT_SCI0_AM = (0x184), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x186), // Receive data full - ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x188), // Transmit end - ELC_EVENT_SCI1_ERI = (0x189), // Receive error - ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI2_ERI = (0x18F), // Receive error - ELC_EVENT_SCI3_RXI = (0x192), // Receive data full - ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x194), // Transmit end - ELC_EVENT_SCI3_ERI = (0x195), // Receive error - ELC_EVENT_SCI3_AM = (0x196), // Address match event - ELC_EVENT_SCI4_RXI = (0x198), // Receive data full - ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI4_ERI = (0x19B), // Receive error - ELC_EVENT_SCI4_AM = (0x19C), // Address match event - ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI5_AM = (0x1A2), // Address match event - ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI6_AM = (0x1A8), // Address match event - ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI7_AM = (0x1AE), // Address match event - ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error - ELC_EVENT_SCI8_AM = (0x1B4), // Address match event - ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error - ELC_EVENT_SCI9_AM = (0x1BA), // Address match event - ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle - ELC_EVENT_SPI0_ERI = (0x1C7), // Error - ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle - ELC_EVENT_SPI1_ERI = (0x1CC), // Error - ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event - ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error - ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error - ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error - ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt - ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt - ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt -} elc_event_t; - -#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) - -#define ELC_PERIPHERAL_NUM (19U) -#define BSP_OVERRIDE_ELC_PERIPHERAL_T -/** Possible peripherals to be linked to event signals - * @note This list is device specific. - * */ -typedef enum e_elc_peripheral -{ - ELC_PERIPHERAL_GPT_A = (0), - ELC_PERIPHERAL_GPT_B = (1), - ELC_PERIPHERAL_GPT_C = (2), - ELC_PERIPHERAL_GPT_D = (3), - ELC_PERIPHERAL_GPT_E = (4), - ELC_PERIPHERAL_GPT_F = (5), - ELC_PERIPHERAL_GPT_G = (6), - ELC_PERIPHERAL_GPT_H = (7), - ELC_PERIPHERAL_ADC0 = (8), - ELC_PERIPHERAL_ADC0_B = (9), - ELC_PERIPHERAL_ADC1 = (10), - ELC_PERIPHERAL_ADC1_B = (11), - ELC_PERIPHERAL_DAC0 = (12), - ELC_PERIPHERAL_DAC1 = (13), - ELC_PERIPHERAL_IOPORT1 = (14), - ELC_PERIPHERAL_IOPORT2 = (15), - ELC_PERIPHERAL_IOPORT3 = (16), - ELC_PERIPHERAL_IOPORT4 = (17), - ELC_PERIPHERAL_CTSU = (18) -} elc_peripheral_t; - -/** Positions of event link set registers (ELSRs) available on this MCU */ -#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) - -/* UNCRUSTIFY-ON */ -/** @} (end addtogroup BSP_MCU_RA6M5) */ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_exceptions.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_exceptions.h deleted file mode 100644 index f388be329..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_exceptions.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_EXCEPTIONS_H - #define BSP_EXCEPTIONS_H - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ -typedef enum IRQn -{ - Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ -} IRQn_Type; - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_feature.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_feature.h deleted file mode 100644 index 29f6b43f1..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_feature.h +++ /dev/null @@ -1,588 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_FEATURE_H -#define BSP_FEATURE_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "bsp_peripheral.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ -#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) -#if (BSP_CFG_XTAL_HZ >= (20000000)) - #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (16000000)) - #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (8000000)) - #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#else - #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#endif - -// *UNCRUSTIFY-OFF* - -#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. -#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. -#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0xFFFFUL) // Create the mask for the valid calibration data provided by TSCDR. -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. -#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FFUL) // Mask of available channels in ADC unit 0. -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007UL) // Mask of available channels in ADC unit 1. -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. - -#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. -#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. -#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. -#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. - -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. -#define BSP_FEATURE_BSP_FLASH_CACHE (1UL) // Flash cache is present. -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. -#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. -#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1UL) // Indicates there is a separate clock for the CEC. -#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. -#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. -#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. -#define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. -#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. -#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. -#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0UL) // Indicates there is a separate clock for the I3C. -#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. -#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. -#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. -#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. -#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. -#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. -#define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. -#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. -#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. -#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. -#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. -#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. -#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. -#define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. -#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. -#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. -#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. -#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. -#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. -#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. -#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. -#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. -#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. -#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. - -#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. -#define BSP_FEATURE_CANFD_LITE (0UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. -#define BSP_FEATURE_CANFD_NUM_CHANNELS (2UL) // Number of CANFD channels per CANFD peripheral instance. -#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. - -#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. -#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. -#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. -#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. -#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. -#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. -#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. -#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. -#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. -#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. -#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. -#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. -#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. -#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. -#define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. -#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. -#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. -#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. -#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000UL) // Maximum input frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. -#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. -#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000UL) // PLL VCO maximum frequency. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. -#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. -#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. -#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. -#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. - -#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. -#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. -#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. - -#define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA (1UL) // RSA support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1UL) // RSA support with key-wrapping is available. - -#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. -#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. - -#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. -#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. -#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. -#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. -#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. - -#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) -#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. - -#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. -#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. - -#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. - -#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. - -#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. - -#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. - -#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. - -#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1UL) // Number of available ethernet PHYs. -#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. - -#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. -#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. -#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. -#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. -#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. -#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. -#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). -#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). -#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. - -#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. -#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. -#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. - -#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x03FFUL) // Mask of channels that support event count input (has GTUPSR register). -#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. -#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. -#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x03FFUL) // Mask of channels that support dead time control. -#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. -#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. -#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. - -#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. -#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. -#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. -#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. -#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. -#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. -#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. -#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FF0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. - -#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. - -#define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. -#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. - -#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. -#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. - -#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. -#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. -#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. -#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. -#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. -#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. -#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. -#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. -#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. -#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. - -#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. -#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. -#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. -#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. -#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. -#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. -#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. -#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. - -#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. - -#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000UL) // Start address of the CS0 memory mapped region for OSPI. -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000UL) // Start address of the CS1 memory mapped region for OSPI. - -#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. -#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. - -#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. - -#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. -#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. -#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RISP_E11A. -#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. -#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. -#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. -#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. -#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. -#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. -#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. -#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. - -#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. -#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. -#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. -#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. -#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. -#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. - -#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x03F9UL) // Mask of channels with data compare match (DCCR) available. -#define BSP_FEATURE_SCI_CHANNELS (0x03FFUL) // Mask of available SCI channels. -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. -#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. -#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x06UL) // Mask of channels that can support LIN. -#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x06UL) // List of channels that do not support ABCSE functionality. -#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9UL) // Mask of channels which support CTS external pins. -#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x03F9UL) // Mask of channels which support the UART FIFO. -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. -#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. - -#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. - -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. - -#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. - -#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. -#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. -#define BSP_FEATURE_SPI_MAX_CHANNEL (2UL) // Number of available SPI channels. -#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. - -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. - -#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. - -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. - -#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. - -#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. - -#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) -#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. -#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. -#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. - -#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) -#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. -#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. - -#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) -#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. -#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. -#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. -#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. -#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. -#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. -#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. -#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. -#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. -#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_group_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_group_irq.h deleted file mode 100644 index 5aede0736..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_group_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GROUP_IRQ_H -#define BSP_GROUP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#ifndef BSP_OVERRIDE_GROUP_IRQ_T - -/** Which interrupts can have callbacks registered. */ -typedef enum e_bsp_grp_irq -{ - BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred - BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred - BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt - BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt - BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt - BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected - BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt - BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error - BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error - BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error - BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error - BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error - BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error - BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error -} bsp_grp_irq_t; - -#endif - -/* Callback type. */ -typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_group_interrupt_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_guard.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_guard.h deleted file mode 100644 index dd63bb41a..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_guard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GUARD_H -#define BSP_GUARD_H - -#include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUp2025-07-28CallbackSet(bsp_clock_up2025-07-28_callback_t p_callback, - bsp_clock_up2025-07-28_callback_args_t * p_callback_memory); - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_io.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_io.h deleted file mode 100644 index 418c75380..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_io.h +++ /dev/null @@ -1,465 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @defgroup BSP_IO BSP I/O access - * @ingroup RENESAS_COMMON - * @brief This module provides basic read/write access to port pins. - * - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_IO_H -#define BSP_IO_H - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) -#define BSP_IO_PRV_8BIT_MASK (0xFF) -#define BSP_IO_PWPR_B0WI_OFFSET (7U) -#define BSP_IO_PWPR_PFSWE_OFFSET (6U) -#define BSP_IO_PFS_PDR_OUTPUT (4U) -#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Levels that can be set and read for individual pins */ -typedef enum e_bsp_io_level -{ - BSP_IO_LEVEL_LOW = 0, ///< Low - BSP_IO_LEVEL_HIGH ///< High -} bsp_io_level_t; - -/** Direction of individual pins */ -typedef enum e_bsp_io_dir -{ - BSP_IO_DIRECTION_INPUT = 0, ///< Input - BSP_IO_DIRECTION_OUTPUT ///< Output -} bsp_io_direction_t; - -/** Superset list of all possible IO ports. */ -typedef enum e_bsp_io_port -{ - BSP_IO_PORT_00 = 0x0000, ///< IO port 0 - BSP_IO_PORT_01 = 0x0100, ///< IO port 1 - BSP_IO_PORT_02 = 0x0200, ///< IO port 2 - BSP_IO_PORT_03 = 0x0300, ///< IO port 3 - BSP_IO_PORT_04 = 0x0400, ///< IO port 4 - BSP_IO_PORT_05 = 0x0500, ///< IO port 5 - BSP_IO_PORT_06 = 0x0600, ///< IO port 6 - BSP_IO_PORT_07 = 0x0700, ///< IO port 7 - BSP_IO_PORT_08 = 0x0800, ///< IO port 8 - BSP_IO_PORT_09 = 0x0900, ///< IO port 9 - BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 - BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 - BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 - BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 - BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 -} bsp_io_port_t; - -/** Superset list of all possible IO port pins. */ -typedef enum e_bsp_io_port_pin_t -{ - BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 - BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port -} bsp_io_port_pin_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern volatile uint32_t g_protect_pfswe_counter; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Read the current input level of the pin. - * - * @param[in] pin The pin - * - * @retval Current input level - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) -{ - /* Read pin level. */ - return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; -} - -/*******************************************************************************************************************//** - * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS - * protection using R_BSP_PinAccessEnable() before calling this function. - * - * @param[in] pin The pin - * @param[in] level The level - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) -{ - /* Clear PMR, ASEL, ISEL and PODR bits. */ - uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; - pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; - - /* Set output level and pin direction to output. */ - uint32_t lvl = ((uint32_t) level | pfs_bits); -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); -#endif -} - -/*******************************************************************************************************************//** - * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling - * this function. - * - * @param[in] pin The pin - * @param[in] cfg Configuration for the pin (PmnPFS register setting) - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) -{ - /* Configure a pin. */ -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; -#endif -} - -/*******************************************************************************************************************//** - * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur - * via multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessEnable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** If this is first entry then allow writing of PFS. */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #endif - } - - /** Increment the protect counter */ - g_protect_pfswe_counter++; - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/*******************************************************************************************************************//** - * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via - * multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessDisable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** Is it safe to disable PFS register? */ - if (0 != g_protect_pfswe_counter) - { - /* Decrement the protect counter */ - g_protect_pfswe_counter--; - } - - /** Is it safe to disable writing of PFS? */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled - #endif - } - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/** @} (end addtogroup BSP_IO) */ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_irq.h deleted file mode 100644 index ad971f32e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_irq.h +++ /dev/null @@ -1,238 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_IRQ_H -#define BSP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @brief Sets the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @param[in] p_context ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - gp_renesas_isr_context[irq] = p_context; -} - -/*******************************************************************************************************************//** - * @brief Finds the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @return ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - return gp_renesas_isr_context[irq]; -} - -#if BSP_CFG_INLINE_IRQ_FUNCTIONS - - #if BSP_FEATURE_ICU_HAS_IELSR - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit - * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) -{ - /* Clear the IR bit in the selected IELSR register. */ - R_ICU->IELSR_b[irq].IR = 0U; - - /* Read back the IELSR register to ensure that the IR bit is cleared. - * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ - FSP_REGISTER_READ(R_ICU->IELSR[irq]); -} - - #endif - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) -{ - #if BSP_FEATURE_ICU_HAS_IELSR - - /* Clear the IR bit in the selected IELSR register. */ - R_BSP_IrqStatusClear(irq); - - /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ - __DMB(); - #endif - - /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context. - * - * @param[in] irq The IRQ to configure. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions - * every time a priority is configured in the NVIC. */ - #if (4U == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (33 == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (23 == __CORTEX_M) - NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); - #else - NVIC_SetPriority(irq, priority); - #endif - - /* Store the context. The context is recovered in the ISR. */ - R_FSP_IsrContextSet(irq, p_context); -} - -/*******************************************************************************************************************//** - * Enable the IRQ in the NVIC (Without clearing the pending bit). - * - * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex - * Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) -{ - /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions - * every time an interrupt is enabled in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - - __COMPILER_BARRIER(); - NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - __COMPILER_BARRIER(); -} - -/*******************************************************************************************************************//** - * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed - * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) -{ - /* Clear pending interrupts in the ICU and NVIC. */ - R_BSP_IrqClearPending(irq); - - /* Enable the IRQ in the NVIC. */ - R_BSP_IrqEnableNoClear(irq); -} - -/*******************************************************************************************************************//** - * Disables interrupts in the NVIC. - * - * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) -{ - /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - - __DSB(); - __ISB(); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. - * - * @param[in] irq Interrupt number. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - R_BSP_IrqCfg(irq, priority, p_context); - R_BSP_IrqEnable(irq); -} - -#else - #if BSP_FEATURE_ICU_HAS_IELSR -void R_BSP_IrqStatusClear(IRQn_Type irq); - - #endif -void R_BSP_IrqClearPending(IRQn_Type irq); -void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); -void R_BSP_IrqEnableNoClear(IRQn_Type const irq); -void R_BSP_IrqEnable(IRQn_Type const irq); -void R_BSP_IrqDisable(IRQn_Type const irq); -void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); - -#endif - -/*******************************************************************************************************************//** - * @internal - * @addtogroup BSP_MCU_PRV Internal BSP Documentation - * @ingroup RENESAS_INTERNAL - * @{ - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_irq_cfg(void); // Used internally by BSP - -/** @} (end addtogroup BSP_MCU_PRV) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_macl.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_macl.h deleted file mode 100644 index 416228d5c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_macl.h +++ /dev/null @@ -1,164 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_MACL -#define RENESAS_MACL - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include -#include "bsp_api.h" - -#if BSP_FEATURE_MACL_SUPPORTED - #if __has_include("arm_math_types.h") - -/* Ignore certain math warnings in ARM CMSIS DSP headers */ - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wsign-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" - #elif defined(__GNUC__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wfloat-conversion" - #endif - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_suppress=Pe223 - #endif - - #include "arm_math_types.h" - #include "dsp/basic_math_functions.h" - #include "dsp/matrix_functions.h" - #include "dsp/filtering_functions.h" - #include "dsp/support_functions.h" - #include "dsp/fast_math_functions.h" - - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_default=Pe223 - #endif - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - #pragma GCC diagnostic pop - #endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MACL - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Common macro used by MACL */ - #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) - #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) - - #define BSP_MACL_SHIFT_SIGN (0x80) - #define BSP_MACL_SHIFT_1_BIT (1U) - #define BSP_MACL_SHIFT_30_BIT (30U) - #define BSP_MACL_SHIFT_31_BIT (31U) - #define BSP_MACL_SHIFT_32_BIT (32U) - - #define BSP_MACL_32_BIT (32U) - - #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 - #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 - - #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 - #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 - - #define BSP_MACL_CLEAR_MULR_REG (0x0U) - - #define BSP_MACL_POSITIVE_NUM (0U) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, - const arm_matrix_instance_q31 * p_src_b, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); -void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, - q31_t scale_fract, - int32_t shift, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); -void R_BSP_MaclConvQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); -arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst, - uint32_t first_idx, - uint32_t num_points); - -void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); - -void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - q31_t * p_scratch_in, - uint32_t block_size); - -void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); - -/******************************************************************************************************************//** - * @} (end addtogroup BSP_MACL) - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - - #endif -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_api.h deleted file mode 100644 index 74624f7ff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_api.h +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MCU_API_H -#define BSP_MCU_API_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -typedef struct st_bsp_event_info -{ - IRQn_Type irq; - elc_event_t event; -} bsp_event_info_t; - -typedef enum e_bsp_clocks_octaclk_div -{ - BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 - BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 - BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 - BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 - BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 - BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 - BSP_CLOCKS_OCTACLK_DIV_5 ///< Divide OCTA source clock by 5 -} bsp_clocks_octaclk_div_t; - -typedef enum e_bsp_clocks_source -{ - BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. - BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. - BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. - BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. - BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. - BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. - BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. -} bsp_clocks_source_t; - -typedef struct st_bsp_octaclk_settings -{ - bsp_clocks_source_t source_clock; ///< OCTACLK source clock - bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider -} bsp_octaclk_settings_t; - -void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); -void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); -fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); -void R_BSP_OctaclkUp2025-07-28(bsp_octaclk_settings_t * p_octaclk_setting); -void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_pn_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 11295843b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5AH3CFP - #define BSP_MCU_FEATURE_SET ('A') - #define BSP_ROM_SIZE_BYTES (2097152) - #define BSP_RAM_SIZE_BYTES (524288) - #define BSP_DATA_FLASH_SIZE_BYTES (8192) - #define BSP_PACKAGE_LQFP - #define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_family_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_family_cfg.h deleted file mode 100644 index a4c302306..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,394 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - - #include "bsp_mcu_device_pn_cfg.h" - #include "bsp_mcu_device_cfg.h" - #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" - #include "bsp_clock_cfg.h" - #define BSP_MCU_GROUP_RA6M5 (1) - #define BSP_LOCO_HZ (32768) - #define BSP_MOCO_HZ (8000000) - #define BSP_SUB_CLOCK_HZ (32768) - #if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (16000000) - #elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - - #define BSP_CFG_FLL_ENABLE (0) - - #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) - #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) - - #if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (0) - #endif - - /* TrustZone Settings */ - #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) - #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) - #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - - /* CMSIS TrustZone Settings */ - #define SCB_CSR_AIRCR_INIT (1) - #define SCB_AIRCR_BFHFNMINS_VAL (0) - #define SCB_AIRCR_SYSRESETREQS_VAL (1) - #define SCB_AIRCR_PRIS_VAL (0) - #define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL - #define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL - #define FPU_FPCCR_TS_VAL (1U) -#endif - #define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL - #define FPU_FPCCR_CLRONRET_VAL (1) -#endif - - /* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE - #define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - - /* Type 1 Peripheral Security Attribution */ - - /* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - - /* Type 2 Peripheral Security Attribution */ - - /* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR - /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ -#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) -#define BSP_TZ_CFG_LVDSAR (0U) -#else -#define BSP_TZ_CFG_LVDSAR (3U) -#endif -#endif - - /* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif - /* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - - /* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFE0E402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - - /* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - - /* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - - /* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - - /* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - - /* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - - /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED - #define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - - /* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - - /* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ - #define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - - /* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR - #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - - /* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA - /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ - #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - - /* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA - #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif - /* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB - #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - - /* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK - #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - - - #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) - #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) - #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) - #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) - #define OFS_SEQ5 (1 << 28) | (1 << 30) - #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - - /* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) -#else - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - - #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - - /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ - #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - - /* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL - #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - - /* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 - #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif - /* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 - #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif - /* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 - #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif - /* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 - #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif - /* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 - #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif - /* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 - #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif - /* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 - #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif - /* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 - #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif - /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 - #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif - /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 - #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif - /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 - #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif - /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 - #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif - /* Security Attribution for Bank Select Register */ -#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL - #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT - #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_info.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_info.h deleted file mode 100644 index 53c1844b3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mcu_info.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup BSP_MCU - * @defgroup BSP_MCU_RA6M5 RA6M5 - * @includedoc config_bsp_ra6m5_fsp.html - * @{ - **********************************************************************************************************************/ - -/** @} (end defgroup BSP_MCU_RA6M5) */ - -#ifndef BSP_MCU_INFO_H -#define BSP_MCU_INFO_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* BSP MCU Specific Includes. */ -#include "bsp_elc.h" -#include "bsp_feature.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -typedef elc_event_t bsp_interrupt_event_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mmf.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mmf.h deleted file mode 100644 index 9b7f1b143..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_mmf.h +++ /dev/null @@ -1,141 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MMF_H -#define BSP_MMF_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MEMORY_MIRROR_REG_KEY (0xDBU) -#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes -#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) - -/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ -#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Enum for state of Memory Mirror Function. */ -typedef enum e_mmf_state -{ - MEMORY_MIRROR_DISABLED = 0, - MEMORY_MIRROR_ENABLED = 1, -} mmf_state_t; - -/** Status instance of Memory Mirror Function. */ -typedef struct st_mmf_status -{ - mmf_state_t mmf_state; // Current state of Memory Mirror Region. - uint32_t mmf_cur_addr; // Current address in register MMSFR. -} mmf_status_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Get the current status of Memory Mirror. - * - * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. - * - * @retval FSP_SUCCESS MMF status retrieved successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. - * - * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that variable for storing the status of MMF was provided. */ - if (NULL == p_mmf_status) - { - return FSP_ERR_ASSERTION; - } - #endif - - p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; - p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_mmf_status); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/*******************************************************************************************************************//** - * Set address for MMF region. - * - * @param[in] addr Address of memory region to be mirrored into MMF region. - * - * @retval FSP_SUCCESS Address is set successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. - * - * This function sets the memory address to be mirrored by MMF. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that requested address is in supported range and must align with 128 */ - if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) - { - return FSP_ERR_INVALID_ADDRESS; - } - #endif - - /* If MMF is enabled, disable MMF before updating the address register. - * For disabling MMF, write 0xDB00 to register MMEN. */ - if (1U == R_MMF->MMEN_b.EN) - { - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); - } - - R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); - - /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into - * MMF region. */ - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(addr); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif - -/** @} (end addtogroup BSP_MCU) */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_module_stop.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_module_stop.h deleted file mode 100644 index d7312cbe8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_module_stop.h +++ /dev/null @@ -1,371 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MODULE_H -#define BSP_MODULE_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* MSTPCRA is located in R_MSTP for Star devices. */ - #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) -#else - -/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ - #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) -#endif - -/*******************************************************************************************************************//** - * Cancels the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= \ - (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/*******************************************************************************************************************//** - * Enables the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/** @} (end addtogroup BSP_MCU) */ - -#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) - #else - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - - #if BSP_MCU_GROUP_RA2A2 - -/* RA2A2 has a combination of AGT and AGTW. - * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) - * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) - * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) - * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) - */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + \ - BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); - - #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #else - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t -#else - #if (2U == BSP_FEATURE_ELC_VERSION) - #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #elif BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ - (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - \ - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #endif -#endif - -#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); - -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t - -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t -#else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#if BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); -#else - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#endif -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t -#if (BSP_PERIPHERAL_DAC8_PRESENT) - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t -#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_pin_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_pin_cfg.h deleted file mode 100644 index cd4206fbf..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_pin_cfg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_PIN_CFG_H_ -#define BSP_PIN_CFG_H_ -#include "r_ioport.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - - -extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5AH3CFP.pincfg */ - -void BSP_PinConfigSecurityInit(); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif /* BSP_PIN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_register_protection.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_register_protection.h deleted file mode 100644 index ca4b64c20..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_register_protection.h +++ /dev/null @@ -1,60 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_REGISTER_PROTECTION_H -#define BSP_REGISTER_PROTECTION_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/** The different types of registers that can be protected. */ -typedef enum e_bsp_reg_protect -{ - /** Enables writing to the registers related to the clock generation circuit. */ - BSP_REG_PROTECT_CGC = 0, - - /** Enables writing to the registers related to operating modes, low power consumption, and battery backup - * function. */ - BSP_REG_PROTECT_OM_LPC_BATT, - - /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, - * LVD2CR1, LVD2SR. */ - BSP_REG_PROTECT_LVD, - - /** Enables writing to the registers related to the security function. */ - BSP_REG_PROTECT_SAR, -} bsp_reg_protect_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_register_protect_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_sdram.h deleted file mode 100644 index 5ba56a638..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SDRAM_H -#define BSP_SDRAM_H - -#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_SdramInit(bool init_memory); -void R_BSP_SdramSelfRefreshEnable(void); -void R_BSP_SdramSelfRefreshDisable(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_security.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_security.h deleted file mode 100644 index 3ceb51f92..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_security.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SECURITY_H -#define BSP_SECURITY_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_NonSecureEnter(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_tfu.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_tfu.h deleted file mode 100644 index 98b09caee..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/bsp_tfu.h +++ /dev/null @@ -1,218 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_TFU -#define RENESAS_TFU - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* Mathematical Functions includes. */ -#ifdef __cplusplus - #include -#else - #include -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TFU_SUPPORTED - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - - #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f - - #ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) - -/* No form of inline is available, it happens only when -std=c89, gnu89 and - * above are OK */ - #warning \ - "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ - -/* gnu89 semantics of inline and extern inline are essentially the exact - * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) - #endif - #endif - #elif __ICCARM__ - #define BSP_TFU_INLINE - #else - #error "Compiler not supported!" - #endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Calculates sine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Sine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __sinf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - return R_TFU->SCDT1; -} - -/*******************************************************************************************************************//** - * Calculates cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __cosf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read cos from R_TFU->SCDT1 */ - return R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates sine and cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * @param[out] sin Sine value of an angle. - * @param[out] cos Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - *sin = R_TFU->SCDT1; - - /* Read sin from R_TFU->SCDT1 */ - *cos = R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-Axis cordinate value. - * @param[in] x_cord X-Axis cordinate value. - * - * @retval Arc tangent for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) -{ - /* Set X-cordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-cordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - return R_TFU->ATDT1; -} - -/*******************************************************************************************************************//** - * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * - * @retval Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * @param[out] atan2 Arc tangent for given values. - * @param[out] hypot Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - *atan2 = R_TFU->ATDT1; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - - #if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) - #endif - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif /* RENESAS_TFU */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_common_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_common_api.h deleted file mode 100644 index 12c7933a7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_common_api.h +++ /dev/null @@ -1,380 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_COMMON_API_H -#define FSP_COMMON_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include -#include - -/* Includes FSP version macros. */ -#include "fsp_version.h" - -/*******************************************************************************************************************//** - * @ingroup RENESAS_COMMON - * @defgroup RENESAS_ERROR_CODES Common Error Codes - * All FSP modules share these common error codes. - * @{ - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing - * about using this implementation is that it does not take any extra RAM or ROM. */ - -#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) - -/** Determine if a C++ compiler is being used. - * If so, ensure that standard C is used to process the API information. */ -#if defined(__cplusplus) - #define FSP_CPP_HEADER extern "C" { - #define FSP_CPP_FOOTER } -#else - #define FSP_CPP_HEADER - #define FSP_CPP_FOOTER -#endif - -/** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically - * defined on the Secure side. */ -#define FSP_SECURE_ARGUMENT (NULL) - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Common error codes */ -typedef enum e_fsp_err -{ - FSP_SUCCESS = 0, - - FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed - FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location - FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter - FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist - FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode - FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API - FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open - FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy - FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h - FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked - FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP - FSP_ERR_OVERFLOW = 12, ///< Hardware overflow - FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow - FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration - FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result - FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason - FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met - FSP_ERR_ABORTED = 18, ///< An operation was aborted - FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled - FSP_ERR_TIMEOUT = 20, ///< Timeout error - FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied - FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied - FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation - FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed - FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed - FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made - FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition - FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU - FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state - FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed - FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed - FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete - FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found - FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback - FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer - FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed - - /* Start of RTOS only error codes */ - FSP_ERR_INTERNAL = 100, ///< Internal error - FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted - - /* Start of UART specific */ - FSP_ERR_FRAMING = 200, ///< Framing error occurs - FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects - FSP_ERR_PARITY = 202, ///< Parity error occurs - FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow - FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue - FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer - FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer - - /* Start of SPI specific */ - FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. - FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. - FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. - FSP_ERR_SPI_PARITY = 303, ///< Parity error. - FSP_ERR_OVERRUN = 304, ///< Overrun error. - - /* Start of CGC Specific */ - FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. - FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. - FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off - FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off - FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled - FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set - FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active - FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit - FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled - FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out - FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode - - /* Start of FLASH Specific */ - FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. - FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state - FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz - FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory - FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed - - /* Start of CAC Specific */ - FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate - - /* Start of IIRFA Specific */ - FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. - - /* Start of GLCD Specific */ - FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock - FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter - FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter - FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found - FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter - FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer - FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register up2025-07-28 - FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry - FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting - FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter - - /* Start of JPEG Specific */ - FSP_ERR_JPEG_ERR = 1100, ///< JPEG error - FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. - FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. - FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. - FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. - FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. - FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. - FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. - FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. - FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. - FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) - FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. - FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. - FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. - FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. - FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough - FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU - - /* Start of touch panel framework specific */ - FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed - - /* Start of IIRFA specific */ - FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected - FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected - - /* Start of IP specific */ - FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device - FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device - FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device - - /* Start of USB specific */ - FSP_ERR_USB_FAILED = 1500, - FSP_ERR_USB_BUSY = 1501, - FSP_ERR_USB_SIZE_SHORT = 1502, - FSP_ERR_USB_SIZE_OVER = 1503, - FSP_ERR_USB_NOT_OPEN = 1504, - FSP_ERR_USB_NOT_SUSPEND = 1505, - FSP_ERR_USB_PARAMETER = 1506, - - /* Start of Message framework specific */ - FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool - FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool - FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid - FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid - FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many - FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found - FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue - FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue - FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal - FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released - - /* Start of 2DG Driver specific */ - FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering - FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering - - /* Start of ETHER Driver specific */ - FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. - FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation - FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled - FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty - FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable - FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication - FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. - - /* Start of ETHER_PHY Driver specific */ - FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. - FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation - - /* Start of BYTEQ library specific */ - FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data - FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue - - /* Start of CTSU Driver specific */ - FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. - FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. - FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. - FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. - FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. - FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. - FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. - FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. - FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. - FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. - FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. - FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. - FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. - FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. - FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. - FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. - - /* Start of SDMMC specific */ - FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. - FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. - FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. - FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. - FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. - FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. - FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. - - /* Start of FX_IO specific */ - FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. - FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. - - /* Start of CAN specific */ - FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. - FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. - FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. - FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. - FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. - FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. - FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. - FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. - - /* Start of SF_WIFI Specific */ - FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. - FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. - FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed - FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode - FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. - FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. - FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point - FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error - FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter - FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value - FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result - FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured - FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure - FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure - FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error - - /* Start of SF_CELLULAR Specific */ - FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. - FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. - FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed - FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is upto2025-07-28 - FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed - FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. - FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. - FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed - - /* Start of SF_BLE specific */ - FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed - FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed - FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed - FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled - FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled - - /* Start of SF_BLE_ABS specific */ - FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. - FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. - - /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ - FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function - FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy - FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty - FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index - FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry - FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed - FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened - FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized - FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred - FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter - FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented - FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified - FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred - FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid - FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state - FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened - FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. - FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher - FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input 2025-07-28 is illegal. - FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. - - /* Start of Crypto RSIP specific (0x10100) */ - FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy - FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return - FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error - FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal - FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed - - /* Start of SF_CRYPTO specific */ - FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened - FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error - FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key - FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold - FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. - FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. - FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. - - /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. - * Refer to sf_cryoto_err.h for Crypto error codes. - */ - - /* Start of Sensor specific */ - FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. - FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. - FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. - - /* Start of COMMS specific */ - FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. -} fsp_err_t; - -/** @} */ - -/*********************************************************************************************************************** - * Function prototypes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_features.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_features.h deleted file mode 100644 index dd54197d7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_features.h +++ /dev/null @@ -1,297 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_FEATURES_H -#define FSP_FEATURES_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include - -/* Different compiler support. */ -#include "fsp_common_api.h" -#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Available modules. */ -typedef enum e_fsp_ip -{ - FSP_IP_CFLASH = 0, ///< Code Flash - FSP_IP_DFLASH = 1, ///< Data Flash - FSP_IP_RAM = 2, ///< RAM - FSP_IP_LVD = 3, ///< Low Voltage Detection - FSP_IP_CGC = 3, ///< Clock Generation Circuit - FSP_IP_LPM = 3, ///< Low Power Modes - FSP_IP_FCU = 4, ///< Flash Control Unit - FSP_IP_ICU = 6, ///< Interrupt Control Unit - FSP_IP_DMAC = 7, ///< DMA Controller - FSP_IP_DTC = 8, ///< Data Transfer Controller - FSP_IP_IOPORT = 9, ///< I/O Ports - FSP_IP_PFS = 10, ///< Pin Function Select - FSP_IP_ELC = 11, ///< Event Link Controller - FSP_IP_MPU = 13, ///< Memory Protection Unit - FSP_IP_MSTP = 14, ///< Module Stop - FSP_IP_MMF = 15, ///< Memory Mirror Function - FSP_IP_KEY = 16, ///< Key Interrupt Function - FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit - FSP_IP_DOC = 18, ///< Data Operation Circuit - FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator - FSP_IP_SCI = 20, ///< Serial Communications Interface - FSP_IP_IIC = 21, ///< I2C Bus Interface - FSP_IP_SPI = 22, ///< Serial Peripheral Interface - FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit - FSP_IP_SCE = 24, ///< Secure Cryptographic Engine - FSP_IP_SLCDC = 25, ///< Segment LCD Controller - FSP_IP_AES = 26, ///< Advanced Encryption Standard - FSP_IP_TRNG = 27, ///< True Random Number Generator - FSP_IP_FCACHE = 30, ///< Flash Cache - FSP_IP_SRAM = 31, ///< SRAM - FSP_IP_ADC = 32, ///< A/D Converter - FSP_IP_DAC = 33, ///< 12-Bit D/A Converter - FSP_IP_TSN = 34, ///< Temperature Sensor - FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit - FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator - FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator - FSP_IP_OPAMP = 38, ///< Operational Amplifier - FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter - FSP_IP_RTC = 40, ///< Real Time Clock - FSP_IP_WDT = 41, ///< Watch Dog Timer - FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer - FSP_IP_GPT = 43, ///< General PWM Timer - FSP_IP_POEG = 44, ///< Port Output Enable for GPT - FSP_IP_OPS = 45, ///< Output Phase Switch - FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer - FSP_IP_CAN = 48, ///< Controller Area Network - FSP_IP_IRDA = 49, ///< Infrared Data Association - FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface - FSP_IP_USBFS = 51, ///< USB Full Speed - FSP_IP_SDHI = 52, ///< SD/MMC Host Interface - FSP_IP_SRC = 53, ///< Sampling Rate Converter - FSP_IP_SSI = 54, ///< Serial Sound Interface - FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface - FSP_IP_ETHER = 64, ///< Ethernet MAC Controller - FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller - FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller - FSP_IP_PDC = 66, ///< Parallel Data Capture Unit - FSP_IP_GLCDC = 67, ///< Graphics LCD Controller - FSP_IP_DRW = 68, ///< 2D Drawing Engine - FSP_IP_JPEG = 69, ///< JPEG - FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter - FSP_IP_USBHS = 71, ///< USB High Speed - FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface - FSP_IP_CEC = 73, ///< HDMI CEC - FSP_IP_TFU = 74, ///< Trigonometric Function Unit - FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator - FSP_IP_CANFD = 76, ///< CAN-FD - FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT - FSP_IP_SAU = 78, ///< Serial Array Unit - FSP_IP_IICA = 79, ///< Serial Interface IICA - FSP_IP_UARTA = 80, ///< Serial Interface UARTA - FSP_IP_TAU = 81, ///< Timer Array Unit - FSP_IP_TML = 82, ///< 32-bit Interval Timer - FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator - FSP_IP_USBCC = 84, ///< USB Type-C Controller -} fsp_ip_t; - -/** Signals that can be mapped to an interrupt. */ -typedef enum e_fsp_signal -{ - FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH - FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH - FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END - FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B - FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A - FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B - FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ - FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ - FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A - FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B - FSP_SIGNAL_AGT_INT, ///< AGT INT - FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR - FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END - FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW - FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR - FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX - FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX - FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX - FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX - FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP - FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST - FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 - FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 - FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD - FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT - FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT - FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT - FSP_SIGNAL_CTSU_END = 0, ///< CTSU END - FSP_SIGNAL_CTSU_READ, ///< CTSU READ - FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE - FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI - FSP_SIGNAL_DALI_CLI, ///< DALI CLI - FSP_SIGNAL_DALI_SDI, ///< DALI SDI - FSP_SIGNAL_DALI_BPI, ///< DALI BPI - FSP_SIGNAL_DALI_FEI, ///< DALI FEI - FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI - FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT - FSP_SIGNAL_DOC_INT = 0, ///< DOC INT - FSP_SIGNAL_DRW_INT = 0, ///< DRW INT - FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE - FSP_SIGNAL_DTC_END, ///< DTC END - FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT - FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 - FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 - FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS - FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT - FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT - FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL - FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE - FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL - FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE - FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL - FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE - FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL - FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE - FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL - FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE - FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL - FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE - FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR - FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI - FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT - FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 - FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 - FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A - FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B - FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C - FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D - FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E - FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F - FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW - FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW - FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A - FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B - FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE - FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 - FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 - FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 - FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 - FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 - FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 - FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 - FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 - FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 - FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 - FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 - FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 - FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 - FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 - FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 - FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 - FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL - FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI - FSP_SIGNAL_IIC_RXI, ///< IIC RXI - FSP_SIGNAL_IIC_TEI, ///< IIC TEI - FSP_SIGNAL_IIC_TXI, ///< IIC TXI - FSP_SIGNAL_IIC_WUI, ///< IIC WUI - FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 - FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 - FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 - FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 - FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B - FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C - FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D - FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E - FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW - FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI - FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI - FSP_SIGNAL_KEY_INT = 0, ///< KEY INT - FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END - FSP_SIGNAL_PDC_INT, ///< PDC INT - FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY - FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT - FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT - FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM - FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD - FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY - FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY - FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY - FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG - FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY - FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 - FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 - FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK - FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY - FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 - FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 - FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 - FSP_SIGNAL_SCI_AM = 0, ///< SCI AM - FSP_SIGNAL_SCI_ERI, ///< SCI ERI - FSP_SIGNAL_SCI_RXI, ///< SCI RXI - FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI - FSP_SIGNAL_SCI_TEI, ///< SCI TEI - FSP_SIGNAL_SCI_TXI, ///< SCI TXI - FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI - FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND - FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND - FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS - FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD - FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ - FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO - FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI - FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE - FSP_SIGNAL_SPI_RXI, ///< SPI RXI - FSP_SIGNAL_SPI_TEI, ///< SPI TEI - FSP_SIGNAL_SPI_TXI, ///< SPI TXI - FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END - FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY - FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL - FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW - FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW - FSP_SIGNAL_SSI_INT = 0, ///< SSI INT - FSP_SIGNAL_SSI_RXI, ///< SSI RXI - FSP_SIGNAL_SSI_TXI, ///< SSI TXI - FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI - FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ - FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 - FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 - FSP_SIGNAL_USB_INT, ///< USB INT - FSP_SIGNAL_USB_RESUME, ///< USB RESUME - FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW - FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A - FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B - FSP_SIGNAL_ULPT_INT, ///< ULPT INT -} fsp_signal_t; - -typedef void (* fsp_vector_t)(void); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_version.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_version.h deleted file mode 100644 index 54b5c25ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/fsp_version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_VERSION_H - #define FSP_VERSION_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ - #include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup RENESAS_COMMON - * @{ - **********************************************************************************************************************/ - - #ifdef __cplusplus -extern "C" { - #endif - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** FSP pack major version. */ - #define FSP_VERSION_MAJOR (5U) - -/** FSP pack minor version. */ - #define FSP_VERSION_MINOR (8U) - -/** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) - -/** FSP pack version build number (currently unused). */ - #define FSP_VERSION_BUILD (0U) - -/** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.8.0") - -/** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.8.0") - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** FSP Pack version structure */ -typedef union st_fsp_pack_version -{ - /** Version id */ - uint32_t version_id; - - /** - * Code version parameters, little endian order. - */ - struct version_id_b_s - { - uint8_t build; ///< Build version of FSP Pack - uint8_t patch; ///< Patch version of FSP Pack - uint8_t minor; ///< Minor version of FSP Pack - uint8_t major; ///< Major version of FSP Pack - } version_id_b; -} fsp_pack_version_t; - -/** @} */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/instance/r_ioport.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/instance/r_ioport.h deleted file mode 100644 index 14abb229e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/instance/r_ioport.h +++ /dev/null @@ -1,522 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup IOPORT - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_H -#define R_IOPORT_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "r_ioport_api.h" -#if __has_include("r_ioport_cfg.h") - #include "r_ioport_cfg.h" -#endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ -typedef struct st_ioport_instance_ctrl -{ - uint32_t open; - void const * p_context; -} ioport_instance_ctrl_t; - -/* This typedef is here temporarily. See SWFLEX-144 for details. */ -/** Superset list of all possible IO port pins. */ -typedef enum e_ioport_port_pin_t -{ - IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 -} ioport_port_pin_t; - -#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #endif - - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an UARTA peripheral pin */ - IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; -#endif - -#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; -#endif - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const ioport_api_t g_ioport_on_ioport; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ - -fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); -fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); -fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); -fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); -fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); -fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); -fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t direction_values, - ioport_size_t mask); -fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); -fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t event_data, - ioport_size_t mask_value); -fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); -fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_IOPORT_H diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/periph/bsp_peripheral.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/periph/bsp_peripheral.h deleted file mode 100644 index bcaaf823c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/periph/bsp_peripheral.h +++ /dev/null @@ -1,211 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_PERIPHERAL_H -#define BSP_PERIPHERAL_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -// *UNCRUSTIFY-OFF* - -#define BSP_PERIPHERAL_ACMP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_PRESENT (1) -#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ADC_B_PRESENT (0) -#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_D_PRESENT (0) -#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AGT_PRESENT (1) -#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) -#define BSP_PERIPHERAL_AGTW_PRESENT (0) -#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AMI_PRESENT (0) -#define BSP_PERIPHERAL_ANALOG_PRESENT (1) -#define BSP_PERIPHERAL_BUS_PRESENT (1) -#define BSP_PERIPHERAL_CAC_PRESENT (1) -#define BSP_PERIPHERAL_CACHE_PRESENT (1) -#define BSP_PERIPHERAL_CAN_PRESENT (0) -#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_CANFD_PRESENT (1) -#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_CEC_PRESENT (1) -#define BSP_PERIPHERAL_CEU_PRESENT (0) -#define BSP_PERIPHERAL_CGC_PRESENT (1) -#define BSP_PERIPHERAL_CPSCU_PRESENT (1) -#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) -#define BSP_PERIPHERAL_CRC_PRESENT (1) -#define BSP_PERIPHERAL_CTSU_PRESENT (1) -#define BSP_PERIPHERAL_DAC_PRESENT (1) -#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DAC_B_PRESENT (0) -#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC8_PRESENT (0) -#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC12_PRESENT (1) -#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DEBUG_PRESENT (1) -#define BSP_PERIPHERAL_DMA_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) -#define BSP_PERIPHERAL_DOC_PRESENT (1) -#define BSP_PERIPHERAL_DOC_B_PRESENT (0) -#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) -#define BSP_PERIPHERAL_DRW_PRESENT (0) -#define BSP_PERIPHERAL_DSILINK_PRESENT (0) -#define BSP_PERIPHERAL_DTC_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ECCMB_PRESENT (1) -#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ELC_PRESENT (1) -#define BSP_PERIPHERAL_ELC_B_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_FACI_PRESENT (1) -#define BSP_PERIPHERAL_FCACHE_PRESENT (1) -#define BSP_PERIPHERAL_FLAD_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) -#define BSP_PERIPHERAL_GLCDC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_PRESENT (1) -#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) -#define BSP_PERIPHERAL_I3C_PRESENT (0) -#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ICU_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) -#define BSP_PERIPHERAL_IIC_PRESENT (1) -#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) -#define BSP_PERIPHERAL_IIC_B_PRESENT (0) -#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) -#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) -#define BSP_PERIPHERAL_IICA_PRESENT (0) -#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IPC_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_PRESENT (0) -#define BSP_PERIPHERAL_IRTC_PRESENT (0) -#define BSP_PERIPHERAL_IWDT_PRESENT (1) -#define BSP_PERIPHERAL_JPEG_PRESENT (0) -#define BSP_PERIPHERAL_KINT_PRESENT (0) -#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_MACL_PRESENT (0) -#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) -#define BSP_PERIPHERAL_MMF_PRESENT (0) -#define BSP_PERIPHERAL_MPU_PRESENT (1) -#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_MRMS_PRESENT (0) -#define BSP_PERIPHERAL_MRRGE_PRESENT (0) -#define BSP_PERIPHERAL_MSTP_PRESENT (1) -#define BSP_PERIPHERAL_OCD_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_OSPI_PRESENT (1) -#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) -#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) -#define BSP_PERIPHERAL_PDC_PRESENT (0) -#define BSP_PERIPHERAL_PFS_PRESENT (1) -#define BSP_PERIPHERAL_PFS_B_PRESENT (0) -#define BSP_PERIPHERAL_PMISC_PRESENT (0) -#define BSP_PERIPHERAL_PORGA_PRESENT (0) -#define BSP_PERIPHERAL_PORT_PRESENT (1) -#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) -#define BSP_PERIPHERAL_PSCU_PRESENT (1) -#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) -#define BSP_PERIPHERAL_QSPI_PRESENT (1) -#define BSP_PERIPHERAL_RADIO_PRESENT (0) -#define BSP_PERIPHERAL_RSIP_PRESENT (1) -#define BSP_PERIPHERAL_RTC_PRESENT (1) -#define BSP_PERIPHERAL_RTC_C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_PRESENT (0) -#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) -#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) -#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SCI_PRESENT (1) -#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_SCI_B_PRESENT (0) -#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDHI_PRESENT (1) -#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SLCDC_PRESENT (0) -#define BSP_PERIPHERAL_SPI_PRESENT (1) -#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_SPI_B_PRESENT (0) -#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SPMON_PRESENT (0) -#define BSP_PERIPHERAL_SRAM_PRESENT (1) -#define BSP_PERIPHERAL_SRC_PRESENT (0) -#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) -#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) -#define BSP_PERIPHERAL_TAU_PRESENT (0) -#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TFU_PRESENT (0) -#define BSP_PERIPHERAL_TML_PRESENT (0) -#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TRNG_PRESENT (0) -#define BSP_PERIPHERAL_TSD_PRESENT (1) -#define BSP_PERIPHERAL_TSN_PRESENT (1) -#define BSP_PERIPHERAL_TZF_PRESENT (1) -#define BSP_PERIPHERAL_UARTA_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ULPT_PRESENT (0) -#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_USB_PRESENT (1) -#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_USB_FS_PRESENT (1) -#define BSP_PERIPHERAL_USB_HS_PRESENT (1) -#define BSP_PERIPHERAL_USBCC_PRESENT (0) -#define BSP_PERIPHERAL_WDT_PRESENT (1) -#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_api.h deleted file mode 100644 index dcb104b06..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_SYSTEM_INTERFACES - * @defgroup IOPORT_API I/O Port Interface - * @brief Interface for accessing I/O ports and configuring I/O functionality. - * - * @section IOPORT_API_SUMMARY Summary - * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. - * Port and pin direction can be changed. - * - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_API_H -#define R_IOPORT_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common error codes and definitions. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -#ifndef BSP_OVERRIDE_IOPORT_SIZE_T - -/** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size -#endif - -/** Pin identifier and pin configuration value */ -typedef struct st_ioport_pin_cfg -{ - uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure - bsp_io_port_pin_t pin; ///< Pin identifier -} ioport_pin_cfg_t; - -/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ -typedef struct st_ioport_cfg -{ - uint16_t number_of_pins; ///< Number of pins for which there is configuration data - ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data - const void * p_extend; ///< Pointer to hardware extend configuration -} ioport_cfg_t; - -/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - */ -typedef void ioport_ctrl_t; - -/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ -typedef struct st_ioport_api -{ - /** Initialize internal driver data and initial pin configurations. Called during startup. Do - * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of - * multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Close the API. - * - * @param[in] p_ctrl Pointer to control structure. - **/ - fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); - - /** Configure multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Configure settings for an individual pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] cfg Configuration options for the pin. - */ - fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); - - /** Read the event input data of the specified pin and return the level. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_event Pointer to return the event data. - */ - fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); - - /** Write pin event data. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin event data is to be written to. - * @param[in] pin_value Level to be written to pin output event. - */ - fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); - - /** Read level of a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_value Pointer to return the pin level. - */ - fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); - - /** Write specified level to a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be written to. - * @param[in] level State to be written to the pin. - */ - fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); - - /** Set the direction of one or more pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port. - * @param[in] mask Mask controlling which pins on the port are to be configured. - */ - fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, - ioport_size_t mask); - - /** Read captured event data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_event_data Pointer to return the event data. - */ - fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); - - /** Write event output data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port event data will be written to. - * @param[in] event_data Data to be written as event data to specified port. - * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. - * being written to port. - */ - fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, - ioport_size_t mask_value); - - /** Read states of pins on the specified port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_port_value Pointer to return the port value. - */ - fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); - - /** Write to multiple pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be written to. - * @param[in] value Value to be written to the port. - * @param[in] mask Mask controlling which pins on the port are written to. - */ - fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); -} ioport_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_ioport_instance -{ - ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - ioport_api_t const * p_api; ///< Pointer to the API structure for this instance -} ioport_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT_API) - **********************************************************************************************************************/ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_cfg.h deleted file mode 100644 index d2688bf5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/r_ioport_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#ifdef __cplusplus -} -#endif -#endif /* R_IOPORT_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/renesas.h b/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/renesas.h deleted file mode 100644 index 41098a054..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/thirdparty/ra6m5ah/renesas.h +++ /dev/null @@ -1,154 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* Ensure Renesas MCU variation definitions are included to ensure MCU - * specific register variations are handled correctly. */ -#ifndef BSP_FEATURE_H - #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." -#endif - -/** @addtogroup Renesas - * @{ - */ - -/** @addtogroup RA - * @{ - */ - -#ifndef RA_H - #define RA_H - - #ifdef __cplusplus -extern "C" { - #endif - - #include "cmsis_compiler.h" - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - - #if BSP_MCU_GROUP_RA0E1 - #include "R7FA0E107.h" - #elif BSP_MCU_GROUP_RA2A1 - #include "R7FA2A1AB.h" - #elif BSP_MCU_GROUP_RA2A2 - #include "R7FA2A2AD.h" - #elif BSP_MCU_GROUP_RA2E1 - #include "R7FA2E1A9.h" - #elif BSP_MCU_GROUP_RA2E2 - #include "R7FA2E2A7.h" - #elif BSP_MCU_GROUP_RA2E3 - #include "R7FA2E307.h" - #elif BSP_MCU_GROUP_RA2L1 - #include "R7FA2L1AB.h" - #elif BSP_MCU_GROUP_RA4E1 - #include "R7FA4E10D.h" - #elif BSP_MCU_GROUP_RA4E2 - #include "R7FA4E2B9.h" - #elif BSP_MCU_GROUP_RA4M1 - #include "R7FA4M1AB.h" - #elif BSP_MCU_GROUP_RA4M2 - #include "R7FA4M2AD.h" - #elif BSP_MCU_GROUP_RA4M3 - #include "R7FA4M3AF.h" - #elif BSP_MCU_GROUP_RA4T1 - #include "R7FA4T1BB.h" - #elif BSP_MCU_GROUP_RA4W1 - #include "R7FA4W1AD.h" - #elif BSP_MCU_GROUP_RA4L1 - #include "R7FA4L1BD.h" - #elif BSP_MCU_GROUP_RA6E1 - #include "R7FA6E10F.h" - #elif BSP_MCU_GROUP_RA6E2 - #include "R7FA6E2BB.h" - #elif BSP_MCU_GROUP_RA6M1 - #include "R7FA6M1AD.h" - #elif BSP_MCU_GROUP_RA6M2 - #include "R7FA6M2AF.h" - #elif BSP_MCU_GROUP_RA6M3 - #include "R7FA6M3AH.h" - #elif BSP_MCU_GROUP_RA6M4 - #include "R7FA6M4AF.h" - #elif BSP_MCU_GROUP_RA6M5 - #include "R7FA6M5BH.h" - #elif BSP_MCU_GROUP_RA6T1 - #include "R7FA6T1AD.h" - #elif BSP_MCU_GROUP_RA6T2 - #include "R7FA6T2BD.h" - #elif BSP_MCU_GROUP_RA6T3 - #include "R7FA6T3BB.h" - #elif BSP_MCU_GROUP_RA8M1 - #include "R7FA8M1AH.h" - #elif BSP_MCU_GROUP_RA8D1 - #include "R7FA8D1BH.h" - #elif BSP_MCU_GROUP_RA8T1 - #include "R7FA8T1AH.h" - #elif BSP_MCU_GROUP_RA8E1 - #include "R7FA8E1AF.h" - #else - #if __has_include("renesas_internal.h") - #include "renesas_internal.h" - #else - #warning "Unsupported MCU" - #endif - #endif - -/* - * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB - * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 - * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: - * - * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | - * |-----------|------------|------------------------| - * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | - * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | - * - * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ - * - * IAR is currently the only toolchain producing the correct __ARM_ARCH value. - * - *- See https://github.com/ARM-software/CMSIS_6/issues/159 - */ - #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 - #undef __ARM_ARCH - #define __ARM_ARCH 801 - #endif - - #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M4 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) - #define RENESAS_CORTEX_M23 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M33 - #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M85 - #else - #warning Unsupported Architecture - #endif - - #ifdef __cplusplus -} - #endif - -#endif /* RA_H */ - -/** @} */ /* End of group RA */ - -/** @} */ /* End of group Renesas */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/R7FA6M5BH.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/R7FA6M5BH.h deleted file mode 100644 index e37ff9a82..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/R7FA6M5BH.h +++ /dev/null @@ -1,29959 +0,0 @@ -/* - * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause - * - * @file ./out/R7FA6M5BH.h - * @brief CMSIS HeaderFile - * @version 1.10.08 - */ - -/** @addtogroup Renesas Electronics Corporation - * @{ - */ - -/** @addtogroup R7FA6M5BH - * @{ - */ - -#ifndef R7FA6M5BH_H - #define R7FA6M5BH_H - - #ifdef __cplusplus -extern "C" { - #endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ - #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ - #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ - #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ - #define __MPU_PRESENT 1 /*!< MPU present */ - #define __FPU_PRESENT 1 /*!< FPU present */ - #define __FPU_DP 0 /*!< Double Precision FPU */ - #define __DSP_PRESENT 1 /*!< DSP extension present */ - #define __SAUREGION_PRESENT 0 /*!< SAU region present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - - #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ - #include "system.h" /*!< R7FA6M5BH System */ - - #ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I - #endif - #ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O - #endif - #ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO - #endif - -/* ======================================== Start of section using anonymous unions ======================================== */ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined(__ICCARM__) - #pragma language=extended - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning 586 - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #else - #warning Not supported compiler type - #endif - -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - -/** - * @brief R_BUS_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ - - struct - { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; - }; - - union - { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ - - struct - { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; - }; - __IM uint32_t RESERVED1; -} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_CSb [CSb] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ - - struct - { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; - }; - __IM uint16_t RESERVED1[3]; - - union - { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ - - struct - { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; - }; - __IM uint16_t RESERVED2[2]; -} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ - - struct - { - __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint8_t : 3; - __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ - uint8_t : 2; - } SDCCR_b; - }; - - union - { - __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ - - struct - { - __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ - uint8_t : 7; - } SDCMOD_b; - }; - - union - { - __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ - - struct - { - __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ - uint8_t : 7; - } SDAMOD_b; - }; - __IM uint8_t RESERVED; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ - - struct - { - __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ - uint8_t : 7; - } SDSELF_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ - - struct - { - __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ - __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count - * Setting. ( REFW+1 Cycles ) */ - } SDRFCR_b; - }; - - union - { - __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ - - struct - { - __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ - uint8_t : 7; - } SDRFEN_b; - }; - __IM uint8_t RESERVED4; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ - - struct - { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ - - struct - { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; - - union - { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ - - struct - { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ - - struct - { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; - }; - - union - { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ - - struct - { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ - uint16_t : 1; - } SDMOD_b; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; - - union - { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ - - struct - { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; - }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ - -/** - * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ - } ADD_b; - }; - - union - { - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ - } STAT_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ - - struct - { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ - - struct - { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ - - struct - { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ - - struct - { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ - __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ - uint8_t : 2; - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - - struct - { - __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when - * a bus error occurs */ - uint32_t : 31; - } IRQEN_b; - }; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ - - struct - { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; - }; - }; - __IM uint32_t RESERVED3; -} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[36]; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ - - struct - { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } STAT_b; - }; - __IM uint8_t RESERVED1[7]; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ - - struct - { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } CLR_b; - }; -} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ - -/** - * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } MRE0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } FLBI_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S0BI_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S1BI_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S2BI_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S3BI_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } STBYSBI_b; - }; - __IM uint32_t RESERVED7; - - union - { - union - { - __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } ECBI_b; - }; - - union - { - __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI0BI_b; - }; - }; - __IM uint32_t RESERVED8; - - union - { - union - { - __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } EOBI_b; - }; - - union - { - __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI1BI_b; - }; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PBBI_b; - }; - __IM uint32_t RESERVED10; - - union - { - union - { - __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PABI_b; - }; - - union - { - __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU0SAHBI_b; - }; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PSBI_b; - }; -} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ - -/** - * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } FHBI_b; - }; - - union - { - __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } MRC0BI_b; - }; - }; - __IM uint32_t RESERVED[5]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S1BI_b; - }; -} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ - -/** - * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ - - struct - { - __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read - * Write. */ - - struct - { - __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write - * Status. */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - - struct - { - __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ - __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ - __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ - uint16_t : 13; - } BUSOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } BUSOADPT_b; - }; - __IM uint16_t RESERVED1[5]; - - union - { - __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection - * Register. */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ - } MSAOAD_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } MSAPT_b; - }; -} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ - -/** - * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ - - struct - { - __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ - __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ - __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ - __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ - __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ - __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ - __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ - __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ - __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ - __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ - __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ - __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ - __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ - __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ - __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ - __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ - __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ - __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ - __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ - __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ - __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ - __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ - __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ - __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ - __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ - __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ - __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ - __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ - __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ - __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ - __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ - __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ - } STAT_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ - - struct - { - __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ - __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ - __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ - __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ - __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ - __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ - __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ - __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ - __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ - __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ - __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ - __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ - __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ - __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ - __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ - __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ - __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ - __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ - __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ - __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ - __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ - __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ - __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ - __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ - __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ - __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ - __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ - __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ - __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ - __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ - __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ - __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ - } CLR_b; - }; -} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ - -/** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - - struct - { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ - uint16_t : 2; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ - uint16_t : 10; - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) - */ -typedef struct -{ - union - { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ - - struct - { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; - }; - - union - { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ - - struct - { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; - }; - - union - { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ - - struct - { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; - }; - - union - { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ - - struct - { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; - }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ - - struct - { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; - }; - - union - { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ - - struct - { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ - - struct - { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; - }; - - union - { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ - - struct - { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; - }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ - union - { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ - - struct - { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; - }; - - union - { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct - { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - - struct - { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - - struct - { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct - { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ - - struct - { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - - struct - { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - - struct - { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ - - struct - { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ - - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ - union - { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - - struct - { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; - }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ - union - { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ - - struct - { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; - }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) - */ -typedef struct -{ - union - { - __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ - uint16_t : 12; - } AC_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ - - struct - { - __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. - * NOTE: Some low-order bits are fixed to 0. */ - } S_b; - }; - - union - { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ - - struct - { - __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination. NOTE: Some low-order - * bits are fixed to 1. */ - } E_b; - }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } EN_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } ENPT_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_SEC_b; - }; - __IM uint16_t RESERVED3; - __IM uint32_t RESERVED4[60]; - __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ - __IM uint32_t RESERVED5[32]; -} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ - union - { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ - - struct - { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; - }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; - - union - { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union - { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union - { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; - - union - { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; - }; - __IM uint8_t RESERVED3[3]; - - union - { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; - - union - { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; - }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; - }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; - }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ - union - { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ - - struct - { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; - }; - - union - { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ - - struct - { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; - }; - - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; - - union - { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct - { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; - - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ - - struct - { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; - - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ - - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; - - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; - }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ - - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct - { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - - struct - { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ - - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct - { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ - - struct - { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED23[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ - - struct - { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; - }; - - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; - - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ - - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ - __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ - uint32_t : 2; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ - uint32_t : 27; - } MSSAR_b; - }; - - union - { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - - union - { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ - - struct - { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; - }; - - union - { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; - }; - - union - { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ - - struct - { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; - }; - - union - { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ - - struct - { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; - }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ - - union - { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - - union - { - __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ - }; - __IM uint32_t RESERVED4[58]; - - union - { - union - { - __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ - uint32_t : 31; - } BUSMABT_b; - }; - __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - }; - __IM uint32_t RESERVED5[46]; - - union - { - __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ - __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ - }; - __IM uint32_t RESERVED6[33]; - - union - { - __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ - - struct - { - __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ - uint32_t : 2; - __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ - uint32_t : 12; - __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ - uint32_t : 15; - } BUSDIVBYP_b; - }; - __IM uint32_t RESERVED7[63]; - - union - { - __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ - - struct - { - __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ - uint16_t : 15; - } BUSTHRPUT_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[255]; - __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED10[16]; - - union - { - __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address - * and Read/Write Status registers. */ - }; - __IM uint32_t RESERVED11[28]; - - union - { - __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ - __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ - }; - __IM uint32_t RESERVED12[16]; - __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED13[5]; - __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ -} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ - union - { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; - }; - - union - { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct - { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; - }; - - union - { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - - struct - { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; - - union - { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - - struct - { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; - }; - - union - { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ - - struct - { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - - union - { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; - }; - - union - { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ - - struct - { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; - }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; - }; - - union - { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - - struct - { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; - }; - - union - { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ - - struct - { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; - }; - - union - { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ - - struct - { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; - }; - - union - { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ - - struct - { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; - }; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - - struct - { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; - }; - - union - { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ - - struct - { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; - }; - - union - { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - - struct - { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; - }; - - union - { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; - }; - - union - { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; - }; - __IM uint32_t RESERVED3[18]; - - union - { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ - - struct - { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; - }; - __IM uint32_t RESERVED4[18]; - - union - { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ - - struct - { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; - }; - __IM uint32_t RESERVED5[18]; - - union - { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; - }; - __IM uint32_t RESERVED6[18]; - - union - { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct - { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; - }; - - union - { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; - }; - - union - { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ - - struct - { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; - }; - - union - { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; - }; - - union - { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; - }; - - union - { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ - - struct - { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; - }; - - union - { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ - - struct - { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; - }; - __IM uint32_t RESERVED7[2]; - - union - { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ - - struct - { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; - }; - __IM uint32_t RESERVED8[288]; - - union - { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ - - struct - { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; - }; - __IM uint32_t RESERVED9[288]; - - union - { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ - - struct - { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; - }; - __IM uint32_t RESERVED10[36]; - - union - { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ - - struct - { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; - }; - __IM uint32_t RESERVED11[36]; - - union - { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ - - struct - { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; - }; - __IM uint32_t RESERVED12[36]; - - union - { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ - - struct - { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; - }; - __IM uint32_t RESERVED13[36]; - - union - { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ - - struct - { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; - }; - __IM uint32_t RESERVED14[40]; - - union - { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; - }; - __IM uint32_t RESERVED15[6]; - - union - { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; - }; - __IM uint32_t RESERVED16[6]; - - union - { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; - }; - __IM uint32_t RESERVED17[6]; - - union - { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; - }; - __IM uint32_t RESERVED18[6]; - - union - { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; - }; - __IM uint32_t RESERVED19[6]; - - union - { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; - }; - __IM uint32_t RESERVED20[6]; - - union - { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; - }; - __IM uint32_t RESERVED21[6]; - - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; - - union - { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; - }; - __IM uint32_t RESERVED23[6]; - - union - { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; - }; - __IM uint32_t RESERVED24[6]; - - union - { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; - }; - __IM uint32_t RESERVED25[6]; - - union - { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; - }; - __IM uint32_t RESERVED26[6]; - - union - { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - - struct - { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; - }; - - union - { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ - - struct - { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; - }; - __IM uint32_t RESERVED27; - - union - { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; - }; - - union - { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ - - struct - { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; - }; - __IM uint32_t RESERVED28[24]; - - union - { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ - - struct - { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; - }; - __IM uint32_t RESERVED29[6]; - - union - { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ - - struct - { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; - }; - __IM uint32_t RESERVED30[6]; - - union - { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ - - struct - { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; - }; - __IM uint32_t RESERVED31[46]; - - union - { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ - - struct - { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; - }; - __IM uint32_t RESERVED32; - - union - { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ - - struct - { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; - }; - - union - { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ - - struct - { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; - }; - __IM uint32_t RESERVED33; - - union - { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ - - struct - { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; - }; - __IM uint32_t RESERVED34; - - union - { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ - - struct - { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; - }; - - union - { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ - - struct - { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ - - struct - { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ - - struct - { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; - - union - { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ - - struct - { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; - }; - - union - { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ - - struct - { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; - }; - __IM uint32_t RESERVED36[2]; - - union - { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ - - struct - { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; - }; - - union - { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ - - struct - { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; - }; - __IM uint32_t RESERVED37[2]; - - union - { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; - }; - __IM uint32_t RESERVED38[10]; - - union - { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ - - struct - { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; - }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; - - union - { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ - - struct - { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; - }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ - -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; - - union - { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - - struct - { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; - }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ - -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ - union - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - - struct - { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; - }; - - union - { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - - struct - { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; - }; - - union - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ - - struct - { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; - }; - - union - { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct - { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; - - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ - - struct - { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; - }; - - union - { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ - - struct - { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; - }; - - union - { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; - }; - - union - { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; - }; - - union - { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ - - struct - { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; - }; - - union - { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ - - struct - { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; - }; - - union - { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; - }; - - union - { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ - - struct - { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; - }; - - union - { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ - - struct - { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; - }; - - union - { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ - - struct - { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; - }; - - union - { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ - - struct - { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; - }; - - union - { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ - - struct - { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; - }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ - -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ - union - { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ - - struct - { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; - }; - - union - { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; - }; - - union - { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; - }; - - union - { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; - }; - - union - { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ - - struct - { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; - }; - - union - { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; - }; - - union - { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ - - struct - { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; - }; - __IM uint16_t RESERVED[9]; - - union - { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; - - union - { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ - - struct - { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ - union - { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct - { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct - { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 12; - __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ - __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; - __IM uint32_t RESERVED1[123]; - - union - { - __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ - - struct - { - __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ - __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ - uint32_t : 6; - __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ - uint32_t : 21; - } FSBLSTAT_b; - }; -} R_DEBUG_Type; /*!< Size = 516 (0x204) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ - -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ - union - { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ - - struct - { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ - - struct - { - __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ - uint8_t : 3; - __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ - uint8_t : 3; - } DMCTL_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[11]; - - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ - - struct - { - __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ - uint32_t : 4; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; - }; - __IM uint32_t RESERVED6[15]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ - union - { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ - - struct - { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; - }; - - union - { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ - - struct - { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; - }; - - union - { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; - }; - - union - { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; - }; - - union - { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ - - struct - { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ - - struct - { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; - }; - - union - { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ - - struct - { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-11 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-11 Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-11 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-11 Mode */ - } DMAMD_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ - - struct - { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-11 mode for transfer source or destination. */ - } DMOFR_b; - }; - - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ - - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - - union - { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ - - struct - { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; - }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ - - union - { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct - { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; - - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ - - struct - { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; - }; - - union - { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct - { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ - -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ - - struct - { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ - - struct - { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; - }; - - union - { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ - - struct - { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; - }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ - -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ - union - { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_b; - }; - - union - { - __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ - - struct - { - __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ - uint8_t : 7; - } DTCADMOD_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ - - struct - { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ - - struct - { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; - }; - - union - { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_SEC_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - - union - { - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_SEC_b; - }; - - union - { - __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ - - struct - { - __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ - } DTCDISP_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ - - struct - { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; - }; - - union - { - __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ - } DTCIBR_b; - }; - - union - { - __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ - - struct - { - __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ - uint8_t : 7; - } DTCOR_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ - - struct - { - __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ - uint16_t : 7; - __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ - } DTCSQE_b; - }; - __IM uint16_t RESERVED10; -} R_DTC_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ - union - { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; - }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; - - union - { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ - - struct - { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ - - struct - { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ - -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ -{ - union - { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ - - struct - { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ - - struct - { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ - - struct - { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ - - struct - { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ - - struct - { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ - - struct - { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; - }; - __IM uint32_t RESERVED5[5]; - - union - { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ - - struct - { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ - - struct - { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; - }; - - union - { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ - - struct - { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; - }; - - union - { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ - - struct - { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ - - struct - { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; - }; - - union - { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ - - struct - { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; - }; - __IM uint32_t RESERVED8[20]; - - union - { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ - - struct - { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ - - struct - { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ - - struct - { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ - - union - { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ - - struct - { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; - }; - - union - { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ - - struct - { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ - - struct - { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; - }; - - union - { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ - - struct - { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union - { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; - }; - - union - { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; - }; - - union - { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ - - struct - { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; - }; - - union - { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ - - struct - { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; - }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ - -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ -{ - union - { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ - - struct - { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ - - struct - { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ - - struct - { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ - - struct - { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ - - struct - { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ - - struct - { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ - - struct - { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; - }; - __IM uint32_t RESERVED11[2]; - - union - { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ - - struct - { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; - }; - - union - { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ - - struct - { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; - }; - - union - { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ - - struct - { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; - }; - - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ - - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ - - struct - { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; - }; - - union - { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ - - struct - { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; - }; - __IM uint32_t RESERVED13[18]; - - union - { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ - - struct - { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; - }; - - union - { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; - }; - __IM uint32_t RESERVED14; - - union - { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ - - struct - { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; - }; - - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ - union - { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ - -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ - - struct - { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; - - union - { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ - - struct - { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; - }; - - union - { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ - - struct - { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union - { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ - - struct - { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ - - struct - { - __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ - uint8_t : 5; - } FCNTSELR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR0_b; - }; - - union - { - __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR1_b; - }; - __IM uint32_t RESERVED12[9]; - - union - { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ - - struct - { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; - }; - __IM uint16_t RESERVED13; - - union - { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ - - struct - { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; - }; - __IM uint16_t RESERVED14; - - union - { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ - - struct - { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; - }; - - union - { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ - - struct - { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; - }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16; - - union - { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ - - struct - { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; - }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[4]; - - union - { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ - - struct - { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; - }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[11]; - - union - { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ - - struct - { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; - - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ - - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; - - union - { - union - { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ - - struct - { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; - }; - - union - { - __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ - - struct - { - __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address - * or the last blank checked address which is found in 'Blank - * Check' command execution. */ - uint32_t : 8; - } FBCADDR_b; - }; - }; - - union - { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ - - struct - { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; - }; - - union - { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ - - struct - { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ - - struct - { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ - - struct - { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; - }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; - - union - { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ - - struct - { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-11 Register */ - - struct - { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-11 Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; - - union - { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ - - struct - { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; - - union - { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ - - struct - { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ - uint16_t : 6; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ - __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ - uint16_t : 4; - __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ - } FSAR_b; - }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief General PWM Timer (R_GPT0) - */ - -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ - union - { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ - - struct - { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; - }; - - union - { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ - - struct - { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; - }; - - union - { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ - - struct - { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; - }; - - union - { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ - - struct - { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; - }; - - union - { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ - - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; - }; - - union - { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ - - struct - { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; - }; - - union - { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ - - struct - { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; - - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ - - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; - - union - { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ - - struct - { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ - uint32_t : 7; - } GTICASR_b; - }; - - union - { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ - - struct - { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ - uint32_t : 7; - } GTICBSR_b; - }; - - union - { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ - - struct - { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 3; - __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ - __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ - uint32_t : 2; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; - }; - - union - { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ - - struct - { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection - * timing setting */ - uint32_t : 3; - } GTUDDTYC_b; - }; - - union - { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ - - struct - { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-11.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-11.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; - }; - - union - { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ - - struct - { - __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; - }; - - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ - - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; - }; - - union - { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ - - struct - { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; - }; - - union - { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ - - struct - { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; - }; - - union - { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ - - struct - { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; - }; - - union - { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ - - struct - { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; - }; - - union - { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ - - struct - { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; - }; - - union - { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ - - struct - { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; - - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; - - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; - - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ - - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; - - union - { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; - }; - - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ - - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; - - union - { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; - }; - - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ - - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; - }; - - union - { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ - - struct - { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; - }; - - union - { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ - - struct - { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; - }; - - union - { - __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Control Register */ - - struct - { - __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter - * 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 - * Skipping Count Setting */ - __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping - * Counter 1 Initial Value */ - __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping - * Counter 1 */ - __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping - * 2 Skipping Count Setting */ - __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Initial Value */ - __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping - * Counter 2 */ - } GTADCMSC_b; - }; - - union - { - __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Setting Register */ - - struct - { - __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 9; - __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 9; - } GTADCMSS_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ - - struct - { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; - }; - - union - { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ - - struct - { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; - }; - __IM uint32_t RESERVED1[2]; - - union - { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ - - struct - { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; - }; - - union - { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ - - struct - { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; - }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ - -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ - union - { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ - - struct - { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; - }; - __IM uint32_t RESERVED[15]; - - union - { - __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection - * Register */ - - struct - { - __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ - uint16_t : 7; - __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ - } GTONCWP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling - * Register */ - - struct - { - __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ - uint16_t : 3; - __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ - __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ - uint16_t : 7; - } GTONCCR_b; - }; - __IM uint16_t RESERVED2; -} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ - -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ - union - { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ - - struct - { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 1; - __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; - }; - __IM uint32_t RESERVED[60]; - - union - { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - - struct - { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - - union - { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ - - struct - { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; - }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; - - union - { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ - - struct - { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; - }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; - - union - { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ - - struct - { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; - - union - { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - - struct - { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - - union - { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ - - struct - { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; - }; - - union - { - __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ - - struct - { - __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze - * Mode */ - uint32_t : 27; - } WUPEN2_b; - }; - __IM uint32_t RESERVED10[5]; - - union - { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ - - struct - { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; - }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; - __IM uint32_t RESERVED16[24]; - - union - { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ - - struct - { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; - }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ - union - { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ - - struct - { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; - }; - - union - { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ - - struct - { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; - }; - - union - { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ - - struct - { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; - }; - - union - { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ - - struct - { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; - }; - - union - { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ - - struct - { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; - }; - - union - { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ - - struct - { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; - }; - - union - { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ - - struct - { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; - }; - - union - { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ - - struct - { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; - }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ - - union - { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ - - struct - { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; - }; - - union - { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ - - struct - { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; - }; - - union - { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ - - struct - { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; - }; - - union - { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ - - struct - { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ - - struct - { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; - }; - - union - { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ - - struct - { - __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; - }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; - }; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; - - union - { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ - -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ - union - { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ - - struct - { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ - - struct - { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; - }; - - union - { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ - - struct - { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; - }; - - union - { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ - - struct - { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ - - struct - { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 2; - __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ - __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ - __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ - __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ - uint32_t : 3; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; - }; - - union - { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; - }; - - union - { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; - }; - - union - { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; - }; - - union - { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ - - struct - { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ - - struct - { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; - }; - __IM uint32_t RESERVED4[4]; - - union - { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ - - struct - { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ - - struct - { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; - }; - - union - { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ - - struct - { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ - uint32_t : 13; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; - }; - - union - { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ - - struct - { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; - }; - - union - { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ - - struct - { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; - }; - - union - { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ - - struct - { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; - }; - - union - { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ - - struct - { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; - }; - - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ - - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; - - union - { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ - - struct - { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; - }; - - union - { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ - - struct - { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; - }; - - union - { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ - - struct - { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ - - struct - { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ - - struct - { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; - }; - - union - { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ - - struct - { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; - }; - __IM uint32_t RESERVED9[2]; - - union - { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ - - struct - { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; - }; - __IM uint32_t RESERVED10[3]; - - union - { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ - - struct - { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; - }; - __IM uint32_t RESERVED11[23]; - - union - { - __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ - - struct - { - __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ - uint32_t : 31; - } STCTL_b; - }; - - union - { - __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ - - struct - { - __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ - __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ - __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ - uint32_t : 5; - __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ - uint32_t : 16; - } ATCTL_b; - }; - - union - { - __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ - - struct - { - __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ - uint32_t : 31; - } ATTRG_b; - }; - - union - { - __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ - - struct - { - __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, - * SC2. */ - uint32_t : 31; - } ATCCNTE_b; - }; - __IM uint32_t RESERVED12[4]; - - union - { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ - - struct - { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; - }; - __IM uint32_t RESERVED13[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED14[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - - union - { - __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ - - struct - { - __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ - } HCMDQP_b; - }; - - union - { - __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ - - struct - { - __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ - } HRSPQP_b; - }; - - union - { - __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ - - struct - { - __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ - } HTDTBP_b; - }; - - union - { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; - }; - - union - { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; - }; - __IM uint32_t RESERVED15[10]; - - union - { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ - - struct - { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; - }; - - union - { - __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ - uint32_t : 16; - } HQTHCTL_b; - }; - - union - { - __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold - * Control Register */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ - uint32_t : 5; - } HTBTHCTL_b; - }; - __IM uint32_t RESERVED16; - - union - { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ - - struct - { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 3; - __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ - uint32_t : 7; - } BST_b; - }; - - union - { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ - - struct - { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ - uint32_t : 7; - } BSTE_b; - }; - - union - { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ - - struct - { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ - uint32_t : 7; - } BIE_b; - }; - - union - { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ - - struct - { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 3; - __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ - uint32_t : 7; - } BSTFC_b; - }; - - union - { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; - }; - - union - { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; - }; - - union - { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; - }; - - union - { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; - }; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ - __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ - uint32_t : 1; - __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ - uint32_t : 22; - } HTST_b; - }; - - union - { - __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ - __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ - uint32_t : 22; - } HTSTE_b; - }; - - union - { - __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ - __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ - uint32_t : 22; - } HTIE_b; - }; - - union - { - __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ - __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ - uint32_t : 1; - __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ - uint32_t : 22; - } HTSTFC_b; - }; - - union - { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ - - struct - { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; - }; - - union - { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - - struct - { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ - uint32_t : 13; - } SVST_b; - }; - - union - { - __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ - - struct - { - __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; - }; - - union - { - __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ - - struct - { - __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ - } MRCCPT_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; - }; - __IM uint32_t RESERVED19; - - union - { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; - }; - __IM uint32_t RESERVED20; - - union - { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; - }; - __IM uint32_t RESERVED21; - - union - { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; - }; - __IM uint32_t RESERVED22; - - union - { - __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS4_b; - }; - __IM uint32_t RESERVED23; - - union - { - __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS5_b; - }; - __IM uint32_t RESERVED24; - - union - { - __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS6_b; - }; - __IM uint32_t RESERVED25; - - union - { - __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS7_b; - }; - __IM uint32_t RESERVED26[16]; - - union - { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - - struct - { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; - }; - __IM uint32_t RESERVED27[3]; - - union - { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; - }; - - union - { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; - }; - - union - { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; - }; - __IM uint32_t RESERVED28[5]; - - union - { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; - }; - - union - { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; - }; - - union - { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; - }; - - union - { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; - }; - - union - { - __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT4_b; - }; - - union - { - __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT5_b; - }; - - union - { - __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT6_b; - }; - - union - { - __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT7_b; - }; - __IM uint32_t RESERVED29[12]; - - union - { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - - struct - { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; - }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED30; - - union - { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; - }; - - union - { - __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD1_b; - }; - - union - { - __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD2_b; - }; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ - - struct - { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; - }; - - union - { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - - struct - { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; - }; - - union - { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ - - struct - { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; - }; - - union - { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ - - struct - { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; - }; - - union - { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - - struct - { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; - }; - - union - { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ - - struct - { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; - }; - - union - { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ - - struct - { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; - }; - - union - { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ - - struct - { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; - }; - - union - { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ - - struct - { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; - }; - - union - { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ - - struct - { - __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ - __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ - __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ - uint32_t : 5; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; - }; - - union - { - __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) - * Register */ - - struct - { - __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ - __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ - uint32_t : 4; - __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ - uint32_t : 24; - } CETSS_b; - }; - - union - { - __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ - - struct - { - __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ - __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ - __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ - uint32_t : 29; - } CGHDRCAP_b; - }; - - union - { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ - - struct - { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; - }; - __IM uint32_t RESERVED32[4]; - - union - { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; - }; - - union - { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; - }; - __IM uint32_t RESERVED33[9]; - - union - { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ - - struct - { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; - }; - - union - { - __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ - uint32_t : 16; - } HQSTLV_b; - }; - - union - { - __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ - uint32_t : 16; - } HDBSTLV_b; - }; - - union - { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - - struct - { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; - }; - - union - { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ - - struct - { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; - __IM uint32_t RESERVED34[3]; - - union - { - __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ - - struct - { - __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ - uint32_t : 16; - } SC1CPT_b; - }; - - union - { - __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ - - struct - { - __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ - uint32_t : 16; - } SC2CPT_b; - }; -} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OADPT_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[62]; - __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ - - struct - { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; - }; - - union - { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ - - struct - { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; - }; - - union - { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ - - struct - { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; - }; - - union - { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; - }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ - -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ - union - { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; - - struct - { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; - }; - - union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; - }; - - union - { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; - - struct - { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; - - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ - - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; - }; - - union - { - union - { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ - - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; - - struct - { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; - - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; - }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ - -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-MISC (R_PMISC) - */ - -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ - union - { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; - }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ - union - { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct - { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; - - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - - struct - { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; - - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; - - union - { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct - { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - - struct - { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; - - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ - - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; - }; - - union - { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct - { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct - { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ - __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using - * time error adjustment function inlow-consumption clock - * mode. */ - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; - }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; - - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; - - union - { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; - - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; - }; - __IM uint8_t RESERVED9; - - union - { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; - - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; - }; - __IM uint8_t RESERVED10; - - union - { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; - - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; - }; - __IM uint8_t RESERVED11; - - union - { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; - - union - { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; - }; - __IM uint8_t RESERVED12; - - union - { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; - - union - { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; - }; - - union - { - union - { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; - - union - { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ - - struct - { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; - }; - - union - { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - - struct - { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; - }; - - union - { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ - - struct - { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; - }; - __IM uint8_t RESERVED19; - - union - { - __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ - - struct - { - uint16_t : 5; - __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ - } RADJ2_b; - }; - __IM uint16_t RESERVED20[7]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ - -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ - union - { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; - - union - { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; - - union - { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; - - union - { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct - { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; - - union - { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF - * = 0, and MMR.MANEN = 1) */ - - struct - { - __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_MANC_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - union - { - __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ - __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ - uint16_t : 2; - __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ - uint16_t : 3; - } TDRHL_MAN_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - union - { - __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ - uint16_t : 2; - __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ - uint16_t : 3; - } RDRHL_MAN_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ - - struct - { - __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ - __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ - __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ - uint8_t : 1; - __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ - __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ - __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ - __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ - } MMR_b; - }; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; - }; - - union - { - __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ - __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ - uint8_t : 2; - } TMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ - - struct - { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; - }; - - union - { - __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ - __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ - uint8_t : 2; - } RMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ - - struct - { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; - }; - - union - { - __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ - - struct - { - __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ - __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ - uint8_t : 5; - } MESR_b; - }; - }; - - union - { - union - { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ - - struct - { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; - }; - - union - { - __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ - - struct - { - __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ - __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ - uint8_t : 5; - } MECR_b; - }; - }; - - union - { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ - - struct - { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; - }; - - union - { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ - - struct - { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; - - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct - { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ - - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ - - struct - { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ - - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ - - struct - { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ - - struct - { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; - - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct - { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ - __IM uint16_t RESERVED1[4]; - - union - { - __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ - - struct - { - __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ - uint8_t : 7; - } SCIMSKEN_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_SCI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ - -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ - union - { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ - - struct - { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ - - struct - { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; - }; - - union - { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - - struct - { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; - }; - - union - { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - - struct - { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; - }; - - union - { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - - struct - { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; - }; - - union - { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - - struct - { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; - }; - - union - { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - - struct - { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; - }; - - union - { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ - - struct - { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; - }; - - union - { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - - struct - { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; - }; - - union - { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ - - struct - { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; - }; - - union - { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - - struct - { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; - }; - - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ - - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; - - union - { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - - struct - { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; - }; - - union - { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; - }; - - union - { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ - - struct - { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; - }; - - union - { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; - }; - - union - { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct - { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; - }; - - union - { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct - { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; - }; - - union - { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ - - struct - { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; - }; - - union - { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - - struct - { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ - - struct - { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; - }; - - union - { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - - struct - { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; - }; - - union - { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ - - struct - { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - - struct - { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; - }; - __IM uint32_t RESERVED3[79]; - - union - { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ - - struct - { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; - }; - __IM uint32_t RESERVED4[3]; - - union - { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ - - struct - { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; - }; - __IM uint32_t RESERVED6[4]; - - union - { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ - - struct - { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; - }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ - - struct - { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; - }; - - union - { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - - struct - { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; - }; - - union - { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ - - struct - { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; - }; - - union - { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - - struct - { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ - }; - - union - { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ - - struct - { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; - }; - - union - { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - - struct - { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; - }; - - union - { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ - - struct - { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; - }; - - union - { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ - - struct - { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; - }; - - union - { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ - - struct - { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; - }; - - union - { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ - - struct - { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; - }; - - union - { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ - - struct - { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; - }; - - union - { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ - - struct - { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; - }; - - union - { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ - - struct - { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; - }; - - union - { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ - - struct - { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; - }; - - union - { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ - - struct - { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; - }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ - -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ - union - { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ - - struct - { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; - }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; - - union - { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ - - struct - { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; - }; - __IM uint8_t RESERVED3[179]; - - union - { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ - - struct - { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; - }; - - union - { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; - }; - - union - { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-11 Enable Register */ - - struct - { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-11 Enable */ - uint8_t : 7; - } ECC1STSEN_b; - }; - - union - { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; - }; - - union - { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; - }; - __IM uint8_t RESERVED4[11]; - - union - { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; - }; - __IM uint8_t RESERVED5[3]; - - union - { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ - - struct - { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; - }; - __IM uint8_t RESERVED6[3]; - - union - { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; - }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ -{ - union - { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ - - struct - { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; - }; - - union - { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ - - struct - { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ - - struct - { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 3; - __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ - uint32_t : 4; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; - }; - - union - { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ - - struct - { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; - }; - - union - { - union - { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - - struct - { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; - }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - - union - { - union - { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - - struct - { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; - }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - }; - - union - { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ - - struct - { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; - }; - - union - { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ - - struct - { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; - }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System Pins (R_SYSTEM) - */ - -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ - - struct - { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; - }; - - union - { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; - }; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ - - struct - { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ - - struct - { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; - }; - - union - { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ - - struct - { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; - }; - - union - { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ - - struct - { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ - - struct - { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; - }; - - union - { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ - - struct - { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; - }; - - union - { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; - }; - - union - { - __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register - * 2 */ - - struct - { - __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ - uint8_t : 1; - __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ - uint8_t : 2; - } HOCOCR2_b; - }; - - union - { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; - }; - - union - { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ - - struct - { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; - }; - - union - { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ - - struct - { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; - }; - - union - { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ - - struct - { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ - uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ - uint8_t : 1; - } OSCSF_b; - }; - __IM uint8_t RESERVED8; - - union - { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ - - struct - { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; - }; - - union - { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ - - struct - { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; - }; - - union - { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ - - struct - { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; - }; - - union - { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ - - struct - { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; - }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; - - union - { - __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ - - struct - { - __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ - uint16_t : 2; - } PLL2CCR_b; - }; - - union - { - __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ - - struct - { - __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ - uint8_t : 7; - } PLL2CR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ - - struct - { - __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock - * (valid only when LPOPTEN = 1) */ - __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ - __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W - * clock (valid only when LPOPT.LPOPTEN = 1) */ - uint8_t : 3; - __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ - } LPOPT_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ - - struct - { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ - - struct - { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; - }; - - union - { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ - - struct - { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; - }; - __IM uint32_t RESERVED15[3]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO - * trimming bits */ - } MOCOUTCR_b; - }; - - union - { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; - }; - __IM uint8_t RESERVED17; - __IM uint32_t RESERVED18[2]; - - union - { - __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ - - struct - { - __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ - uint8_t : 5; - } USBCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ - uint8_t : 5; - } OCTACKDIVCR_b; - }; - - union - { - __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ - uint8_t : 5; - } SCISPICKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ - - struct - { - __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ - uint8_t : 5; - } CANFDCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - - struct - { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; - }; - - union - { - __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ - - struct - { - __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ - uint8_t : 5; - } USB60CKDIVCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - - struct - { - __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ - uint8_t : 5; - } CECCKDIVCR_b; - }; - - union - { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ - - struct - { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ - - struct - { - __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ - uint8_t : 5; - } I3CCKDIVCR_b; - }; - __IM uint16_t RESERVED19; - - union - { - __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ - __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ - } USBCKCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ - - struct - { - __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ - uint8_t : 3; - __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ - __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ - } OCTACKCR_b; - }; - - union - { - __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ - - struct - { - __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ - uint8_t : 3; - __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ - __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ - } SCISPICKCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ - - struct - { - __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ - __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ - } CANFDCKCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - - struct - { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; - }; - - union - { - __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ - - struct - { - __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ - uint8_t : 2; - __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ - __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ - } USB60CKCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ - - struct - { - __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ - __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ - } CECCKCR_b; - }; - - union - { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ - - struct - { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ - - struct - { - __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ - uint8_t : 3; - __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ - __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ - } I3CCKCR_b; - }; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ - uint32_t : 29; - } SNZREQCR1_b; - }; - __IM uint32_t RESERVED22; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ - - struct - { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; - }; - __IM uint8_t RESERVED24; - - union - { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ - - struct - { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; - }; - - union - { - __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ - - struct - { - __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ - uint8_t : 7; - } SNZEDCR1_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ - - struct - { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; - }; - - union - { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ - - struct - { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; - }; - - union - { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ - - struct - { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; - }; - __IM uint8_t RESERVED27; - - union - { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ - - struct - { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; - }; - __IM uint8_t RESERVED28[2]; - - union - { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ - - struct - { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; - }; - __IM uint16_t RESERVED29[2]; - - union - { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ - - struct - { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; - }; - __IM uint8_t RESERVED30; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ - - struct - { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ - uint16_t : 1; - __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ - } RSTSR1_b; - }; - __IM uint16_t RESERVED32; - __IM uint32_t RESERVED33[3]; - - union - { - __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_ALT_b; - }; - - union - { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ - - struct - { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; - }; - __IM uint16_t RESERVED34; - __IM uint32_t RESERVED35[3]; - - union - { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; - }; - - union - { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; - }; - - union - { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; - }; - - union - { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; - }; - __IM uint32_t RESERVED36[183]; - - union - { - __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute - * Register */ - - struct - { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ - __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ - __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ - __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ - __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ - __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ - __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ - __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ - __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ - __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ - __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ - __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ - } CGFSAR_b; - }; - __IM uint32_t RESERVED37; - - union - { - __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - uint32_t : 1; - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 1; - __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - uint32_t : 3; - __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - uint32_t : 22; - } LPMSAR_b; - }; - - union - { - union - { - __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - uint32_t : 30; - } LVDSAR_b; - }; - - union - { - __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 29; - } RSTSAR_b; - }; - }; - - union - { - __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 13; - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - uint32_t : 8; - } BBFSAR_b; - }; - __IM uint32_t RESERVED38[3]; - - union - { - __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution - * Register */ - - struct - { - __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit - * 0 */ - __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit - * 1 */ - __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit - * 2 */ - __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit - * 3 */ - __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit - * 4 */ - __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit - * 5 */ - __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit - * 6 */ - __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit - * 7 */ - __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit - * 8 */ - __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit - * 9 */ - __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit - * 10 */ - __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit - * 11 */ - __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit - * 12 */ - __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit - * 13 */ - __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit - * 14 */ - __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit - * 15 */ - __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit - * 16 */ - __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit - * 17 */ - __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit - * 18 */ - __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit - * 19 */ - __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit - * 20 */ - uint32_t : 3; - __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit - * 24 */ - uint32_t : 1; - __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit - * 26 */ - __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit - * 27 */ - uint32_t : 4; - } DPFSAR_b; - }; - __IM uint32_t RESERVED39[6]; - __IM uint16_t RESERVED40; - - union - { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ - - struct - { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ - uint16_t : 3; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; - }; - - union - { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ - - struct - { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; - }; - - union - { - __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ - - struct - { - __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ - uint8_t : 2; - } DPSWCR_b; - }; - - union - { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ - - struct - { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; - }; - - union - { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ - - struct - { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; - }; - - union - { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ - - struct - { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; - }; - - union - { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 4; - } DPSIER3_b; - }; - - union - { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ - - struct - { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; - }; - - union - { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ - - struct - { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; - }; - - union - { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ - - struct - { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; - }; - - union - { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ - uint8_t : 4; - } DPSIFR3_b; - }; - - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; - }; - - union - { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; - }; - - union - { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ - - struct - { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; - }; - __IM uint8_t RESERVED41; - - union - { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ - - struct - { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; - }; - - union - { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ - - struct - { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; - }; - - union - { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ - - struct - { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; - }; - - union - { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ - - struct - { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; - }; - __IM uint8_t RESERVED42; - - union - { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; - }; - __IM uint16_t RESERVED43; - - union - { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ - - struct - { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; - }; - - union - { - union - { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; - }; - - union - { - __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 2; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ - } LVD1CMPCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - - struct - { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; - }; - - union - { - __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 4; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ - } LVD2CMPCR_b; - }; - }; - __IM uint8_t RESERVED44; - - union - { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; - }; - - union - { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; - }; - __IM uint8_t RESERVED45; - - union - { - __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select - * Register */ - - struct - { - __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ - uint8_t : 7; - } VBATTMNSELR_b; - }; - - union - { - __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ - - struct - { - __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ - uint8_t : 7; - } VBATTMONR_b; - }; - - union - { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ - - struct - { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; - }; - __IM uint32_t RESERVED46[8]; - - union - { - union - { - __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ - - struct - { - __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ - __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ - uint8_t : 2; - __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ - __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ - __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ - __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ - } DCDCCTL_b; - }; - - union - { - __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ - - struct - { - __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ - __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ - uint8_t : 6; - } LDOSCR_b; - }; - }; - - union - { - __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ - - struct - { - __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ - uint8_t : 6; - } VCCSEL_b; - }; - __IM uint16_t RESERVED47; - - union - { - __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ - - struct - { - __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ - uint8_t : 7; - } PL2LDOSCR_b; - }; - __IM uint8_t RESERVED48; - __IM uint16_t RESERVED49; - __IM uint32_t RESERVED50[14]; - - union - { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; - }; - - union - { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ - - struct - { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; - }; - - union - { - __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ - - struct - { - __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ - uint8_t : 6; - } SOMRG_b; - }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[3]; - - union - { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; - }; - __IM uint8_t RESERVED53; - - union - { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; - }; - __IM uint8_t RESERVED54; - __IM uint32_t RESERVED55[7]; - - union - { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; - }; - - union - { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ - - struct - { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; - }; - - union - { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ - - struct - { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; - }; - __IM uint8_t RESERVED56; - - union - { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ - - struct - { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; - }; - __IM uint8_t RESERVED57; - - union - { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ - - struct - { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; - }; - __IM uint8_t RESERVED58; - - union - { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; - }; - - union - { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ - - struct - { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; - }; - - union - { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ - - struct - { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; - }; - - union - { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ - - struct - { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; - }; - - union - { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ - - struct - { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; - }; - - union - { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ - - struct - { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; - }; - - union - { - __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ - uint8_t : 4; - } VBTBER_b; - }; - __IM uint8_t RESERVED59; - __IM uint16_t RESERVED60; - __IM uint32_t RESERVED61[15]; - - union - { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ - - struct - { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; - }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ - -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ - union - { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ - - struct - { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; - }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ - -typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ -{ - union - { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; - }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ - -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } DVCHGR_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ - uint16_t : 4; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - - union - { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - - struct - { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; - - union - { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ - - struct - { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ - - struct - { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; - - union - { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ - - struct - { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct - { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED23[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED25[5]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - __IM uint32_t RESERVED26[165]; - - union - { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ - - struct - { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union - { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ - - struct - { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ - -typedef struct /*!< (@ 0x40083400) R_WDT Structure */ -{ - union - { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ - - struct - { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; - }; - - union - { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; - }; - - union - { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/** - * @brief TrustZone Filter (R_TZF) - */ - -typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ -{ - union - { - __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFPT_b; - }; -} R_TZF_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief R_CACHE (R_CACHE) - */ - -typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ -{ - union - { - __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ - - struct - { - __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ - uint32_t : 31; - } CCACTL_b; - }; - - union - { - __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ - uint32_t : 31; - } CCAFCT_b; - }; - - union - { - __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ - uint32_t : 30; - } CCALCF_b; - }; - __IM uint32_t RESERVED[13]; - - union - { - __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ - - struct - { - __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ - uint32_t : 31; - } SCACTL_b; - }; - - union - { - __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ - uint32_t : 31; - } SCAFCT_b; - }; - - union - { - __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ - uint32_t : 30; - } SCALCF_b; - }; - __IM uint32_t RESERVED1[109]; - - union - { - __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection - * Register */ - - struct - { - __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint32_t : 31; - } CAPOAD_b; - }; - - union - { - __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ - - struct - { - __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ - __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ - uint32_t : 24; - } CAPRCR_b; - }; -} R_CACHE_Type; /*!< Size = 520 (0x208) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU System Security Control Unit (R_CPSCU) - */ - -typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ -{ - union - { - __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ - - struct - { - __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ - __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ - __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ - uint32_t : 29; - } CSAR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ - - struct - { - __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ - __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection - * 2 */ - __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ - uint32_t : 29; - } SRAMSAR_b; - }; - - union - { - __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ - - struct - { - __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ - uint32_t : 28; - } STBRAMSAR_b; - }; - __IM uint32_t RESERVED1[6]; - - union - { - __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ - uint32_t : 31; - } DTCSAR_b; - }; - - union - { - __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ - uint32_t : 31; - } DMACSAR_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ - - struct - { - __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ - uint32_t : 16; - } ICUSARA_b; - }; - - union - { - __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ - - struct - { - __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ - uint32_t : 31; - } ICUSARB_b; - }; - - union - { - __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ - - struct - { - __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ - uint32_t : 24; - } ICUSARC_b; - }; - - union - { - __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ - - struct - { - __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ - uint32_t : 31; - } ICUSARD_b; - }; - - union - { - __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ - - struct - { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 2; - __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ - } ICUSARE_b; - }; - - union - { - __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ - - struct - { - __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ - __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ - __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ - __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 3; - __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ - __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ - __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ - __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ - __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ - __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ - __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ - __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ - uint32_t : 17; - } ICUSARF_b; - }; - - union - { - __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ - - struct - { - __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ - __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ - __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ - __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ - __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ - __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ - __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ - uint32_t : 25; - } ICUSARM_b; - }; - __IM uint32_t RESERVED3[5]; - - union - { - __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ - } ICUSARG_b; - }; - - union - { - __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ - } ICUSARH_b; - }; - - union - { - __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ - } ICUSARI_b; - }; - __IM uint32_t RESERVED4[33]; - - union - { - __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ - - struct - { - __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ - uint32_t : 31; - } BUSSARA_b; - }; - - union - { - __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ - - struct - { - __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ - uint32_t : 31; - } BUSSARB_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ - - struct - { - __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ - uint32_t : 31; - } BUSSARC_b; - }; - - union - { - __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ - - struct - { - __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ - uint32_t : 31; - } BUSPARC_b; - }; - __IM uint32_t RESERVED6[6]; - - union - { - __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution - * Register A */ - - struct - { - __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ - uint32_t : 24; - } MMPUSARA_b; - }; - - union - { - __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution - * Register B */ - - struct - { - __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ - uint32_t : 31; - } MMPUSARB_b; - }; - __IM uint32_t RESERVED7[18]; - - union - { - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; - - union - { - __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ - - struct - { - __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ - uint32_t : 31; - } DEBUGSAR_b; - }; - }; - __IM uint32_t RESERVED8[7]; - - union - { - __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ - - struct - { - __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ - uint32_t : 24; - } DMACCHSAR_b; - }; - __IM uint32_t RESERVED9[3]; - - union - { - __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ - - struct - { - __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ - uint32_t : 31; - } CPUDSAR_b; - }; - __IM uint32_t RESERVED10[147]; - - union - { - __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register - * 0 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR0_b; - }; - - union - { - __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register - * 1 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR1_b; - }; - __IM uint32_t RESERVED11[126]; - - union - { - __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ - - struct - { - __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn - * and ELCSRn */ - uint32_t : 31; - } TEVTRCR_b; - }; -} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Consumer Electronics Control (R_CEC) - */ - -typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ -{ - union - { - __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ - - struct - { - __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ - __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device - * 1) */ - __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device - * 2) */ - __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ - __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ - __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ - __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ - __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ - __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ - __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device - * 3) */ - __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ - __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device - * 3) */ - __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ - __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ - __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ - uint16_t : 1; - } CADR_b; - }; - - union - { - __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ - - struct - { - __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ - __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing - * Select */ - __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ - __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ - __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ - __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ - } CECCTL1_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ - - struct - { - __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ - uint16_t : 7; - } STATB_b; - }; - - union - { - __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ - uint16_t : 7; - } STATL_b; - }; - - union - { - __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ - uint16_t : 7; - } LGC0L_b; - }; - - union - { - __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ - uint16_t : 7; - } LGC1L_b; - }; - - union - { - __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ - - struct - { - __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ - uint16_t : 7; - } DATB_b; - }; - - union - { - __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ - - struct - { - __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ - uint16_t : 7; - } NOMT_b; - }; - - union - { - __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ - uint16_t : 7; - } STATLL_b; - }; - - union - { - __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATLH_b; - }; - - union - { - __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ - uint16_t : 7; - } STATBL_b; - }; - - union - { - __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATBH_b; - }; - - union - { - __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LL_b; - }; - - union - { - __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LH_b; - }; - - union - { - __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ - uint16_t : 7; - } LGC1LL_b; - }; - - union - { - __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ - uint16_t : 7; - } LGC1LH_b; - }; - - union - { - __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ - uint16_t : 7; - } DATBL_b; - }; - - union - { - __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ - uint16_t : 7; - } DATBH_b; - }; - - union - { - __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ - - struct - { - __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ - uint16_t : 7; - } NOMP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ - __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ - uint8_t : 1; - __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ - } CECEXMD_b; - }; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ - - struct - { - __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ - __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ - uint8_t : 6; - } CECEXMON_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[10]; - __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ - __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ - - union - { - __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ - - struct - { - __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ - __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ - __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ - __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ - __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ - __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ - __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ - uint8_t : 1; - } CECES_b; - }; - - union - { - __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ - - struct - { - __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ - __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ - __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ - __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ - __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ - uint8_t : 2; - __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ - } CECS_b; - }; - - union - { - __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ - - struct - { - __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ - __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ - __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ - __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ - __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ - __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ - __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ - uint8_t : 1; - } CECFC_b; - }; - - union - { - __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ - - struct - { - __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ - __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ - __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ - __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ - __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ - __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ - } CECCTL0_b; - }; -} R_CEC_Type; /*!< Size = 70 (0x46) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Octa Serial Peripheral Interface (R_OSPI) - */ - -typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ -{ - union - { - __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ - - struct - { - __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ - __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ - uint32_t : 16; - } DCR_b; - }; - - union - { - __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ - - struct - { - __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ - __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ - __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ - __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ - } DAR_b; - }; - - union - { - __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ - - struct - { - __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ - __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ - uint32_t : 3; - __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ - __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ - __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ - __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ - __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ - __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ - __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ - uint32_t : 2; - } DCSR_b; - }; - - union - { - __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ - - struct - { - __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ - __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ - } DSR_b[2]; - }; - - union - { - __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ - - struct - { - __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ - __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ - __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ - __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ - __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ - uint32_t : 4; - } MDTR_b; - }; - - union - { - __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ - - struct - { - __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ - } ACTR_b; - }; - - union - { - __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ - - struct - { - __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ - } ACAR_b[2]; - }; - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ - __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ - __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ - __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ - __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DRCSTR_b; - }; - - union - { - __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ - __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ - __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ - __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ - __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DWCSTR_b; - }; - - union - { - __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ - __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ - __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ - uint32_t : 16; - } DCSTR_b; - }; - - union - { - __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ - - struct - { - __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ - __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ - __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ - __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ - uint32_t : 4; - __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device - * 0 */ - __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device - * 1 */ - __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ - uint32_t : 17; - __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ - } CDSR_b; - }; - - union - { - __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ - - struct - { - __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ - __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ - __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ - __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ - } MDLR_b; - }; - - union - { - __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ - - struct - { - __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ - __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ - __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ - __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ - } MRWCR_b[2]; - }; - - union - { - __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ - - struct - { - __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ - __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ - __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ - __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ - __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ - __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ - __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ - uint32_t : 1; - __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ - __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ - __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ - __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ - __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ - __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ - __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ - uint32_t : 1; - } MRWCSR_b; - }; - - union - { - __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ - - struct - { - __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ - __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ - uint32_t : 16; - } ESR_b; - }; - - union - { - __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ - - struct - { - __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ - } CWNDR_b; - }; - - union - { - __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ - - struct - { - __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ - __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ - __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ - __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ - } CWDR_b; - }; - - union - { - __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ - - struct - { - __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ - __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ - __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ - __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ - } CRR_b; - }; - - union - { - __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ - - struct - { - __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ - __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ - uint32_t : 26; - } ACSR_b; - }; - __IM uint32_t RESERVED1[5]; - - union - { - __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ - - struct - { - __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are - * Low in single continuous write of OctaRAM. */ - uint32_t : 7; - __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 - * are Low in single continuous read of OctaRAM. */ - uint32_t : 7; - } DCSMXR_b; - }; - - union - { - __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating - * size Register */ - - struct - { - __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single - * continuous write of device 0. */ - uint32_t : 5; - __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single - * continuous write of device 1. */ - uint32_t : 5; - } DWSCTSR_b; - }; -} R_OSPI_Type; /*!< Size = 132 (0x84) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 High-Speed Module (R_USB_HS0) - */ - -typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ - uint16_t : 7; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller - * Operation */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit - * when switching from device B to device A in OTGmode. If - * the HNPBTOA bit is 1, the internal function controlremains - * in the Suspend state until the HNP processing endseven - * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } CFIFO_b; - }; - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } D0FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write - * transmit data to the FIFO buffer by accessing these bits. */ - } D1FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-11 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be - * set only in the initial setting (before communications).The - * setting cannot be changed once communication starts. */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency - * can be improved by setting this bit to 1 if no low-speed - * device is connected directly or via FS-HUB to the USB port. */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ - - struct - { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected - * : read-only Host controller selected : read-write */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected - * : read-only Host controller selected : read-write */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected - * : read-only Host controller selected : read-write */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected - * : read-only Host controller selected : read-write */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected - * : read-only Host controller selected : read-write */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * destination function device for control transfer when the - * host controller function is selected. */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - - union - { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ - - struct - { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number - * of the selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - uint16_t : 1; - } PIPEBUF_b; - }; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the selected pipe.A size - * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * peripheral device when the host controller function is - * selected. */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the - * transfer interval timing for the selected pipe as n-th - * power of 2 of the frame timing. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for - * the next transaction of the relevant pipe. */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe - * is being used for the USB bus */ - __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is set for DATA1 */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is cleared to DATA0 */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto - * buffer clear mode for the relevant pipe */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto - * response mode for the relevant pipe. */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO - * buffer status for the relevant pipe in the transmitting - * direction. */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status - * for the relevant pipe. */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED14[11]; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED15[7]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED16[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED17; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ - - struct - { - __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset - * value for adjusting the terminating resistance. */ - uint16_t : 1; - } PHYTRIM1_b; - }; - - union - { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ - - struct - { - __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ - uint16_t : 1; - } PHYTRIM2_b; - }; - __IM uint32_t RESERVED19[3]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; -} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGTX0) - */ - -typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ -{ - union - { - __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ - __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ - }; -} R_AGTX0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CANFD ECC (R_ECCMB0) - */ - -typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ -{ - union - { - __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ - - struct - { - __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ - __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ - __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ - __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ - __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ - __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ - __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ - uint32_t : 2; - __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag - * Clear */ - __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ - __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ - uint32_t : 2; - __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ - __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ - __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ - uint32_t : 14; - } EC710CTL_b; - }; - - union - { - __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ - uint16_t : 5; - __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ - uint16_t : 6; - __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ - } EC710TMC_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ - - struct - { - __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ - } EC710TED_b; - }; - - union - { - __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ - - struct - { - __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ - uint32_t : 22; - } EC710EAD0_b; - }; -} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Flash (R_FLAD) - */ - -typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ -{ - __IM uint8_t RESERVED[64]; - - union - { - __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ - - struct - { - __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ - } FCKMHZ_b; - }; -} R_FLAD_Type; /*!< Size = 65 (0x41) */ - -/** @} */ /* End of group Device_Peripheral_peripherals */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ADC0_BASE 0x40170000UL - #define R_ADC1_BASE 0x40170200UL - #define R_PSCU_BASE 0x400E0000UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40083600UL - #define R_CANFD_BASE 0x400B0000UL - #define R_CRC_BASE 0x40108000UL - #define R_CTSU_BASE 0x400D0000UL - #define R_DAC_BASE 0x40171000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40109000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40082000UL - #define R_ETHERC0_BASE 0x40114100UL - #define R_ETHERC_EDMAC_BASE 0x40114000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GPT0_BASE 0x40169000UL - #define R_GPT1_BASE 0x40169100UL - #define R_GPT2_BASE 0x40169200UL - #define R_GPT3_BASE 0x40169300UL - #define R_GPT4_BASE 0x40169400UL - #define R_GPT5_BASE 0x40169500UL - #define R_GPT6_BASE 0x40169600UL - #define R_GPT7_BASE 0x40169700UL - #define R_GPT8_BASE 0x40169800UL - #define R_GPT9_BASE 0x40169900UL - #define R_GPT10_BASE 0x40169A00UL - #define R_GPT11_BASE 0x40169B00UL - #define R_GPT12_BASE 0x40169C00UL - #define R_GPT13_BASE 0x40169D00UL - #define R_GPT_OPS_BASE 0x40169A00UL - #define R_GPT_POEG0_BASE 0x4008A000UL - #define R_GPT_POEG1_BASE 0x4008A100UL - #define R_GPT_POEG2_BASE 0x4008A200UL - #define R_GPT_POEG3_BASE 0x4008A300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x4009F000UL - #define R_IIC1_BASE 0x4009F100UL - #define R_IIC2_BASE 0x4009F200UL - #define R_IWDT_BASE 0x40083200UL - #define R_I3C0_BASE 0x4011F000UL - #define R_I3C1_BASE 0x4011F400UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40084000UL - #define R_PORT0_BASE 0x40080000UL - #define R_PORT1_BASE 0x40080020UL - #define R_PORT2_BASE 0x40080040UL - #define R_PORT3_BASE 0x40080060UL - #define R_PORT4_BASE 0x40080080UL - #define R_PORT5_BASE 0x400800A0UL - #define R_PORT6_BASE 0x400800C0UL - #define R_PORT7_BASE 0x400800E0UL - #define R_PORT8_BASE 0x40080100UL - #define R_PORT9_BASE 0x40080120UL - #define R_PORT10_BASE 0x40080140UL - #define R_PORT11_BASE 0x40080160UL - #define R_PORT12_BASE 0x40080180UL - #define R_PORT13_BASE 0x400801A0UL - #define R_PORT14_BASE 0x400801C0UL - #define R_PFS_BASE 0x40080800UL - #define R_PMISC_BASE 0x40080D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40083000UL - #define R_SCI0_BASE 0x40118000UL - #define R_SCI1_BASE 0x40118100UL - #define R_SCI2_BASE 0x40118200UL - #define R_SCI3_BASE 0x40118300UL - #define R_SCI4_BASE 0x40118400UL - #define R_SCI5_BASE 0x40118500UL - #define R_SCI6_BASE 0x40118600UL - #define R_SCI7_BASE 0x40118700UL - #define R_SCI8_BASE 0x40118800UL - #define R_SCI9_BASE 0x40118900UL - #define R_SDHI0_BASE 0x40092000UL - #define R_SDHI1_BASE 0x40092400UL - #define R_SPI0_BASE 0x4011A000UL - #define R_SPI1_BASE 0x4011A100UL - #define R_SPI2_BASE 0x40072200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SSI0_BASE 0x4009D000UL - #define R_SSI1_BASE 0x4009D100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x400F3000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_WDT_BASE 0x40083400UL - #define R_TZF_BASE 0x40000E00UL - #define R_CACHE_BASE 0x40007000UL - #define R_CPSCU_BASE 0x40008000UL - #define R_CEC_BASE 0x400AC000UL - #define R_OSPI_BASE 0x400A6000UL - #define R_USB_HS0_BASE 0x40111000UL - #define R_AGTX0_BASE 0x400E8000UL - #define R_AGTX1_BASE 0x400E8100UL - #define R_AGTX2_BASE 0x400E8200UL - #define R_AGTX3_BASE 0x400E8300UL - #define R_AGTX4_BASE 0x400E8400UL - #define R_AGTX5_BASE 0x400E8500UL - #define R_AGTX6_BASE 0x400E8600UL - #define R_AGTX7_BASE 0x400E8700UL - #define R_AGTX8_BASE 0x400E8800UL - #define R_AGTX9_BASE 0x400E8900UL - #define R_ECCMB0_BASE 0x4036F200UL - #define R_ECCMB1_BASE 0x4036F300UL - #define R_FLAD_BASE 0x407FC000UL - #define R_WDT1_BASE 0x40044300UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) - #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) - #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) - #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - #define R_TZF ((R_TZF_Type *) R_TZF_BASE) - #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) - #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) - #define R_CEC ((R_CEC_Type *) R_CEC_BASE) - #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) - #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) - #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) - #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) - #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) - #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) - #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) - #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) - #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) - #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) - #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) - #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) - #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) - #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - -/* ========================================= End of section using anonymous unions ========================================= */ - #if defined(__CC_ARM) - #pragma pop - #elif defined(__ICCARM__) - -/* leave anonymous unions enabled */ - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning restore - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #endif - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_clusters - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ SDRAM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SDCCR ========================================================= */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCMOD ========================================================= */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDAMOD ========================================================= */ - #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ - #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDSELF ========================================================= */ - #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ - #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDRFCR ========================================================= */ - #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ - #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ -/* ======================================================== SDRFEN ========================================================= */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ -/* ========================================================= SDICR ========================================================= */ - #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ - #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SDIR ========================================================== */ - #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ - #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ - #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ - #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ -/* ========================================================= SDADR ========================================================= */ - #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ - #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ -/* ========================================================= SDTR ========================================================== */ - #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ - #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ - #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ - #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ - #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ - #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ -/* ========================================================= SDMOD ========================================================= */ - #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ - #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ -/* ========================================================= SDSR ========================================================== */ - #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ - #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ - #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ - #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= IRQEN ========================================================= */ - #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ - #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ DMACDTCERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FLBI ========================================================== */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== MRE0BI ========================================================= */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S2BI ========================================================== */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S3BI ========================================================== */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== STBYSBI ======================================================== */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= ECBI ========================================================== */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= EOBI ========================================================== */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI0BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI1BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PBBI ========================================================== */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PABI ========================================================== */ - #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PIBI ========================================================== */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PSBI ========================================================== */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU0SAHBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT1 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FHBI ========================================================== */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ======================================================== MRC0BI ========================================================= */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ BMSAERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ - #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ OAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BUSOAD ========================================================= */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSOADPT ======================================================== */ - #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== MSAOAD ========================================================= */ - #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= MSAPT ========================================================= */ - #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ MBWERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ - #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ - #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ - #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ ELSEGR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== BY =========================================================== */ - #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ - #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ - #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ - #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ ELSR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== HA =========================================================== */ - #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ - #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ SAR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== L =========================================================== */ - #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ - #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ -/* =========================================================== U =========================================================== */ - #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ - #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ - #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ REGION ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AC =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ -/* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ GROUP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== EN =========================================================== */ - #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= ENPT ========================================================== */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== RPT ========================================================== */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== RPT_SEC ======================================================== */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================== CTL ========================================================== */ - #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ - #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== SA =========================================================== */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== EA =========================================================== */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ PIN ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= PmnPFS_BY ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ======================================================= PmnPFS_HA ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ -/* ======================================================== PmnPFS ========================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PORT ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PMSAR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PMSAR ========================================================= */ - -/* =========================================================================================================================== */ -/* ================ RTCCR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RTCCR ========================================================= */ - #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ - #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ - #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ - #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RSEC ========================================================== */ - #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ - #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMIN ========================================================== */ - #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ - #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ -/* ========================================================== RHR ========================================================== */ - #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ - #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RDAY ========================================================== */ - #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ - #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMON ========================================================== */ - #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= AGTCR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTMR1 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ -/* ======================================================== AGTMR2 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ -/* ===================================================== AGTIOSEL_ALT ====================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ -/* ======================================================== AGTIOC ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTISR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTCMSR ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ -/* ======================================================= AGTIOSEL ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ AGT16 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ AGT32 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ - -/** @} */ /* End of group PosMask_clusters */ - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ADCSR ========================================================= */ - #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ - #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ - #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ - #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ - #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ - #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ - #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ - #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ - #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ - #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSA ========================================================= */ - #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ - #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADS ========================================================= */ - #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ - #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADC ========================================================= */ - #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ - #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ - #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ -/* ========================================================= ADCER ========================================================= */ - #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ - #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ - #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ - #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ - #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ - #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ - #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ - #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ - #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSTRGR ======================================================== */ - #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ - #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ - #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ - #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ -/* ======================================================== ADEXICR ======================================================== */ - #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ - #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ - #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ - #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ - #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ - #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ - #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ - #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ - #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSB ========================================================= */ - #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ - #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADDBLDR ======================================================== */ - #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ - #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADTSDR ========================================================= */ - #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ - #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADOCDR ========================================================= */ - #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ - #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADRD_RIGHT ======================================================= */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ -/* ======================================================= ADRD_LEFT ======================================================= */ - #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ - #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ========================================================= ADDR ========================================================== */ - #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ - #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADSHCR ========================================================= */ - #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ - #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ - #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ - #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ - #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ -/* ======================================================== ADDISCR ======================================================== */ - #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ - #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ - #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADSHMSR ======================================================== */ - #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ - #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADACSR ========================================================= */ - #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ - #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ -/* ======================================================== ADGSPCR ======================================================== */ - #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ - #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ - #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ - #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ -/* ========================================================= ADICR ========================================================= */ - #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ - #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ -/* ======================================================= ADDBLDRA ======================================================== */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADDBLDRB ======================================================== */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADHVREFCNT ======================================================= */ - #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= ADWINMON ======================================================== */ - #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ - #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ - #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ - #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPCR ======================================================== */ - #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ - #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ - #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ - #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ - #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ - #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ - #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCMPANSER ======================================================= */ - #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ - #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPLER ======================================================== */ - #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ - #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPANSR ======================================================= */ - #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ - #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPLR ======================================================== */ - #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ - #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPDR0 ======================================================== */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPDR1 ======================================================== */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADCMPSR ======================================================== */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPSER ======================================================== */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPBNSR ======================================================= */ - #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ - #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ -/* ======================================================= ADWINLLB ======================================================== */ - #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ - #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADWINULB ======================================================== */ - #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ - #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPBSR ======================================================== */ - #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ - #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSSTRL ======================================================== */ - #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRT ======================================================== */ - #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRO ======================================================== */ - #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTR ========================================================= */ - #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADPGACR ======================================================== */ - #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ - #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ - #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ - #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ - #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ - #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ - #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ - #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ - #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ - #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ - #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ - #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ - #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ - #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ - #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ - #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ - #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADRD ========================================================== */ - #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ -/* ========================================================= ADRST ========================================================= */ - #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ====================================================== VREFAMPCNT ======================================================= */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ - #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCALEXE ======================================================== */ - #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ - #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ - #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANIM ========================================================= */ - #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ - #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGAGS0 ======================================================== */ - #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ - #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= ADPGADCR0 ======================================================= */ - #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ - #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ - #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ - #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ - #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ - #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ - #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ - #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ - #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADREF ========================================================= */ - #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ - #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ - #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ -/* ======================================================== ADEXREF ======================================================== */ - #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ - #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADAMPOFF ======================================================== */ - #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ - #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ -/* ======================================================== ADTSTPR ======================================================== */ - #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ - #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ - #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================= ADDDACER ======================================================== */ - #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ - #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ - #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ - #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADEXTSTR ======================================================== */ - #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ - #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ - #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ - #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ -/* ======================================================== ADTSTRA ======================================================== */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ - #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ - #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADTSTRB ======================================================== */ - #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ - #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ -/* ======================================================== ADTSTRC ======================================================== */ - #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ - #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ - #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ADTSTRD ======================================================== */ - #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ - #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR0 ======================================================= */ - #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ - #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR1 ======================================================= */ - #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ - #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR2 ======================================================= */ - #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ - #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSWCR ========================================================= */ - #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ - #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ - #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ -/* ======================================================== ADGSCS ========================================================= */ - #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ - #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ - #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ -/* ========================================================= ADSER ========================================================= */ - #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ - #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ -/* ======================================================== ADBUF0 ========================================================= */ - #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF1 ========================================================= */ - #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF2 ========================================================= */ - #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF3 ========================================================= */ - #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF4 ========================================================= */ - #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF5 ========================================================= */ - #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF6 ========================================================= */ - #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF7 ========================================================= */ - #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF8 ========================================================= */ - #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF9 ========================================================= */ - #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF10 ======================================================== */ - #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF11 ======================================================== */ - #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF12 ======================================================== */ - #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF13 ======================================================== */ - #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF14 ======================================================== */ - #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF15 ======================================================== */ - #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUFEN ======================================================== */ - #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ - #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADBUFPTR ======================================================== */ - #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ - #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ - #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS0 ======================================================= */ - #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS1 ======================================================= */ - #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADREFMON ======================================================== */ - #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ - #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ - #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ - #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ - #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ - #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ - #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ - #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ - #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ - #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ - #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ - #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ - #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ - #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ - #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ - #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ - #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ - #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ - #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ - #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ - #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ - #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ - #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ - #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ - #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ - #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ - #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ - #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ - #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ -/* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ - #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ - #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ - #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ -/* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ -/* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ -/* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ - #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ -/* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ - #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSMABT ======================================================== */ - #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSDIVBYP ======================================================= */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSTHRPUT ======================================================= */ - #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ - #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CACR0 ========================================================= */ - #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ - #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR1 ========================================================= */ - #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ - #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ - #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ - #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR2 ========================================================= */ - #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ - #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ - #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ - #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ - #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ -/* ========================================================= CAICR ========================================================= */ - #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ - #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ - #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ - #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ - #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ - #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ - #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ -/* ========================================================= CASTR ========================================================= */ - #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ - #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ - #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ - #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ -/* ======================================================== CAULVR ========================================================= */ - #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ - #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CALLVR ========================================================= */ - #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ - #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CACNTBR ======================================================== */ - #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ - #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CRCCR0 ========================================================= */ - #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ - #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ - #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ - #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ -/* ======================================================== CRCCR1 ========================================================= */ - #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ - #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ - #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CRCDIR ========================================================= */ - #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ - #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDIR_BY ======================================================= */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCDOR ========================================================= */ - #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ - #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDOR_HA ======================================================= */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ -/* ======================================================= CRCDOR_BY ======================================================= */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCSAR ========================================================= */ - #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ - #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTSUCR0 ======================================================== */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ -/* ======================================================== CTSUCR1 ======================================================== */ - #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ - #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ - #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUSDPRS ======================================================= */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSST ======================================================== */ - #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ - #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ -/* ======================================================= CTSUMCH0 ======================================================== */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUMCH1 ======================================================== */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUCHAC ======================================================== */ - #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUCHTRC ======================================================= */ - #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUDCLKC ======================================================= */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== CTSUST ========================================================= */ - #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ - #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ - #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ - #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ - #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ - #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ -/* ======================================================== CTSUSSC ======================================================== */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSO0 ======================================================== */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ - #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ - #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ -/* ======================================================== CTSUSO1 ======================================================== */ - #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ - #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ -/* ======================================================== CTSUSC ========================================================= */ - #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ - #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ -/* ======================================================== CTSURC ========================================================= */ - #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ - #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ -/* ======================================================= CTSUERRS ======================================================== */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUTRMR ======================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DACR ========================================================== */ - #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ - #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ - #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ - #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ -/* ========================================================= DADR ========================================================== */ - #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ - #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DADPR ========================================================= */ - #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ - #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADSCR ======================================================== */ - #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ - #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ -/* ======================================================= DAVREFCR ======================================================== */ - #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ - #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ -/* ========================================================= DAPC ========================================================== */ - #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ - #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== DAAMPCR ======================================================== */ - #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ - #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DAASWCR ======================================================== */ - #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ - #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ - #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ - #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== DBGSTR ========================================================= */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ -/* ======================================================= DBGSTOPCR ======================================================= */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ -/* ======================================================= FSBLSTAT ======================================================== */ - #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ - #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ -/* ======================================================== DMECHR ========================================================= */ - #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ - #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ - #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ - #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ - #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ -/* ========================================================= DELSR ========================================================= */ - #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMSAR ========================================================= */ - #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ - #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMDAR ========================================================= */ - #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ - #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCRA ========================================================= */ - #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ - #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ - #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ - #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMCRB ========================================================= */ - #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ - #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ - #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMTMD ========================================================= */ - #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ - #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ - #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ - #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ - #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ - #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ -/* ========================================================= DMINT ========================================================= */ - #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ - #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ - #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ - #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ - #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ - #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMAMD ========================================================= */ - #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ - #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ - #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ - #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ - #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ - #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ - #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ -/* ========================================================= DMOFR ========================================================= */ - #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ - #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCNT ========================================================= */ - #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ - #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMREQ ========================================================= */ - #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ - #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ - #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSTS ========================================================= */ - #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ - #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ - #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ - #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSRR ========================================================= */ -/* ========================================================= DMDRR ========================================================= */ -/* ========================================================= DMSBS ========================================================= */ - #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ - #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ - #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMDBS ========================================================= */ - #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ - #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ - #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMBWR ========================================================= */ - #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ - #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DOCR ========================================================== */ - #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ - #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ - #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ - #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ - #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ -/* ========================================================= DODIR ========================================================= */ - #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ - #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DODSR ========================================================= */ - #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ - #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= DTCADMOD ======================================================== */ - #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ - #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ -/* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ -/* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ====================================================== DTCVBR_SEC ======================================================= */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DTCDISP ======================================================== */ - #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ - #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCIBR ========================================================= */ - #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ - #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ -/* ========================================================= DTCOR ========================================================= */ - #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ - #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSQE ========================================================= */ - #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ - #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARA ======================================================== */ - #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ - #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ - #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ - #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARB ======================================================== */ - #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ - #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ - #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ - #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ - #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ - #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ - #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ - #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ - #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ - #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ - #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ - #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ - #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ - #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ - #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ - #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ - #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARC ======================================================== */ - #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ - #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ - #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ - #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ECMR ========================================================== */ - #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ - #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ - #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ - #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ - #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ - #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ - #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ - #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ - #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ - #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ - #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ - #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ - #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ -/* ========================================================= RFLR ========================================================== */ - #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ - #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ - #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ - #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ - #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ - #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ - #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ -/* ======================================================== ECSIPR ========================================================= */ - #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ - #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ - #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ - #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ -/* ========================================================== PIR ========================================================== */ - #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ - #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ - #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ - #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ - #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ -/* ========================================================== PSR ========================================================== */ - #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ - #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ -/* ========================================================= RDMLR ========================================================= */ - #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ - #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ -/* ========================================================= IPGR ========================================================== */ - #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ - #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ -/* ========================================================== APR ========================================================== */ - #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ - #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ -/* ========================================================== MPR ========================================================== */ - #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ - #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFCF ========================================================== */ - #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ - #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ -/* ======================================================== TPAUSER ======================================================== */ - #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ - #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ -/* ======================================================= TPAUSECR ======================================================== */ -/* ========================================================= BCFRR ========================================================= */ - #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ - #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ -/* ========================================================= MAHR ========================================================== */ - #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ - #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MALR ========================================================== */ - #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ - #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ -/* ========================================================= TROCR ========================================================= */ - #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ - #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CDCR ========================================================== */ -/* ========================================================= LCCR ========================================================== */ - #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ - #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CNDCR ========================================================= */ - #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ - #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CEFCR ========================================================= */ - #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ - #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= FRECR ========================================================= */ - #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ - #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TSFRCR ========================================================= */ - #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ - #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TLFRCR ========================================================= */ - #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ - #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RFCR ========================================================== */ - #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ - #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MAFCR ========================================================= */ - #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ - #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= EDMR ========================================================== */ - #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ - #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ - #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDTRR ========================================================= */ - #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ - #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDRRR ========================================================= */ - #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ - #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ -/* ========================================================= TDLAR ========================================================= */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDLAR ========================================================= */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= EESR ========================================================== */ - #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ - #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ - #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ - #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ - #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ - #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ - #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ - #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ - #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ - #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ - #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ - #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ - #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ - #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ - #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ - #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ - #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ -/* ======================================================== EESIPR ========================================================= */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ -/* ======================================================== TRSCER ========================================================= */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ -/* ========================================================= RMFCR ========================================================= */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= TFTR ========================================================== */ - #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ - #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ -/* ========================================================== FDR ========================================================== */ - #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ - #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ - #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ - #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ -/* ========================================================= RMCR ========================================================== */ - #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ - #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ -/* ========================================================= TFUCR ========================================================= */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFOCR ========================================================= */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ -/* ========================================================= IOSR ========================================================== */ - #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ - #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ -/* ========================================================= FCFTR ========================================================= */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ -/* ======================================================== RPADIR ========================================================= */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ -/* ========================================================= TRIMD ========================================================= */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ -/* ========================================================= RBWAR ========================================================= */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDFAR ========================================================= */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TBRAR ========================================================= */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TDFAR ========================================================= */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/* ====================================================== FACI_CMD16 ======================================================= */ -/* ======================================================= FACI_CMD8 ======================================================= */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ -/* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FMEPROT ======================================================== */ - #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ - #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT0 ======================================================== */ - #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ - #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT1 ======================================================== */ - #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ - #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ - #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ - #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ - #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ -/* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ -/* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ -/* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ -/* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ -/* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ -/* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== FBCADDR ======================================================== */ - #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ - #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ -/* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ -/* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ -/* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ -/* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ -/* ======================================================= FCNTSELR ======================================================== */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ -/* ====================================================== FCNTDATAR0 ======================================================= */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FCNTDATAR1 ======================================================= */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ -/* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ -/* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ -/* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ - #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ - #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ - #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ - #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= GTWP ========================================================== */ - #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ - #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ - #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ - #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ - #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTR ========================================================= */ - #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ - #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTP ========================================================= */ - #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ - #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCLR ========================================================= */ - #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ - #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSSR ========================================================= */ - #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ - #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ - #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ - #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ - #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ - #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ - #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ - #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ - #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ - #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ - #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ - #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ - #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTPSR ========================================================= */ - #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ - #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ - #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ - #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ - #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ - #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ - #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ - #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ - #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ - #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ - #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ - #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ - #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCSR ========================================================= */ - #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ - #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ - #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ - #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ - #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ - #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ - #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ - #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ - #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ - #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ - #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ - #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ - #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ - #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ - #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTUPSR ========================================================= */ - #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ - #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ - #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ - #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ - #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ - #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ - #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ - #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ - #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ - #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ - #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ - #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ - #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTDNSR ========================================================= */ - #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ - #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ - #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ - #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ - #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ - #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ - #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ - #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ - #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ - #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ - #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ - #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ - #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICASR ======================================================== */ - #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ - #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ - #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ - #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ - #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ - #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ - #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ - #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ - #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ - #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ - #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ - #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ - #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICBSR ======================================================== */ - #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ - #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ - #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ - #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ - #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ - #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ - #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ - #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ - #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ - #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ - #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ - #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ - #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ - #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ - #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ - #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ - #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ - #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ - #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ - #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ - #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ - #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ - #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ -/* ======================================================= GTUDDTYC ======================================================== */ - #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ - #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ - #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ - #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ - #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ - #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ - #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ - #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ -/* ========================================================= GTIOR ========================================================= */ - #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ - #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ - #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ - #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ - #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ - #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ - #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ - #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ - #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ - #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ - #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ - #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ - #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ - #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ - #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ - #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ - #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ - #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ - #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTINTAD ======================================================== */ - #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ - #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ - #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ - #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ - #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ - #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ - #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ - #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ - #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ - #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ - #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ - #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTST ========================================================== */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ - #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ - #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ - #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ - #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ - #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ - #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ - #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ - #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ - #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ - #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ - #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ - #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ - #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ - #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ - #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ - #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ - #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ - #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTBER ========================================================= */ - #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ - #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ - #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ - #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ - #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ - #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ - #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ - #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ - #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ - #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ - #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ - #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ - #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ - #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ -/* ========================================================= GTITC ========================================================= */ - #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ - #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ - #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ - #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ - #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ - #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ - #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ - #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ - #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ - #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ - #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCNT ========================================================= */ - #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ - #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTCCR ========================================================= */ - #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ - #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPR ========================================================== */ - #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ - #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPBR ========================================================= */ - #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ - #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTPDBR ========================================================= */ - #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ - #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRA ======================================================== */ - #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ - #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRB ======================================================== */ - #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ - #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRA ======================================================== */ - #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ - #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRB ======================================================== */ - #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ - #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRA ======================================================= */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRB ======================================================= */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTDTCR ========================================================= */ - #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ - #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ - #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ - #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ - #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ -/* ========================================================= GTDVU ========================================================= */ - #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDVD ========================================================= */ - #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ - #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBU ========================================================= */ - #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBD ========================================================= */ - #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ - #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTSOS ========================================================= */ - #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ - #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ -/* ======================================================== GTSOTR ========================================================= */ - #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ - #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTADSMR ======================================================== */ - #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ - #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ - #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ - #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ - #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTEITC ========================================================= */ - #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ - #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ - #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ - #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ - #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ - #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ - #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ - #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= GTEITLI1 ======================================================== */ - #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ - #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ - #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ - #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ - #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ - #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ - #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ - #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ - #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ -/* ======================================================= GTEITLI2 ======================================================== */ - #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ - #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ - #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ -/* ======================================================== GTEITLB ======================================================== */ - #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ - #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ - #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ - #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ - #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ - #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ - #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ - #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ -/* ======================================================== GTICLF ========================================================= */ - #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ - #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ - #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ - #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ - #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ - #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ -/* ========================================================= GTPC ========================================================== */ - #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ - #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ - #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ - #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ -/* ======================================================= GTADCMSC ======================================================== */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ - #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ - #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ -/* ======================================================= GTADCMSS ======================================================== */ - #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ - #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ -/* ======================================================== GTSECSR ======================================================== */ - #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ - #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ - #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ - #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ - #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ - #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ - #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ - #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ - #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ - #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ - #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTSECR ========================================================= */ - #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ - #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ - #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ - #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ - #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ - #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ - #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ - #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ - #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ - #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ - #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ - #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ - #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ -/* ======================================================== GTBER2 ========================================================= */ - #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ - #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ - #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ - #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ - #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ - #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ - #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ - #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ - #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ - #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ - #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ - #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ - #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ - #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ - #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ - #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ - #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ - #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ - #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ - #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ - #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ -/* ======================================================== GTOLBR ========================================================= */ - #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ - #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ - #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTICCR ========================================================= */ - #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ - #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ - #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ - #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ - #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ - #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ - #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ - #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ - #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ - #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ - #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ - #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ - #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ - #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ - #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ - #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ - #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ - #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ - #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ - #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ - #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= OPSCR ========================================================= */ - #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ - #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ - #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ - #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ - #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ - #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ - #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ - #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ - #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ - #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ - #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ - #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ - #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ - #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ - #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ -/* ======================================================== GTONCWP ======================================================== */ - #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== GTONCCR ======================================================== */ - #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ - #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ - #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ - #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ - #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ - #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ -/* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ -/* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ -/* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ -/* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ -/* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN2 ========================================================= */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ICCR1 ========================================================= */ - #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ - #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ - #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ - #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ - #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ - #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ - #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ - #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ - #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ -/* ========================================================= ICCR2 ========================================================= */ - #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ - #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ - #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ - #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ - #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ - #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ - #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR1 ========================================================= */ - #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ - #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ - #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ - #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ -/* ========================================================= ICMR2 ========================================================= */ - #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ - #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ - #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ - #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ - #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ - #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR3 ========================================================= */ - #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ - #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ - #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ - #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ - #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ - #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ - #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ - #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ -/* ========================================================= ICFER ========================================================= */ - #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ - #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ - #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ - #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ - #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ - #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ - #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ - #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ - #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSER ========================================================= */ - #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ - #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ - #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ - #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ - #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ - #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ - #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ -/* ========================================================= ICIER ========================================================= */ - #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ - #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ - #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ - #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ - #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ - #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ - #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ - #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR1 ========================================================= */ - #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ - #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ - #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ - #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ - #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ - #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ - #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR2 ========================================================= */ - #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ - #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ - #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ - #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ - #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ - #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ - #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ -/* ========================================================= ICBRL ========================================================= */ - #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ - #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICBRH ========================================================= */ - #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ - #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICDRT ========================================================= */ - #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ - #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ -/* ========================================================= ICDRR ========================================================= */ - #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ - #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ -/* ========================================================= ICWUR ========================================================= */ - #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ - #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ - #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ - #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ - #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ - #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICWUR2 ========================================================= */ - #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ - #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ - #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ - #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== IWDTRR ========================================================= */ - #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ - #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ -/* ======================================================== IWDTCR ========================================================= */ - #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ======================================================== IWDTSR ========================================================= */ - #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== IWDTRCR ======================================================== */ - #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= IWDTCSTPR ======================================================= */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PRTS ========================================================== */ - #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ - #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ -/* ========================================================= CECTL ========================================================= */ - #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ - #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ -/* ========================================================= BCTL ========================================================== */ - #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ - #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ - #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ - #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ - #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ - #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ - #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSDVAD ========================================================= */ - #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ - #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ - #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTCTL ========================================================= */ - #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ - #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ - #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ - #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ - #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ - #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ - #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ - #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ - #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ - #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ - #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ - #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ - #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ -/* ========================================================= PRSST ========================================================= */ - #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ - #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ - #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ - #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ -/* ========================================================= INST ========================================================== */ - #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ - #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ -/* ========================================================= INSTE ========================================================= */ - #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ - #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ -/* ========================================================= INIE ========================================================== */ - #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ - #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== INSTFC ========================================================= */ - #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ - #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= DVCT ========================================================== */ - #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ - #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ -/* ======================================================== IBINCTL ======================================================== */ - #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ - #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ - #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ -/* ========================================================= BFCTL ========================================================= */ - #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ - #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ - #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ - #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ - #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ - #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ - #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ - #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ -/* ========================================================= SVCTL ========================================================= */ - #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ - #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ - #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ - #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ - #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ -/* ======================================================= REFCKCTL ======================================================== */ - #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ - #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ -/* ========================================================= STDBR ========================================================= */ - #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ - #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ - #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ - #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ - #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ - #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ -/* ========================================================= EXTBR ========================================================= */ - #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ - #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ - #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ - #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ - #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ -/* ======================================================== BFRECDT ======================================================== */ - #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ - #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BAVLCDT ======================================================== */ - #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ - #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BIDLCDT ======================================================== */ - #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ - #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== OUTCTL ========================================================= */ - #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ - #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ - #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ - #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ - #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ - #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ - #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ - #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ -/* ========================================================= INCTL ========================================================= */ - #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ - #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ - #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ - #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ -/* ======================================================== TMOCTL ========================================================= */ - #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ - #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ - #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ - #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ - #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ - #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ -/* ========================================================= WUCTL ========================================================= */ - #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ - #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ - #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ - #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ - #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ -/* ======================================================== ACKCTL ========================================================= */ - #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ - #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ - #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ - #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTRCTL ======================================================== */ - #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ - #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ - #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTLCTL ======================================================== */ - #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ - #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ - #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ - #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ - #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ - #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ - #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SVTDLG0 ======================================================== */ - #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ - #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= STCTL ========================================================= */ - #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ - #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ATCTL ========================================================= */ - #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ - #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ - #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ - #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ - #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ -/* ========================================================= ATTRG ========================================================= */ - #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ - #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== ATCCNTE ======================================================== */ - #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ - #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ -/* ======================================================== CNDCTL ========================================================= */ - #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ - #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ - #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ - #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ -/* ======================================================== NCMDQP ========================================================= */ -/* ======================================================== NRSPQP ========================================================= */ -/* ======================================================== NTDTBP0 ======================================================== */ -/* ======================================================== NIBIQP ========================================================= */ -/* ========================================================= NRSQP ========================================================= */ -/* ======================================================== HCMDQP ========================================================= */ - #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ - #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HRSPQP ========================================================= */ - #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ - #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HTDTBP ========================================================= */ - #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ - #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== NQTHCTL ======================================================== */ - #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ - #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= NTBTHCTL0 ======================================================= */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ======================================================= NRQTHCTL ======================================================== */ - #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ - #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ -/* ======================================================== HQTHCTL ======================================================== */ - #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= HTBTHCTL ======================================================== */ - #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ========================================================== BST ========================================================== */ - #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ - #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ - #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ - #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ - #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ - #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ - #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ - #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ - #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTE ========================================================== */ - #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ - #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ - #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ - #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ - #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ - #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ - #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ - #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ - #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ -/* ========================================================== BIE ========================================================== */ - #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ - #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ - #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ - #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ - #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ - #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ - #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ - #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ - #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTFC ========================================================= */ - #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ - #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ - #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ - #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ - #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ - #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ - #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ - #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ - #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= NTST ========================================================== */ - #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ - #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ - #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ - #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ - #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ -/* ========================================================= NTSTE ========================================================= */ - #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ - #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ - #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ - #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ - #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ -/* ========================================================= NTIE ========================================================== */ - #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ - #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ - #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ - #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ - #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ -/* ======================================================== NTSTFC ========================================================= */ - #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ - #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ - #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ - #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ -/* ========================================================= HTST ========================================================== */ - #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ - #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ - #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ -/* ========================================================= HTSTE ========================================================= */ - #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ - #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ - #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ -/* ========================================================= HTIE ========================================================== */ - #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ - #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ - #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== HTSTFC ========================================================= */ - #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ - #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ - #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= BCST ========================================================== */ - #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ - #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ - #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ - #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ -/* ========================================================= SVST ========================================================== */ - #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ - #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ - #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ - #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ - #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ -/* ========================================================= WUST ========================================================== */ - #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ - #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ -/* ======================================================== MRCCPT ========================================================= */ - #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ - #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DATBAS0 ======================================================== */ - #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS1 ======================================================== */ - #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS2 ======================================================== */ - #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS3 ======================================================== */ - #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS4 ======================================================== */ - #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS5 ======================================================== */ - #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS6 ======================================================== */ - #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS7 ======================================================== */ - #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= EXDATBAS ======================================================== */ - #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ - #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ - #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ - #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ - #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= SDATBAS0 ======================================================== */ - #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS1 ======================================================== */ - #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS2 ======================================================== */ - #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================== MSDCT0 ========================================================= */ - #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT1 ========================================================= */ - #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT2 ========================================================= */ - #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT3 ========================================================= */ - #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT4 ========================================================= */ - #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT5 ========================================================= */ - #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT6 ========================================================= */ - #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT7 ========================================================= */ - #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ========================================================= SVDCT ========================================================= */ - #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ - #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ - #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ - #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ - #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ - #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ - #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ - #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================= SDCTPIDL ======================================================== */ -/* ======================================================= SDCTPIDH ======================================================== */ -/* ======================================================== SVDVAD0 ======================================================== */ - #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD1 ======================================================== */ - #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD2 ======================================================== */ - #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== CSECMD ========================================================= */ - #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ - #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ - #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ - #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ -/* ======================================================== CEACTST ======================================================== */ - #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ - #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CMWLG ========================================================= */ - #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ - #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= CMRLG ========================================================= */ - #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ - #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ - #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ - #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ -/* ======================================================== CETSTMD ======================================================== */ - #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ - #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ -/* ======================================================== CGDVST ========================================================= */ - #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ - #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ - #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ - #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ - #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ - #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ - #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ -/* ======================================================== CMDSPW ========================================================= */ - #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ - #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPR ========================================================= */ - #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ - #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ - #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ - #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPT ========================================================= */ - #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ - #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ - #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ - #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ -/* ========================================================= CETSM ========================================================= */ - #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ - #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ - #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ - #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ - #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ - #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ - #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ -/* ========================================================= CETSS ========================================================= */ - #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ - #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ - #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ - #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ - #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ -/* ======================================================= CGHDRCAP ======================================================== */ - #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ - #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ - #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ - #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BITCNT ========================================================= */ - #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ - #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ - #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ - #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ -/* ======================================================== NQSTLV ========================================================= */ - #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ - #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ - #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ - #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================= NDBSTLV0 ======================================================== */ - #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================= NRSQSTLV ======================================================== */ - #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ - #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HQSTLV ========================================================= */ - #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ - #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HDBSTLV ======================================================== */ - #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================== PRSTDBG ======================================================== */ - #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ - #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ - #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ - #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ - #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ -/* ======================================================= MSERRCNT ======================================================== */ - #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ - #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ -/* ======================================================== SC1CPT ========================================================= */ - #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ - #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ -/* ======================================================== SC2CPT ========================================================= */ - #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ - #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= OADPT ========================================================= */ - #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== MSTPCRA ======================================================== */ - #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRB ======================================================== */ - #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ - #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRC ======================================================== */ - #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ - #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRD ======================================================== */ - #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ - #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRE ======================================================== */ - #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ - #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ -/* ======================================================= LSMRWDIS ======================================================== */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ - #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PODR ========================================================== */ - #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ========================================================== PDR ========================================================== */ - #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EIDR ========================================================== */ - #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ - #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ -/* ========================================================= PIDR ========================================================== */ - #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PORR ========================================================== */ - #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ - #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ -/* ========================================================= POSR ========================================================== */ - #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EORR ========================================================== */ - #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ - #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ -/* ========================================================= EOSR ========================================================== */ - #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PFENET ========================================================= */ - #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ - #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ - #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ - #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================== PRWCNTR ======================================================== */ - #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ - #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SFMSMD ========================================================= */ - #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ - #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ - #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ - #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ - #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ - #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ - #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ - #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ - #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ - #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ - #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ -/* ======================================================== SFMSSC ========================================================= */ - #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ - #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ - #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ - #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSKC ========================================================= */ - #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ - #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ - #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMSST ========================================================= */ - #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ - #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ - #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ - #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMCOM ========================================================= */ - #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ - #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMCMD ========================================================= */ - #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ - #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCST ========================================================= */ - #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ - #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ - #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMSIC ========================================================= */ - #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ - #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMSAC ========================================================= */ - #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ - #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ - #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMSDC ========================================================= */ - #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ - #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ - #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ - #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ - #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ - #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSPC ========================================================= */ - #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ - #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ - #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMPMD ========================================================= */ - #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ - #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCNT1 ======================================================== */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ - #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ - #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ - #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECCNT ======================================================== */ - #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ - #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINCNT ======================================================== */ - #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ - #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ -/* ======================================================== RHRCNT ========================================================= */ - #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ - #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ -/* ======================================================== RWKCNT ========================================================= */ - #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================== RDAYCNT ======================================================== */ - #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RMONCNT ======================================================== */ - #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RYRCNT ========================================================= */ - #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT0AR ======================================================== */ - #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ - #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECAR ========================================================= */ - #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT1AR ======================================================== */ - #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ - #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINAR ========================================================= */ - #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT2AR ======================================================== */ - #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ - #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RHRAR ========================================================= */ - #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT3AR ======================================================== */ - #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ - #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RWKAR ========================================================= */ - #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================= BCNT0AER ======================================================== */ - #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RDAYAR ========================================================= */ - #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT1AER ======================================================== */ - #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RMONAR ========================================================= */ - #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT2AER ======================================================== */ - #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ========================================================= RYRAR ========================================================= */ - #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT3AER ======================================================== */ - #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RYRAREN ======================================================== */ - #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR1 ========================================================== */ - #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ - #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ - #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ - #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ - #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ - #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ - #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR2 ========================================================== */ - #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ - #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ - #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ - #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ - #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ - #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ - #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ - #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ - #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR4 ========================================================== */ - #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ - #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ - #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRH ========================================================== */ - #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ - #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRL ========================================================== */ - #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= RADJ ========================================================== */ - #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ - #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ - #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ - #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ -/* ========================================================= RADJ2 ========================================================= */ - #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ - #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SMR ========================================================== */ - #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ - #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ - #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ - #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ======================================================= SMR_SMCI ======================================================== */ - #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ - #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ - #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ - #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ - #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ========================================================== BRR ========================================================== */ - #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ - #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ -/* ========================================================== SCR ========================================================== */ - #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ======================================================= SCR_SMCI ======================================================== */ - #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ========================================================== TDR ========================================================== */ - #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ - #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ -/* ========================================================== SSR ========================================================== */ - #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_FIFO ======================================================== */ - #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ - #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ - #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_MANC ======================================================== */ - #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ - #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_SMCI ======================================================== */ - #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ - #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ========================================================== RDR ========================================================== */ - #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ - #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ -/* ========================================================= SCMR ========================================================== */ - #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ - #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ - #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ - #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ - #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ - #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ -/* ========================================================= SEMR ========================================================== */ - #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ - #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ - #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ - #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ - #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ - #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ - #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ - #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ - #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= SNFR ========================================================== */ - #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ - #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ -/* ========================================================= SIMR1 ========================================================= */ - #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ - #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ - #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ - #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR2 ========================================================= */ - #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ - #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ - #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ - #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR3 ========================================================= */ - #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ - #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ - #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ - #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ - #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ - #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SISR ========================================================== */ - #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ - #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ -/* ========================================================= SPMR ========================================================== */ - #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ - #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ - #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ - #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ - #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ - #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ - #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ - #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ -/* ========================================================= TDRHL ========================================================= */ - #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ - #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FTDRHL ========================================================= */ - #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ -/* ========================================================= FTDRH ========================================================= */ - #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ - #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ - #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FTDRL ========================================================= */ - #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ - #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= RDRHL ========================================================= */ - #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ - #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FRDRHL ========================================================= */ - #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ - #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ - #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ - #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ - #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ - #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ -/* ======================================================= TDRHL_MAN ======================================================= */ - #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ -/* ======================================================= RDRHL_MAN ======================================================= */ - #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRH ========================================================= */ - #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ - #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ - #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRL ========================================================= */ - #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ - #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= MDDR ========================================================== */ - #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ - #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ -/* ========================================================= DCCR ========================================================== */ - #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ - #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ - #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ - #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ - #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ - #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ -/* ========================================================== FCR ========================================================== */ - #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ - #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ - #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ - #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ - #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ - #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ - #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ - #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ -/* ========================================================== FDR ========================================================== */ - #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ - #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ - #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ - #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ -/* ========================================================== LSR ========================================================== */ - #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ - #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ - #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ - #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ -/* ========================================================== CDR ========================================================== */ - #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ - #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ -/* ========================================================= SPTR ========================================================== */ - #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ - #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ - #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ - #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ - #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ - #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ - #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ - #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ACTR ========================================================== */ - #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ - #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ - #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ - #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ - #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ - #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ -/* ========================================================= ESMER ========================================================= */ - #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ - #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR0 ========================================================== */ - #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ - #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ - #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ - #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR1 ========================================================== */ - #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ - #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ - #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ - #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ - #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ - #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ -/* ========================================================== CR2 ========================================================== */ - #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ - #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ - #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ - #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ - #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ -/* ========================================================== CR3 ========================================================== */ - #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ - #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ -/* ========================================================== PCR ========================================================== */ - #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ - #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ - #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ - #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ -/* ========================================================== ICR ========================================================== */ - #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ - #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ - #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ - #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ - #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ - #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ - #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ - #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ - #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ - #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ - #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ - #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ - #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ -/* ========================================================= STCR ========================================================== */ - #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ - #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ - #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ - #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ - #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ - #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ - #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0DR ========================================================= */ -/* ========================================================= CF0CR ========================================================= */ - #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ - #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ - #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ - #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ - #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ - #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ - #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ - #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ - #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0RR ========================================================= */ -/* ======================================================== PCF1DR ========================================================= */ -/* ======================================================== SCF1DR ========================================================= */ -/* ========================================================= CF1CR ========================================================= */ - #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ - #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ - #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ - #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ - #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ - #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ - #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ - #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ - #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF1RR ========================================================= */ -/* ========================================================== TCR ========================================================== */ - #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ - #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ -/* ========================================================== TMR ========================================================== */ - #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ - #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ - #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ - #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ - #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ -/* ========================================================= TPRE ========================================================== */ -/* ========================================================= TCNT ========================================================== */ -/* ======================================================= SCIMSKEN ======================================================== */ - #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ - #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== MMR ========================================================== */ - #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ - #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ - #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ - #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ - #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ - #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ - #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ - #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ -/* ========================================================= TMPR ========================================================== */ - #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ - #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ - #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= RMPR ========================================================== */ - #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ - #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ - #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= MESR ========================================================== */ - #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ - #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ - #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ - #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ -/* ========================================================= MECR ========================================================== */ - #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ - #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ - #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ - #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SD_CMD ========================================================= */ - #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ - #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ - #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ - #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ - #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ - #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ - #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ - #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ -/* ======================================================== SD_ARG ========================================================= */ - #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ - #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_ARG1 ======================================================== */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== SD_STOP ======================================================== */ - #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ - #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ - #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_SECCNT ======================================================= */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SD_RSP10 ======================================================== */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP1 ======================================================== */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP32 ======================================================== */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP3 ======================================================== */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP54 ======================================================== */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP5 ======================================================== */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP76 ======================================================== */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ -/* ======================================================== SD_RSP7 ======================================================== */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ -/* ======================================================= SD_INFO1 ======================================================== */ - #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ - #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ - #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ - #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_INFO2 ======================================================== */ - #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ - #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ - #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ - #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ - #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ - #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ - #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ - #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ - #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ - #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ - #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ - #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO1_MASK ===================================================== */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO2_MASK ===================================================== */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_CLK_CTRL ====================================================== */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ -/* ======================================================== SD_SIZE ======================================================== */ - #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ - #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= SD_OPTION ======================================================= */ - #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ - #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ - #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ - #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ - #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ -/* ====================================================== SD_ERR_STS1 ====================================================== */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_ERR_STS2 ====================================================== */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SD_BUF0 ======================================================== */ - #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ - #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SDIO_MODE ======================================================= */ - #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ - #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ - #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ - #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SDIO_INFO1 ======================================================= */ - #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ -/* ==================================================== SDIO_INFO1_MASK ==================================================== */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_DMAEN ======================================================== */ - #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ - #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ -/* ======================================================= SOFT_RST ======================================================== */ - #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ - #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ -/* ======================================================= SDIF_MODE ======================================================= */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ -/* ======================================================= EXT_SWAP ======================================================== */ - #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ - #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SPCR ========================================================== */ - #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ - #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ - #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ - #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ - #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ - #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ - #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ - #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ - #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ -/* ========================================================= SSLP ========================================================== */ - #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ - #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ - #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ - #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ - #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ - #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ - #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ - #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ - #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPCR ========================================================= */ - #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ - #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ - #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ - #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ - #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSR ========================================================== */ - #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ - #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ - #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ - #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ - #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ - #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ - #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ - #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ - #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ -/* ========================================================= SPDR ========================================================== */ -/* ======================================================== SPDR_HA ======================================================== */ -/* ======================================================== SPDR_BY ======================================================== */ -/* ========================================================= SPSCR ========================================================= */ - #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ - #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ -/* ========================================================= SPBR ========================================================== */ - #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ - #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ -/* ========================================================= SPDCR ========================================================= */ - #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ - #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ - #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ - #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ - #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ - #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= SPCKD ========================================================= */ - #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ - #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SSLND ========================================================= */ - #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ - #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPND ========================================================== */ - #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ - #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR2 ========================================================= */ - #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ - #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ - #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ - #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ - #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ - #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ - #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCMD ========================================================= */ - #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ - #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ - #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ - #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ - #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ - #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ - #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ - #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ - #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ - #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ - #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ - #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ -/* ======================================================== SPDCR2 ========================================================= */ - #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ - #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ - #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSSR ========================================================= */ - #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ - #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ - #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR3 ========================================================= */ - #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ - #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ - #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ - #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPR ========================================================== */ - #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ - #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ - #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ - #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PARIOAD ======================================================== */ - #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR ======================================================== */ - #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMWTSC ======================================================== */ -/* ======================================================== ECCMODE ======================================================== */ - #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ - #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== ECC2STS ======================================================== */ - #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ - #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECC1STSEN ======================================================= */ - #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ - #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ECC1STS ======================================================== */ - #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ - #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCPRCR ======================================================== */ - #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECCPRCR2 ======================================================== */ - #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ - #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCETST ======================================================== */ - #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ - #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCOAD ========================================================= */ - #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR2 ======================================================= */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ - #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SSICR ========================================================= */ - #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ - #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ - #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ - #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ - #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ - #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ - #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ - #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ - #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ - #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ - #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ - #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ - #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ - #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ - #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ - #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ - #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ - #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ - #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ - #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ - #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ - #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ -/* ========================================================= SSISR ========================================================= */ - #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ - #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ - #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ - #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ - #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ - #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ - #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ - #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ - #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ - #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ - #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFCR ========================================================= */ - #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ - #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ - #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ - #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ - #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ - #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ - #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ - #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ - #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ - #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFSR ========================================================= */ - #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ - #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ - #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ - #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ - #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFTDR ======================================================== */ - #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ - #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFTDR16 ======================================================= */ -/* ======================================================= SSIFTDR8 ======================================================== */ -/* ======================================================== SSIFRDR ======================================================== */ - #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ - #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFRDR16 ======================================================= */ -/* ======================================================= SSIFRDR8 ======================================================== */ -/* ======================================================== SSIOFR ========================================================= */ - #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ - #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ - #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ - #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== SSISCR ========================================================= */ - #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ - #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ - #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ - #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ -/* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ -/* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ -/* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ -/* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ -/* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ -/* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR2 ======================================================== */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ -/* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ -/* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ -/* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ -/* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ -/* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ -/* ========================================================= LPOPT ========================================================= */ - #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ - #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ - #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ -/* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ -/* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ -/* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ -/* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ -/* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ -/* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ -/* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ -/* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ -/* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ -/* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ -/* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ -/* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ -/* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ -/* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LDOSCR ========================================================= */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ -/* ======================================================= PL2LDOSCR ======================================================= */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ -/* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ -/* ========================================================= SOMRG ========================================================= */ - #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ - #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ -/* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ -/* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ -/* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ -/* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ -/* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== SCISPICKDIVCR ===================================================== */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== CANFDCKDIVCR ====================================================== */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== GPTCKDIVCR ======================================================= */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== USB60CKDIVCR ====================================================== */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== CECCKDIVCR ======================================================= */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== I3CCKDIVCR ======================================================= */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== IICCKDIVCR ======================================================= */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ -/* ====================================================== SCISPICKCR ======================================================= */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= CANFDCKCR ======================================================= */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== GPTCKCR ======================================================== */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= USB60CKCR ======================================================= */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCKCR ======================================================== */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== IICCKCR ======================================================== */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== I3CCKCR ======================================================== */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ - #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ -/* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ -/* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ -/* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCDR ========================================================= */ - #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ - #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCR ========================================================== */ - #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ - #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ - #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ - #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ - #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ - #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ========================================================= CFIFO ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DVCHGR ========================================================= */ - #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ - #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ - #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ - #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ====================================================== USBBCCTRL0 ======================================================= */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ -/* ======================================================== UCKSEL ========================================================= */ - #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ - #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ -/* ========================================================= USBMC ========================================================= */ - #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ - #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ - #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSLEW ======================================================== */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR0R_FS ======================================================= */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR1R_FS ======================================================= */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= WDTRR ========================================================= */ - #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ - #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ -/* ========================================================= WDTCR ========================================================= */ - #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ========================================================= WDTSR ========================================================= */ - #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== WDTRCR ========================================================= */ - #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= WDTCSTPR ======================================================== */ - #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFOAD ========================================================= */ - #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ========================================================= TZFPT ========================================================= */ - #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CCACTL ========================================================= */ - #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ - #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCAFCT ========================================================= */ - #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ - #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCALCF ========================================================= */ - #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ - #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ -/* ======================================================== SCACTL ========================================================= */ - #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ - #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCAFCT ========================================================= */ - #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCALCF ========================================================= */ - #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ -/* ======================================================== CAPOAD ========================================================= */ - #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================== CAPRCR ========================================================= */ - #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ - #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ - #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CSAR ========================================================== */ - #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ - #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ - #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ - #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ -/* ======================================================== SRAMSAR ======================================================== */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ -/* ======================================================= STBRAMSAR ======================================================= */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DTCSAR ========================================================= */ - #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ - #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACSAR ======================================================== */ - #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ - #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARA ======================================================== */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ -/* ======================================================== ICUSARB ======================================================== */ - #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ - #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARC ======================================================== */ - #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ - #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ -/* ======================================================== ICUSARD ======================================================== */ - #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ - #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARE ======================================================== */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARF ======================================================== */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARG ======================================================== */ - #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARH ======================================================== */ - #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARI ======================================================== */ - #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARM ======================================================== */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARA ======================================================== */ - #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ - #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARB ======================================================== */ - #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ - #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARC ======================================================== */ - #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ - #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSPARC ======================================================== */ - #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ - #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MMPUSARA ======================================================== */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ -/* ======================================================= MMPUSARB ======================================================== */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGSAR ======================================================== */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DMACCHSAR ======================================================= */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ -/* ======================================================== CPUDSAR ======================================================== */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SRAMSABAR0 ======================================================= */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ====================================================== SRAMSABAR1 ======================================================= */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ======================================================== TEVTRCR ======================================================== */ - #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ - #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CADR ========================================================== */ - #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ - #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ - #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ - #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ - #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ - #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ - #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ - #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ - #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ - #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ - #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ - #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ - #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ - #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ - #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ - #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL1 ======================================================== */ - #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ - #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ - #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ - #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ - #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ - #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ - #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= STATB ========================================================= */ - #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ - #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= STATL ========================================================= */ - #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ - #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC0L ========================================================= */ - #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ - #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC1L ========================================================= */ - #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ - #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATB ========================================================== */ - #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ - #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMT ========================================================== */ - #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ - #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLL ========================================================= */ - #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ - #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLH ========================================================= */ - #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ - #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBL ========================================================= */ - #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ - #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBH ========================================================= */ - #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ - #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LL ========================================================= */ - #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ - #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LH ========================================================= */ - #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ - #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LL ========================================================= */ - #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ - #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LH ========================================================= */ - #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ - #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBL ========================================================= */ - #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ - #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBH ========================================================= */ - #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ - #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMP ========================================================== */ - #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ - #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CECEXMD ======================================================== */ - #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ - #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ - #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= CECEXMON ======================================================== */ - #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ - #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ - #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ -/* ========================================================= CTXD ========================================================== */ -/* ========================================================= CRXD ========================================================== */ -/* ========================================================= CECES ========================================================= */ - #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ - #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ - #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ - #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ - #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ - #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ - #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ - #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ -/* ========================================================= CECS ========================================================== */ - #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ - #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ - #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ - #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ - #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ - #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ - #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ -/* ========================================================= CECFC ========================================================= */ - #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ - #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ - #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ - #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ - #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ - #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ - #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ - #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL0 ======================================================== */ - #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ - #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ - #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ - #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ - #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ - #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ - #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ - #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DCR ========================================================== */ - #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ - #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ - #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ -/* ========================================================== DAR ========================================================== */ - #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ - #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ - #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ - #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ - #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= DCSR ========================================================== */ - #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ - #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ - #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ - #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ - #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ - #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ - #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ - #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ - #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ - #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ -/* ========================================================== DSR ========================================================== */ - #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ - #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ - #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ - #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ -/* ========================================================= MDTR ========================================================== */ - #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ - #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ - #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ - #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ - #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ - #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ -/* ========================================================= ACTR ========================================================== */ - #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ - #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ACAR ========================================================== */ - #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ - #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DRCSTR ========================================================= */ - #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ - #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ - #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ - #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ - #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ - #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ - #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ - #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ - #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ -/* ======================================================== DWCSTR ========================================================= */ - #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ - #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ - #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ - #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ - #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ - #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ - #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ - #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ - #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ - #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ - #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ -/* ========================================================= DCSTR ========================================================= */ - #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ - #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ - #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ - #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ -/* ========================================================= CDSR ========================================================== */ - #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ - #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ - #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ - #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ - #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ - #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ - #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ - #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ - #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ -/* ========================================================= MDLR ========================================================== */ - #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ - #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ - #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ - #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ - #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ -/* ========================================================= MRWCR ========================================================= */ - #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ - #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ - #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ - #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ - #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ -/* ======================================================== MRWCSR ========================================================= */ - #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ - #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ - #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ - #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ - #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ - #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ - #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ - #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ - #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ - #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ - #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ - #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ - #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ - #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ - #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ -/* ========================================================== ESR ========================================================== */ - #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ - #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ - #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ - #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ -/* ========================================================= CWNDR ========================================================= */ - #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ - #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CWDR ========================================================== */ - #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ - #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ - #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ - #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ - #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ -/* ========================================================== CRR ========================================================== */ - #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ - #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ - #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ - #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ - #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= ACSR ========================================================== */ - #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ - #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ - #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ -/* ======================================================== DCSMXR ========================================================= */ - #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ - #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ - #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ - #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== DWSCTSR ======================================================== */ - #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ - #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ - #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ - #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ - #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CFIFO ========================================================= */ - #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ - #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ - #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPEBUF ======================================================== */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================= PHYTRIM1 ======================================================== */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ -/* ======================================================= PHYTRIM2 ======================================================== */ - #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ - #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ - #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ - #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= EC710CTL ======================================================== */ - #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ - #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ - #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ - #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ - #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ - #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ - #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ - #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ -/* ======================================================= EC710TMC ======================================================== */ - #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ - #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ - #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ -/* ======================================================= EC710TED ======================================================== */ - #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ - #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= EC710EAD0 ======================================================= */ - #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ - #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCKMHZ ========================================================= */ - #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ - #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ - -/** @} */ /* End of group PosMask_peripherals */ - - #ifdef __cplusplus -} - #endif - -#endif /* R7FA6M5BH_H */ - -/** @} */ /* End of group R7FA6M5BH */ - -/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_cfg.h deleted file mode 100644 index 825f8cd32..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BOARD_CFG_H_ -#define BOARD_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - void bsp_init(void * p_args); - - #ifdef __cplusplus - } - #endif -#endif /* BOARD_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_sdram.h deleted file mode 100644 index 2d5eb7405..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/board_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BOARD_SDRAM_H -#define BOARD_SDRAM_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. - * It is only present if the new support has not been enabled. */ -#if 1 != BSP_CFG_SDRAM_ENABLED - #define bsp_sdram_init() R_BSP_SdramInit(true) -#endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_api.h deleted file mode 100644 index d912bc0ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_api.h +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_API_H -#define BSP_API_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* FSP Common Includes. */ -#include "fsp_common_api.h" - -/* Gets MCU configuration information. */ -#include "bsp_cfg.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic push - -/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. - * We are not modifying these files so we will ignore these warnings temporarily. */ - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" -#endif - -/* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_exceptions.h" -#include "vector_data.h" - -/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ -#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" -#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic pop -#endif - -#if defined(BSP_API_OVERRIDE) - #include BSP_API_OVERRIDE -#else - -/* BSP Common Includes. */ - #include "../../src/bsp/mcu/all/bsp_common.h" - -/* BSP MCU Specific Includes. */ - #include "../../src/bsp/mcu/all/bsp_register_protection.h" - #include "../../src/bsp/mcu/all/bsp_irq.h" - #include "../../src/bsp/mcu/all/bsp_io.h" - #include "../../src/bsp/mcu/all/bsp_group_irq.h" - #include "../../src/bsp/mcu/all/bsp_clocks.h" - #include "../../src/bsp/mcu/all/bsp_module_stop.h" - #include "../../src/bsp/mcu/all/bsp_security.h" - -/* Factory MCU information. */ - #include "../../inc/fsp_features.h" - -/* BSP Common Includes (Other than bsp_common.h) */ - #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" - - #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") - #include "../../src/bsp/mcu/all/internal/bsp_internal.h" - #endif - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_cfg.h deleted file mode 100644 index 8074418ad..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_cfg.h +++ /dev/null @@ -1,61 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - #include "bsp_clock_cfg.h" - #include "bsp_mcu_family_cfg.h" - #include "board_cfg.h" - #define RA_NOT_DEFINED 0 - #ifndef BSP_CFG_RTOS - #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else - #define BSP_CFG_RTOS (0) - #endif - #endif - #ifndef BSP_CFG_RTC_USED - #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) - #endif - #undef RA_NOT_DEFINED - #if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif - #define BSP_CFG_MCU_VCC_MV (3300) - #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0) - #define BSP_CFG_PARAM_CHECKING_ENABLE (0) - #define BSP_CFG_ASSERT (0) - - #define BSP_CFG_PFS_PROTECT ((1)) - - #define BSP_CFG_C_RUNTIME_INIT ((1)) - #define BSP_CFG_EARLY_INIT ((0)) - - #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED - #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - #endif - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE - #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE - #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS - #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - #endif - - #ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_clocks.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_clocks.h deleted file mode 100644 index 986b0529c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_clocks.h +++ /dev/null @@ -1,1727 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_CLOCKS_H -#define BSP_CLOCKS_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_clock_cfg.h" -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match SCKCR.CKSEL values. */ -#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. - #endif - #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. - #endif - #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. - #endif -#else - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ - #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. - #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. - -/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ - #define BSP_PRV_OSTC_OFFSET (0x7FU) - -#endif - -/* PLLs are not supported in the following scenarios: - * - When using low voltage mode - * - When using an MCU that does not have a PLL - * - When the PLL only accepts the main oscillator as a source and XTAL is not used - */ -#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) - #define BSP_PRV_PLL_SUPPORTED (1) - #if BSP_FEATURE_CGC_HAS_PLL2 - #define BSP_PRV_PLL2_SUPPORTED (1) - #else - #define BSP_PRV_PLL2_SUPPORTED (0) - #endif -#else - #define BSP_PRV_PLL_SUPPORTED (0) - #define BSP_PRV_PLL2_SUPPORTED (0) -#endif - -/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency - * calculated here is also used to initialize the g_clock_freq array. */ -#if BSP_PRV_PLL_SUPPORTED - #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ - (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif -#if BSP_PRV_PLL2_SUPPORTED - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif - -#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) - -/* Frequencies of clocks with fixed freqencies. */ -#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz -#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz - -#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #endif - #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ - (BSP_CFG_PLL_DIV + 1U)) - #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ - (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) - #endif -#endif - -/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ -#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) -#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) -#else - #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) -#endif - -#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) -#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) -#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) -#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) -#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) -#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) -#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) -#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) - -/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have - * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ -#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) -#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) -#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) -#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) -#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) -#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) -#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) -#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) -#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) -#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) - -/* System clock divider options. */ -#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. -#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. -#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. -#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. -#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. -#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. -#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. -#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). -#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. -#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. -#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. -#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. - -/* USB clock divider options. */ -#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 -#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 -#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 -#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 -#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 -#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 -#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 -#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 -#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 -#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 - -/* USB60 clock divider options. */ -#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 -#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 -#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 -#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 -#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 -#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 -#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 -#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 -#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 -#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 - -/* GLCD clock divider options. */ -#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 -#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 -#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 -#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 -#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 -#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 -#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 -#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 -#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 -#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 - -/* OCTA clock divider options. */ -#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 - -/* CANFD clock divider options. */ -#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 - -/* SCI clock divider options. */ -#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 -#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 -#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 -#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 -#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 -#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 -#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 -#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 -#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 -#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 - -/* SPI clock divider options. */ -#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 -#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 -#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 -#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 -#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 -#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 -#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 -#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 -#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 -#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 - -/* SCISPI clock divider options. */ -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 - -/* GPT clock divider options. */ -#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 -#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 -#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 -#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 -#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 -#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 -#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 -#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 -#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 -#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 - -/* IIC clock divider options. */ -#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 -#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 -#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 -#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 -#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 - -/* CEC clock divider options. */ -#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 -#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 - -/* I3C clock divider options. */ -#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 -#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 -#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 -#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 -#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 -#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 -#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 -#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 -#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 -#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 - -/* ADC clock divider options. */ -#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 -#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 -#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 -#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 -#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 -#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 -#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 -#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 -#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 -#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 - -/* SAU clock divider options. */ -#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 -#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 -#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 -#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 -#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 -#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 - -/* Extra peripheral 0 clock divider options. */ -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 - -/* PLL divider options. */ -#define BSP_CLOCKS_PLL_DIV_1 (0) -#define BSP_CLOCKS_PLL_DIV_2 (1) -#define BSP_CLOCKS_PLL_DIV_3 (2) -#define BSP_CLOCKS_PLL_DIV_4 (3) -#define BSP_CLOCKS_PLL_DIV_5 (4) -#define BSP_CLOCKS_PLL_DIV_6 (5) -#define BSP_CLOCKS_PLL_DIV_8 (7) -#define BSP_CLOCKS_PLL_DIV_9 (8) -#define BSP_CLOCKS_PLL_DIV_1_5 (9) -#define BSP_CLOCKS_PLL_DIV_16 (15) - -/* PLL multiplier options. */ -#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - -/* Offset from decimal multiplier to register value for PLLCCR type 4. */ - #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) - -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) - -#else - - #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U))) - -#endif - -/* Configuration option used to disable clock output. */ -#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) - -/* HOCO cycles per microsecond. */ -#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) - -/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ -#if BSP_HOCO_HZ < 48000000U - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) -#else - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) -#endif - -/* Create a mask of valid bits in SCKDIVCR. */ -#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) -#else - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) -#else - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) -#else - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) -#else - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB - #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) -#else - #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#else - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) -#else - #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) -#endif -#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ - BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ - BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ - BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) - -/* FLL is only used when enabled, present and the subclock is populated. */ -#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_PRV_HOCO_USE_FLL (1) - #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US - #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) - #endif -#else - #define BSP_PRV_HOCO_USE_FLL (0) - #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) -#endif - -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR - #define BSP_PRV_RTC_RESET_DELAY_US (200) -#endif - -/* Operating power control modes. */ -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed -#else - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed - #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed -#endif -#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -typedef struct -{ - uint32_t pll_freq; -} bsp_clock_up2025-08-11_callback_args_t; - - #if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_up2025-08-11_callback_t)(bsp_clock_up2025-08-11_callback_args_t * - p_callback_args); - #elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_up2025-08-11_callback_t)(bsp_clock_up2025-08-11_callback_args_t * - p_callback_args); - #endif - -#endif - -/** PLL multiplier values */ -typedef enum e_cgc_pll_mul -{ - CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 - CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 - CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 - CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 - CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 - CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 - CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 - CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 - CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 - CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 - CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 - CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 - CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 - CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 - CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 - CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 - CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 - CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 - CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 - CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 - CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 - CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 - CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 - CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 - CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 - CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 - CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 - CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 - CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 - CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 - CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 - CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 - CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 - CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 - CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 - CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 - CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 - CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 - CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 - CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 - CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 - CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 - CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 - CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 - CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 - CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 - CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 - CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 - CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 - CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 - CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 - CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 - CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 - CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 - CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 - CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 - CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 - CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 - CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 - CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 - CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 - CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 - CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 - CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 - CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 - CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 - CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 - CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 - CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 - CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 - CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 - CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 - CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 - CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 - CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 - CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 - CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 - CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 - CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 - CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 - CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 - CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 - CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 - CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 - CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 - CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 - CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 - CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 - CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 - CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 - CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 - CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 - CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 - CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 - CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 - CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 - CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 - CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 - CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 - CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 - CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 - CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 - CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 - CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 - CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 - CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 - CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 - CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 - CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 - CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 - CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 - CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 - CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 - CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 - CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 - CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 - CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 - CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 - CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 - CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 - CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 - CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 - CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 - CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 - CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 - CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 - CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 - CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 - CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 - CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 - CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 - CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 - CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 - CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 - CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 - CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 - CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 - CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 - CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 - CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 - CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 - CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 - CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 - CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 - CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 - CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 - CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 - CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 - CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 - CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 - CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 - CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 - CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 - CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 - CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 - CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 - CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 - CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 - CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 - CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 - CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 - CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 - CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 - CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 - CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 - CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 - CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 - CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 - CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 - CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 - CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 - CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 - CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 - CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 - CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 - CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 - CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 - CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 - CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 - CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 - CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 - CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 - CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 - CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 - CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 - CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 - CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 - CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 - CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 - CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 - CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 - CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 - CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 - CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 - CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 - CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 - CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 - CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 - CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 - CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 - CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 - CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 - CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 - CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 - CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 - CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 - CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 - CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 - CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 - CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 - CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 - CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 - CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 - CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 - CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 - CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 - CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 - CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 - CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 - CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 - CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 - CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 - CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 - CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 - CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 - CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 - CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 - CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 - CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 - CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 - CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 - CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 - CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 - CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 - CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 - CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 - CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 - CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 - CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 - CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 - CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 - CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 - CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 - CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 - CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 - CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 - CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 - CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 - CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 - CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 - CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 - CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 - CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 - CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 - CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 - CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 - CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 - CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 - CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 - CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 - CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 - CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 - CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 - CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 - CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 - CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 - CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 - CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 - CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 - CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 - CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 - CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 - CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 - CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 - CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 - CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 - CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 - CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 - CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 - CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 - CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 - CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 - CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 - CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 - CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 - CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 - CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 - CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 - CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 - CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 - CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 - CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 - CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 - CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 - CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 - CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 - CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 - CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 - CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 - CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 - CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 - CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 - CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 - CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 - CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 - CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 - CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 - CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 - CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 - CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 - CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 - CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 - CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 - CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 - CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 - CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 - CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 - CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 - CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 - CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 - CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 - CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 - CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 - CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 - CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 - CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 - CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 - CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 - CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 - CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 - CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 - CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 - CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 - CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 - CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 - CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 - CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 - CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 - CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 - CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 - CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 - CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 - CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 - CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 - CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 - CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 - CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 - CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 - CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 - CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 - CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 - CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 - CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 - CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 - CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 - CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 - CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 - CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 - CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 - CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 - CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 - CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 - CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 - CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 - CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 - CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 - CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 - CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 - CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 - CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 - CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 - CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 - CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 - CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 - CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 - CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 - CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 - CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 - CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 - CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 - CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 - CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 - CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 - CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 - CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 - CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 - CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 - CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 - CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 - CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 - CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 - CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 - CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 - CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 - CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 - CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 - CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 - CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 - CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 - CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 - CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 - CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 - CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 - CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 - CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 - CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 - CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 - CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 - CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 - CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 - CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 - CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 - CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 - CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 - CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 - CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 - CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 - CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 - CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 - CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 - CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 - CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 - CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 - CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 - CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 - CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 - CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 - CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 - CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 - CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 - CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 - CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 - CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 - CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 - CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 - CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 - CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 - CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 - CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 - CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 - CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 - CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 - CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 - CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 - CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 - CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 - CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 - CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 - CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 - CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 - CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 - CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 - CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 - CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 - CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 - CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 - CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 - CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 - CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 - CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 - CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 - CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 - CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 - CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 - CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 - CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 - CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 - CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 - CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 - CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 - CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 - CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 - CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 - CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 - CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 - CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 - CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 - CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 - CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 - CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 - CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 - CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 - CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 - CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 - CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 - CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 - CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 - CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 - CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 - CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 - CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 - CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 - CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 - CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 - CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 - CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 - CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 - CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 - CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 - CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 - CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 - CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 - CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 - CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 - CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 - CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 - CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 - CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 - CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 - CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 - CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 - CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 - CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 - CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 - CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 - CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 - CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 - CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 - CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 - CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 - CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 - CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 - CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 - CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 - CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 - CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 - CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 - CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 - CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 - CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 - CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 - CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 - CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 - CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 - CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 - CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 - CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 - CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 - CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 - CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 - CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 - CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 - CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 - CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 - CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 - CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 - CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 - CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 - CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 - CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 - CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 - CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 - CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 - CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 - CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 - CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 - CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 - CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 - CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 - CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 - CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 - CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 - CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 - CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 - CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 - CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 - CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 - CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 - CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 - CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 - CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 - CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 - CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 - CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 - CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 - CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 - CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 - CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 - CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 - CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 - CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 - CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 - CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 - CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 - CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 - CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 - CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 - CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 - CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 - CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 - CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 - CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 - CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 - CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 - CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 - CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 - CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 - CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 - CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 - CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 - CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 - CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 - CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 - CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 - CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 - CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 - CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 - CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 - CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 - CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 - CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 - CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 - CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 - CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 - CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 - CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 - CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 - CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 - CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 - CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 - CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 - CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 - CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 - CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 - CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 - CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 - CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 - CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 - CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 - CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 - CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 - CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 - CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 - CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 - CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 - CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 - CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 - CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 - CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 - CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 - CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 - CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 - CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 - CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 - CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 - CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 - CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 - CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 - CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 - CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 - CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 - CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 - CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 - CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 - CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 - CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 - CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 - CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 - CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 - CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 - CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 - CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 - CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 - CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 - CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 - CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 - CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 - CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 - CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 - CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 - CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 - CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 - CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 - CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 - CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 - CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 - CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 - CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 - CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 - CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 - CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 - CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 - CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 - CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 - CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 - CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 - CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 - CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 - CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 - CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 - CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 - CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 - CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 - CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 - CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 - CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 - CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 - CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 - CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 - CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 - CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 - CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 - CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 - CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 - CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 - CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 - CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 - CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 - CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 - CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 - CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 - CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 - CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 - CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 - CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 - CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 - CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 - CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 - CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 - CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 - CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 - CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 - CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 - CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 - CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 - CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 - CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 - CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 - CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 - CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 - CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 - CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 - CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 - CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 - CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 - CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 - CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 - CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 - CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 - CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 - CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 - CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 - CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 - CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 - CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 - CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 - CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 - CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 - CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 - CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 - CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 - CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 - CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 - CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 - CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 - CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 - CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 - CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 - CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 - CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 - CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 - CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 - CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 - CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 - CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 - CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 - CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 - CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 - CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 - CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 - CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 - CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 - CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 - CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 - CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 - CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 - CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 - CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 - CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 - CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 - CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 - CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 - CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 - CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 - CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 - CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 - CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 - CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 - CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 - CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 - CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 - CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 - CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 - CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 - CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 - CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 - CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 - CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 - CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 - CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 - CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 - CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 - CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 - CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 - CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 - CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 - CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 - CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 - CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 - CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 - CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 - CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 - CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 - CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 - CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 - CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 - CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 - CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 - CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 - CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 - CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 - CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 - CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 - CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 - CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 - CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 - CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 - CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 - CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 - CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 - CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 - CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 - CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 - CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 - CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 - CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 - CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 - CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 - CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 - CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 - CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 - CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 - CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 - CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 - CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 - CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 - CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 - CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 - CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 - CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 - CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 - CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 - CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 - CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 - CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 - CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 - CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 - CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 - CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 - CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 - CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 - CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 - CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 - CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 - CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 - CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 - CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 - CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 - CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 - CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 - CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 - CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 - CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 - CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 - CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 - CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 - CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 - CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 - CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 - CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 - CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 - CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 - CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 - CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 - CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 - CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 - CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 - CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 - CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 - CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 - CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 - CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 - CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 - CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 - CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 - CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 - CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 - CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 - CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 - CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 - CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 - CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 - CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 - CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 - CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 - CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 - CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 - CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 - CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 - CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 - CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 - CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 - CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 - CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 - CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 - CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 - CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 - CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 - CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 - CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 - CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 - CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 - CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 - CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 - CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 - CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 - CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 - CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 - CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 - CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 - CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 - CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 - CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 - CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 - CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 - CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 - CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 - CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 - CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 - CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 - CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 - CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 - CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 - CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 - CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 - CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 - CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 - CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 - CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 - CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 - CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 - CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 - CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 - CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 - CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 - CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 - CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 - CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 - CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 - CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 - CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 - CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 - CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 - CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 - CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 - CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 - CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 - CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 - CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 - CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 - CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 - CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 - CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 - CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 - CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 - CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 - CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 - CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 - CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 - CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 - CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 - CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 - CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 - CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 - CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 - CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 - CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 - CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 - CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 - CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 - CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 - CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 - CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 - CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 - CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 - CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 - CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 - CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 - CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 - CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 - CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 - CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 - CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 - CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 - CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 - CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 - CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 - CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 - CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 - CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 - CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 - CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 - CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 - CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 - CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 - CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 - CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 - CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 - CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 - CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 - CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 - CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 - CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 - CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 - CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 - CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 - CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 - CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 - CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 - CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 - CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 - CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 - CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 - CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 - CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 - CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 - CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 - CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 - CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 - CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 - CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 - CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 - CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 - CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 - CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 - CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 - CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 - CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 - CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 - CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 - CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 - CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 - CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 - CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 - CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 - CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 - CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 - CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 - CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 - CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 - CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 - CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 - CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 - CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 - CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 - CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 - CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 - CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 - CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 - CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 - CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 - CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 - CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 - CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 - CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 - CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 - CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 - CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 - CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 - CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 - CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 - CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 - CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 - CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 - CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 - CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 - CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 - CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 - CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 - CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 - CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 - CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 - CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 - CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 - CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 - CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 - CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 - CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 - CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 - CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 - CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 - CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 - CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 - CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 - CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 - CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 - CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 - CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 - CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 - CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 - CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 - CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 - CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 - CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 - CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 - CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 - CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 - CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 - CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 - CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 - CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 - CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 - CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 - CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 - CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 - CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 - CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 - CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 - CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 - CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 - CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 - CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 - CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 - CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 - CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 - CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 - CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 - CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 - CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 - CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 - CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 - CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 - CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 - CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 - CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 - CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 -} cgc_pll_mul_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_clock_init(void); // Used internally by BSP - -#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD -void bsp_clock_freq_var_init(void); // Used internally by BSP - -#endif - -#if BSP_TZ_SECURE_BUILD -void r_bsp_clock_up2025-08-11_callback_set(bsp_clock_up2025-08-11_callback_t p_callback, - bsp_clock_up2025-08-11_callback_args_t * p_callback_memory); - -#endif - -/* Used internally by CGC */ - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE -void bsp_prv_operating_mode_set(uint8_t operating_mode); - -#endif - -#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED -uint32_t bsp_prv_power_change_mstp_set(void); -void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); - -#endif - -void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); - -#if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); - -#else -void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); -uint32_t bsp_prv_clock_source_get(void); - -#endif - -/* RTC Initialization */ -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR -void R_BSP_Init_RTC(void); - -#endif - -#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE -bool bsp_prv_rtc_register_clock_set(bool enable); - -#endif - -#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE -bool bsp_prv_clock_prepare_pre_sleep(void); -void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); - -#endif - -/* The public function is used to get state or initialize the sub-clock. */ -#if BSP_FEATURE_RTC_IS_IRTC -fsp_err_t R_BSP_SubclockStatusGet(); -fsp_err_t R_BSP_SubclockInitialize(); - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_common.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_common.h deleted file mode 100644 index 5c09ac9ca..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_common.h +++ /dev/null @@ -1,623 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_COMMON_H -#define BSP_COMMON_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include -#include - -/* Different compiler support. */ -#include "../../inc/api/fsp_common_api.h" -#include "bsp_compiler_support.h" - -/* BSP TFU Includes. */ -#include "../../src/bsp/mcu/all/bsp_tfu.h" - -#include "../../src/bsp/mcu/all/bsp_sdram.h" - -/* BSP MMF Includes. */ -#include "../../src/bsp/mcu/all/bsp_mmf.h" - -#include "bsp_cfg.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** Used to signify that an ELC event is not able to be used as an interrupt. */ -#define BSP_IRQ_DISABLED (0xFFU) - -/* Version of this module's code and API. */ - -#if 1 == BSP_CFG_RTOS /* ThreadX */ - #include "tx_user.h" - #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) - #include "tx_port.h" - #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); - #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); - #else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE - #endif -#else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE -#endif - -/** Macro that can be defined in order to enable logging in FSP modules. */ -#ifndef FSP_LOG_PRINT - #define FSP_LOG_PRINT(X) -#endif - -/** Macro to log and return error without an assertion. */ -#ifndef FSP_RETURN - - #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ - return err; -#endif - -/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in - * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ -#if (1 == BSP_CFG_ASSERT) - - #ifndef FSP_ERROR_LOG - #define FSP_ERROR_LOG(err) \ - fsp_error_log((err), __FILE__, __LINE__); - #endif -#else - - #define FSP_ERROR_LOG(err) -#endif - -/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP - * functions. */ -#if (3 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) -#elif (2 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) {assert(a);} -#else - #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) -#endif // ifndef FSP_ASSERT - -/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used - * to identify runtime errors in FSP functions. */ - -#define FSP_ERROR_RETURN(a, err) \ - { \ - if ((a)) \ - { \ - (void) 0; /* Do nothing */ \ - } \ - else \ - { \ - FSP_ERROR_LOG(err); \ - return err; \ - } \ - } - -/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register up2025-08-11s. - * This macro can be redefined to add a timeout if necessary. */ -#ifndef FSP_HARDWARE_REGISTER_WAIT - #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} -#endif - -#ifndef FSP_REGISTER_READ - -/* Read a register and discard the result. */ - #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); -#endif - -/**************************************************************** - * - * This check is performed to select suitable ASM API with respect to core - * - * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so - * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ - -#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) - #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) - #endif -#else - #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #endif - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) -#endif - -/* This macro defines a variable for saving previous mask value */ -#ifndef FSP_CRITICAL_SECTION_DEFINE - - #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U -#endif - -/* These macros abstract methods to save and restore the interrupt state for different architectures. */ -#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK - #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) -#else - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI - #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ - (8U - __NVIC_PRIO_BITS))) -#endif - -/** This macro temporarily saves the current interrupt state and disables interrupts. */ -#ifndef FSP_CRITICAL_SECTION_ENTER - #define FSP_CRITICAL_SECTION_ENTER \ - old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ - FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) -#endif - -/** This macro restores the previously saved interrupt state, reenabling interrupts. */ -#ifndef FSP_CRITICAL_SECTION_EXIT - #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) -#endif - -/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ -#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) - -/** Used to signify that the requested IRQ vector is not defined in this system. */ -#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) - -/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ -#if (BSP_CFG_MCU_PART_SERIES == 8) - #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) -#else - #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) -#endif - -/* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE - #define FSP_PRIV_TZ_USE_SECURE_REGS (1) -#else - #define FSP_PRIV_TZ_USE_SECURE_REGS (0) -#endif - -/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ -#if BSP_CFG_EARLY_INIT - #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) -#else - #define BSP_SECTION_EARLY_INIT -#endif - -#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 -BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); - -#endif - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/* - * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register - * from the secure application using the provided non-secure callable functions. - */ - #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) - #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) - #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) -#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/*******************************************************************************************************************//** - * Read a non-secure 8-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) -{ - p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 16-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) -{ - p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 32-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) -{ - p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/* - * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register - * using the non-secure aliased address. - */ - #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) - #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) - #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) -#else - #define FSP_STYPE3_REG8_READ(X, S) (X) - #define FSP_STYPE3_REG16_READ(X, S) (X) - #define FSP_STYPE3_REG32_READ(X, S) (X) -#endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Different warm start entry locations in the BSP. */ -typedef enum e_bsp_warm_start_event -{ - BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. - BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. - BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up -} bsp_warm_start_event_t; - -/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ -typedef enum e_fsp_priv_clock -{ - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_PCLKE = 20, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, - FSP_PRIV_CLOCK_CPUCLK = 32, -} fsp_priv_clock_t; - -/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ -typedef enum e_fsp_priv_source_clock -{ - FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator - FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator - FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator - FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator - FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator - FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output - FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output - FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output - FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output - FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output - FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output - FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output - FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output -} fsp_priv_source_clock_t; - -typedef struct st_bsp_unique_id -{ - union - { - uint32_t unique_id_words[4]; - uint8_t unique_id_bytes[16]; - }; -} bsp_unique_id_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); - -/*********************************************************************************************************************** - * Global variables (defined in other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Return active interrupt vector number value - * - * @return Active interrupt vector number value - **********************************************************************************************************************/ -__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) -{ - xPSR_Type xpsr_value; - xpsr_value.w = __get_xPSR(); - - return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); -} - -/*******************************************************************************************************************//** - * Gets the frequency of a system clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) -{ -#if !BSP_FEATURE_CGC_REGISTER_SET_B - uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; - - #if BSP_FEATURE_CGC_HAS_CPUCLK - if (FSP_PRIV_CLOCK_CPUCLK == clock) - { - return SystemCoreClock; - } - - /* Get CPUCLK divisor */ - uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; - - /* Determine if either divisor is a multiple of 3 */ - if ((cpuclk_div | clock_div) & 8U) - { - /* Convert divisor settings to their actual values */ - cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); - clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); - - /* Calculate clock with multiplication and division instead of shifting */ - return (SystemCoreClock * cpuclk_div) / clock_div; - } - else - { - return (SystemCoreClock << cpuclk_div) >> clock_div; - } - - #else - uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; - - return (SystemCoreClock << iclk_div) >> clock_div; - #endif -#else - FSP_PARAMETER_NOT_USED(clock); - - return SystemCoreClock; -#endif -} - -/*******************************************************************************************************************//** - * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). - * - * @return Clock Divider - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) -{ - if (2U >= ckdivcr) - { - - /* clock_div: - * - Clock Divided by 1: 0 - * - Clock Divided by 2: 1 - * - Clock Divided by 4: 2 - */ - return 1U << ckdivcr; - } - else if (3U == ckdivcr) - { - - /* Clock Divided by 6 */ - return 6U; - } - else if (4U == ckdivcr) - { - - /* Clock Divided by 8 */ - return 8U; - } - else if (5U == ckdivcr) - { - - /* Clock Divided by 3 */ - return 3U; - } - else if (6U == ckdivcr) - { - - /* Clock Divided by 5 */ - return 5; - } - else if (7U == ckdivcr) - { - - /* Clock Divided by 10 */ - return 10; - } - else - { - /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ - } - - /* Clock Divided by 16 */ - return 16U; -} - -#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI/SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) -{ - uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; - uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; - - return R_BSP_SourceClockHzGet(scispicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) -{ - uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = - (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> - R_SYSTEM_SPICKCR_CKSEL_Pos); - - return R_BSP_SourceClockHzGet(spicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SCI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) -{ - uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = - (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> - R_SYSTEM_SCICKCR_SCICKSEL_Pos); - - return R_BSP_SourceClockHzGet(scicksel) / clock_div; -} - -#endif - -/*******************************************************************************************************************//** - * Get unique ID for this device. - * - * @return A pointer to the unique identifier structure - **********************************************************************************************************************/ -__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) -{ -#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 - - return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); -#else - - return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; -#endif -} - -/*******************************************************************************************************************//** - * Disables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheDisable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 - - /* Writeback and flush cache when disabling - * MREF_INTERNAL_12 */ - if (R_CACHE->CCAWTA_b.WT) - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; - } - else - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; - } - - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #else - - /* Disable the C-Cache. */ - R_CACHE->CCACTL = 0U; - #endif -#endif -} - -/*******************************************************************************************************************//** - * Enables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheEnable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invali2025-08-11 the flash cache and wait until it is invali2025-08-11d. (See section 55.3.2.2 "Operation" of the Flash Cache - * in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 - - /* Configure the C-Cache line size. */ - R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; - #else - - /* Check that no flush or writeback are ongoing before enabling - * MREF_INTERNAL_13 */ - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #endif - - /* Enable the C-Cache. */ - R_CACHE->CCACTL = 1U; -#endif -} - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -#if (1 == BSP_CFG_ASSERT) - -/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ -void fsp_error_log(fsp_err_t err, const char * file, int32_t line); - -#endif - -/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will - * alert the user of the error. The user can override this default behavior by defining their own - * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. - */ -#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) - - #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_compiler_support.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_compiler_support.h deleted file mode 100644 index 39f752c3c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_compiler_support.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_COMPILER_SUPPORT_H - #define BSP_COMPILER_SUPPORT_H - - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - #include "arm_cmse.h" - #endif - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - #if defined(__ARMCC_VERSION) /* AC6 compiler */ - -/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load - * memory (ROM) is reserved unnecessarily. */ - #define BSP_UNINIT_SECTION_PREFIX ".bss" - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__GNUC__) /* GCC compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__ICCARM__) /* IAR compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP "HEAP" - #endif - #define BSP_DONT_REMOVE __root - #define BSP_ATTRIBUTE_STACKLESS __stackless - #define BSP_FORCE_INLINE _Pragma("inline=forced") - #endif - - #ifndef BSP_SECTION_STACK - #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" - #endif - #ifndef BSP_SECTION_FLASH_GAP - #define BSP_SECTION_FLASH_GAP - #endif - #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" - #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - #define BSP_SECTION_ROM_REGISTERS ".rom_registers" - #define BSP_SECTION_ID_CODE ".id_code" - -/* Compiler neutral macros. */ - #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - - #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) - - #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED - - #define BSP_WEAK_REFERENCE __attribute__((weak)) - -/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ - #define BSP_STACK_ALIGNMENT (8) - -/*********************************************************************************************************************** - * TrustZone definitions - **********************************************************************************************************************/ - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) - #if defined(__ICCARM__) /* IAR compiler */ - #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call - #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry - #else - #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) - #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) - #endif - #else - #define BSP_CMSE_NONSECURE_CALL - #define BSP_CMSE_NONSECURE_ENTRY - #endif - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/** @} (end of addtogroup BSP_MCU) */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_delay.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_delay.h deleted file mode 100644 index 94a13ccff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_delay.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_DELAY_H -#define BSP_DELAY_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "bsp_compiler_support.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The number of cycles required per software delay loop. */ -#ifndef BSP_DELAY_LOOP_CYCLES - #if defined(RENESAS_CORTEX_M85) - -/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for - * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in - * this case. */ - #if defined(__ICCARM__) - #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) - #else - #define BSP_DELAY_LOOP_CYCLES (1) - #endif - #else - #define BSP_DELAY_LOOP_CYCLES (4) - #endif -#endif - -/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle - * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures - * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count - * of 0. */ -#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) - -/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ -typedef enum -{ - BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds - BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds - BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds -} bsp_delay_units_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_elc.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_elc.h deleted file mode 100644 index 9a2207791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_elc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_ELC_H -#define BSP_ELC_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU_RA6M5 - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* UNCRUSTIFY-OFF */ - -/** Sources of event signals to be linked to other peripherals or the CPU - * @note This list is device specific. - * */ -typedef enum e_elc_event_ra6m5 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end - ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end - ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end - ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end - ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end - ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete - ELC_EVENT_DTC_END = (0x02A), // DTC transfer end - ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode - ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt - ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt - ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry - ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B - ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt - ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A - ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B - ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt - ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A - ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B - ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt - ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A - ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B - ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt - ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A - ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt - ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt - ELC_EVENT_CAN_GLERR = (0x05A), // Global error - ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 - ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 - ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 - ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 - ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 - ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 - ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 - ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 - ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt - ELC_EVENT_CAN0_CHERR = (0x064), // Channel error - ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt - ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request - ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt - ELC_EVENT_CAN1_CHERR = (0x068), // Channel error - ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt - ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request - ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x073), // Receive data full - ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x075), // Transmit end - ELC_EVENT_IIC0_ERI = (0x076), // Transfer error - ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x078), // Receive data full - ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x080), // Transfer error - ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request - ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full - ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt - ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt - ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt - ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow - ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow - ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow - ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow - ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch - ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt - ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x180), // Receive data full - ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x182), // Transmit end - ELC_EVENT_SCI0_ERI = (0x183), // Receive error - ELC_EVENT_SCI0_AM = (0x184), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x186), // Receive data full - ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x188), // Transmit end - ELC_EVENT_SCI1_ERI = (0x189), // Receive error - ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI2_ERI = (0x18F), // Receive error - ELC_EVENT_SCI3_RXI = (0x192), // Receive data full - ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x194), // Transmit end - ELC_EVENT_SCI3_ERI = (0x195), // Receive error - ELC_EVENT_SCI3_AM = (0x196), // Address match event - ELC_EVENT_SCI4_RXI = (0x198), // Receive data full - ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI4_ERI = (0x19B), // Receive error - ELC_EVENT_SCI4_AM = (0x19C), // Address match event - ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI5_AM = (0x1A2), // Address match event - ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI6_AM = (0x1A8), // Address match event - ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI7_AM = (0x1AE), // Address match event - ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error - ELC_EVENT_SCI8_AM = (0x1B4), // Address match event - ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error - ELC_EVENT_SCI9_AM = (0x1BA), // Address match event - ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle - ELC_EVENT_SPI0_ERI = (0x1C7), // Error - ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle - ELC_EVENT_SPI1_ERI = (0x1CC), // Error - ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event - ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error - ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error - ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error - ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt - ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt - ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt -} elc_event_t; - -#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) - -#define ELC_PERIPHERAL_NUM (19U) -#define BSP_OVERRIDE_ELC_PERIPHERAL_T -/** Possible peripherals to be linked to event signals - * @note This list is device specific. - * */ -typedef enum e_elc_peripheral -{ - ELC_PERIPHERAL_GPT_A = (0), - ELC_PERIPHERAL_GPT_B = (1), - ELC_PERIPHERAL_GPT_C = (2), - ELC_PERIPHERAL_GPT_D = (3), - ELC_PERIPHERAL_GPT_E = (4), - ELC_PERIPHERAL_GPT_F = (5), - ELC_PERIPHERAL_GPT_G = (6), - ELC_PERIPHERAL_GPT_H = (7), - ELC_PERIPHERAL_ADC0 = (8), - ELC_PERIPHERAL_ADC0_B = (9), - ELC_PERIPHERAL_ADC1 = (10), - ELC_PERIPHERAL_ADC1_B = (11), - ELC_PERIPHERAL_DAC0 = (12), - ELC_PERIPHERAL_DAC1 = (13), - ELC_PERIPHERAL_IOPORT1 = (14), - ELC_PERIPHERAL_IOPORT2 = (15), - ELC_PERIPHERAL_IOPORT3 = (16), - ELC_PERIPHERAL_IOPORT4 = (17), - ELC_PERIPHERAL_CTSU = (18) -} elc_peripheral_t; - -/** Positions of event link set registers (ELSRs) available on this MCU */ -#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) - -/* UNCRUSTIFY-ON */ -/** @} (end addtogroup BSP_MCU_RA6M5) */ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_exceptions.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_exceptions.h deleted file mode 100644 index f388be329..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_exceptions.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_EXCEPTIONS_H - #define BSP_EXCEPTIONS_H - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ -typedef enum IRQn -{ - Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ -} IRQn_Type; - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_feature.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_feature.h deleted file mode 100644 index 29f6b43f1..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_feature.h +++ /dev/null @@ -1,588 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_FEATURE_H -#define BSP_FEATURE_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "bsp_peripheral.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ -#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) -#if (BSP_CFG_XTAL_HZ >= (20000000)) - #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (16000000)) - #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (8000000)) - #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#else - #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#endif - -// *UNCRUSTIFY-OFF* - -#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. -#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. -#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0xFFFFUL) // Create the mask for the valid calibration data provided by TSCDR. -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. -#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FFUL) // Mask of available channels in ADC unit 0. -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007UL) // Mask of available channels in ADC unit 1. -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. - -#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. -#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. -#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. -#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. - -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. -#define BSP_FEATURE_BSP_FLASH_CACHE (1UL) // Flash cache is present. -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. -#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. -#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1UL) // Indicates there is a separate clock for the CEC. -#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. -#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. -#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. -#define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. -#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. -#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. -#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0UL) // Indicates there is a separate clock for the I3C. -#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. -#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. -#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. -#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. -#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. -#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. -#define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. -#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. -#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. -#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. -#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. -#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. -#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. -#define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. -#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. -#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. -#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. -#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. -#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. -#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. -#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. -#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. -#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. -#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. - -#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. -#define BSP_FEATURE_CANFD_LITE (0UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. -#define BSP_FEATURE_CANFD_NUM_CHANNELS (2UL) // Number of CANFD channels per CANFD peripheral instance. -#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. - -#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. -#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. -#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. -#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. -#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. -#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. -#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. -#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. -#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. -#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. -#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. -#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. -#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. -#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. -#define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. -#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. -#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. -#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. -#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000UL) // Maximum input frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. -#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. -#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000UL) // PLL VCO maximum frequency. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. -#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. -#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. -#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. -#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. - -#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. -#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. -#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. - -#define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA (1UL) // RSA support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1UL) // RSA support with key-wrapping is available. - -#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. -#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. - -#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. -#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. -#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. -#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. -#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. - -#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) -#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. - -#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. -#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. - -#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. - -#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. - -#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. - -#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. - -#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. - -#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1UL) // Number of available ethernet PHYs. -#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. - -#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. -#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. -#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. -#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. -#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. -#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. -#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). -#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). -#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. - -#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. -#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. -#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. - -#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x03FFUL) // Mask of channels that support event count input (has GTUPSR register). -#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. -#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. -#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x03FFUL) // Mask of channels that support dead time control. -#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. -#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. -#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. - -#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. -#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. -#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. -#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. -#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. -#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. -#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. -#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FF0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. - -#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. - -#define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. -#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. - -#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. -#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. - -#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. -#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. -#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. -#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. -#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. -#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. -#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. -#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. -#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. -#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. - -#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. -#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. -#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. -#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. -#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. -#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. -#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. -#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. - -#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. - -#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000UL) // Start address of the CS0 memory mapped region for OSPI. -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000UL) // Start address of the CS1 memory mapped region for OSPI. - -#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. -#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. - -#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. - -#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. -#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. -#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RISP_E11A. -#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. -#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. -#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. -#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. -#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. -#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. -#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. -#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. - -#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. -#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. -#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. -#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. -#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. -#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. - -#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x03F9UL) // Mask of channels with data compare match (DCCR) available. -#define BSP_FEATURE_SCI_CHANNELS (0x03FFUL) // Mask of available SCI channels. -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. -#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. -#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x06UL) // Mask of channels that can support LIN. -#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x06UL) // List of channels that do not support ABCSE functionality. -#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9UL) // Mask of channels which support CTS external pins. -#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x03F9UL) // Mask of channels which support the UART FIFO. -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. -#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. - -#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. - -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. - -#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. - -#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. -#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. -#define BSP_FEATURE_SPI_MAX_CHANNEL (2UL) // Number of available SPI channels. -#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. - -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. - -#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. - -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. - -#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. - -#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. - -#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) -#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. -#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. -#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. - -#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) -#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. -#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. - -#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) -#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. -#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. -#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. -#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. -#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. -#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. -#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. -#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. -#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. -#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_group_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_group_irq.h deleted file mode 100644 index 5aede0736..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_group_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GROUP_IRQ_H -#define BSP_GROUP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#ifndef BSP_OVERRIDE_GROUP_IRQ_T - -/** Which interrupts can have callbacks registered. */ -typedef enum e_bsp_grp_irq -{ - BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred - BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred - BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt - BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt - BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt - BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected - BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt - BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error - BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error - BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error - BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error - BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error - BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error - BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error -} bsp_grp_irq_t; - -#endif - -/* Callback type. */ -typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_group_interrupt_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_guard.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_guard.h deleted file mode 100644 index f1dc5a590..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_guard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GUARD_H -#define BSP_GUARD_H - -#include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUp2025-08-11CallbackSet(bsp_clock_up2025-08-11_callback_t p_callback, - bsp_clock_up2025-08-11_callback_args_t * p_callback_memory); - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_io.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_io.h deleted file mode 100644 index 418c75380..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_io.h +++ /dev/null @@ -1,465 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @defgroup BSP_IO BSP I/O access - * @ingroup RENESAS_COMMON - * @brief This module provides basic read/write access to port pins. - * - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_IO_H -#define BSP_IO_H - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) -#define BSP_IO_PRV_8BIT_MASK (0xFF) -#define BSP_IO_PWPR_B0WI_OFFSET (7U) -#define BSP_IO_PWPR_PFSWE_OFFSET (6U) -#define BSP_IO_PFS_PDR_OUTPUT (4U) -#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Levels that can be set and read for individual pins */ -typedef enum e_bsp_io_level -{ - BSP_IO_LEVEL_LOW = 0, ///< Low - BSP_IO_LEVEL_HIGH ///< High -} bsp_io_level_t; - -/** Direction of individual pins */ -typedef enum e_bsp_io_dir -{ - BSP_IO_DIRECTION_INPUT = 0, ///< Input - BSP_IO_DIRECTION_OUTPUT ///< Output -} bsp_io_direction_t; - -/** Superset list of all possible IO ports. */ -typedef enum e_bsp_io_port -{ - BSP_IO_PORT_00 = 0x0000, ///< IO port 0 - BSP_IO_PORT_01 = 0x0100, ///< IO port 1 - BSP_IO_PORT_02 = 0x0200, ///< IO port 2 - BSP_IO_PORT_03 = 0x0300, ///< IO port 3 - BSP_IO_PORT_04 = 0x0400, ///< IO port 4 - BSP_IO_PORT_05 = 0x0500, ///< IO port 5 - BSP_IO_PORT_06 = 0x0600, ///< IO port 6 - BSP_IO_PORT_07 = 0x0700, ///< IO port 7 - BSP_IO_PORT_08 = 0x0800, ///< IO port 8 - BSP_IO_PORT_09 = 0x0900, ///< IO port 9 - BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 - BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 - BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 - BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 - BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 -} bsp_io_port_t; - -/** Superset list of all possible IO port pins. */ -typedef enum e_bsp_io_port_pin_t -{ - BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 - BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port -} bsp_io_port_pin_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern volatile uint32_t g_protect_pfswe_counter; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Read the current input level of the pin. - * - * @param[in] pin The pin - * - * @retval Current input level - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) -{ - /* Read pin level. */ - return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; -} - -/*******************************************************************************************************************//** - * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS - * protection using R_BSP_PinAccessEnable() before calling this function. - * - * @param[in] pin The pin - * @param[in] level The level - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) -{ - /* Clear PMR, ASEL, ISEL and PODR bits. */ - uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; - pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; - - /* Set output level and pin direction to output. */ - uint32_t lvl = ((uint32_t) level | pfs_bits); -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); -#endif -} - -/*******************************************************************************************************************//** - * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling - * this function. - * - * @param[in] pin The pin - * @param[in] cfg Configuration for the pin (PmnPFS register setting) - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) -{ - /* Configure a pin. */ -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; -#endif -} - -/*******************************************************************************************************************//** - * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur - * via multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessEnable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** If this is first entry then allow writing of PFS. */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #endif - } - - /** Increment the protect counter */ - g_protect_pfswe_counter++; - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/*******************************************************************************************************************//** - * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via - * multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessDisable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** Is it safe to disable PFS register? */ - if (0 != g_protect_pfswe_counter) - { - /* Decrement the protect counter */ - g_protect_pfswe_counter--; - } - - /** Is it safe to disable writing of PFS? */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled - #endif - } - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/** @} (end addtogroup BSP_IO) */ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_irq.h deleted file mode 100644 index ad971f32e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_irq.h +++ /dev/null @@ -1,238 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_IRQ_H -#define BSP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @brief Sets the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @param[in] p_context ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - gp_renesas_isr_context[irq] = p_context; -} - -/*******************************************************************************************************************//** - * @brief Finds the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @return ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - return gp_renesas_isr_context[irq]; -} - -#if BSP_CFG_INLINE_IRQ_FUNCTIONS - - #if BSP_FEATURE_ICU_HAS_IELSR - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit - * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) -{ - /* Clear the IR bit in the selected IELSR register. */ - R_ICU->IELSR_b[irq].IR = 0U; - - /* Read back the IELSR register to ensure that the IR bit is cleared. - * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ - FSP_REGISTER_READ(R_ICU->IELSR[irq]); -} - - #endif - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) -{ - #if BSP_FEATURE_ICU_HAS_IELSR - - /* Clear the IR bit in the selected IELSR register. */ - R_BSP_IrqStatusClear(irq); - - /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ - __DMB(); - #endif - - /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context. - * - * @param[in] irq The IRQ to configure. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions - * every time a priority is configured in the NVIC. */ - #if (4U == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (33 == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (23 == __CORTEX_M) - NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); - #else - NVIC_SetPriority(irq, priority); - #endif - - /* Store the context. The context is recovered in the ISR. */ - R_FSP_IsrContextSet(irq, p_context); -} - -/*******************************************************************************************************************//** - * Enable the IRQ in the NVIC (Without clearing the pending bit). - * - * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex - * Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) -{ - /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions - * every time an interrupt is enabled in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - - __COMPILER_BARRIER(); - NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - __COMPILER_BARRIER(); -} - -/*******************************************************************************************************************//** - * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed - * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) -{ - /* Clear pending interrupts in the ICU and NVIC. */ - R_BSP_IrqClearPending(irq); - - /* Enable the IRQ in the NVIC. */ - R_BSP_IrqEnableNoClear(irq); -} - -/*******************************************************************************************************************//** - * Disables interrupts in the NVIC. - * - * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) -{ - /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - - __DSB(); - __ISB(); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. - * - * @param[in] irq Interrupt number. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - R_BSP_IrqCfg(irq, priority, p_context); - R_BSP_IrqEnable(irq); -} - -#else - #if BSP_FEATURE_ICU_HAS_IELSR -void R_BSP_IrqStatusClear(IRQn_Type irq); - - #endif -void R_BSP_IrqClearPending(IRQn_Type irq); -void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); -void R_BSP_IrqEnableNoClear(IRQn_Type const irq); -void R_BSP_IrqEnable(IRQn_Type const irq); -void R_BSP_IrqDisable(IRQn_Type const irq); -void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); - -#endif - -/*******************************************************************************************************************//** - * @internal - * @addtogroup BSP_MCU_PRV Internal BSP Documentation - * @ingroup RENESAS_INTERNAL - * @{ - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_irq_cfg(void); // Used internally by BSP - -/** @} (end addtogroup BSP_MCU_PRV) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_macl.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_macl.h deleted file mode 100644 index 416228d5c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_macl.h +++ /dev/null @@ -1,164 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_MACL -#define RENESAS_MACL - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include -#include "bsp_api.h" - -#if BSP_FEATURE_MACL_SUPPORTED - #if __has_include("arm_math_types.h") - -/* Ignore certain math warnings in ARM CMSIS DSP headers */ - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wsign-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" - #elif defined(__GNUC__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wfloat-conversion" - #endif - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_suppress=Pe223 - #endif - - #include "arm_math_types.h" - #include "dsp/basic_math_functions.h" - #include "dsp/matrix_functions.h" - #include "dsp/filtering_functions.h" - #include "dsp/support_functions.h" - #include "dsp/fast_math_functions.h" - - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_default=Pe223 - #endif - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - #pragma GCC diagnostic pop - #endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MACL - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Common macro used by MACL */ - #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) - #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) - - #define BSP_MACL_SHIFT_SIGN (0x80) - #define BSP_MACL_SHIFT_1_BIT (1U) - #define BSP_MACL_SHIFT_30_BIT (30U) - #define BSP_MACL_SHIFT_31_BIT (31U) - #define BSP_MACL_SHIFT_32_BIT (32U) - - #define BSP_MACL_32_BIT (32U) - - #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 - #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 - - #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 - #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 - - #define BSP_MACL_CLEAR_MULR_REG (0x0U) - - #define BSP_MACL_POSITIVE_NUM (0U) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, - const arm_matrix_instance_q31 * p_src_b, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); -void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, - q31_t scale_fract, - int32_t shift, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); -void R_BSP_MaclConvQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); -arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst, - uint32_t first_idx, - uint32_t num_points); - -void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); - -void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - q31_t * p_scratch_in, - uint32_t block_size); - -void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); - -/******************************************************************************************************************//** - * @} (end addtogroup BSP_MACL) - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - - #endif -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_api.h deleted file mode 100644 index 5dcb1cd45..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_api.h +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MCU_API_H -#define BSP_MCU_API_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -typedef struct st_bsp_event_info -{ - IRQn_Type irq; - elc_event_t event; -} bsp_event_info_t; - -typedef enum e_bsp_clocks_octaclk_div -{ - BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 - BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 - BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 - BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 - BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 - BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 - BSP_CLOCKS_OCTACLK_DIV_5 ///< Divide OCTA source clock by 5 -} bsp_clocks_octaclk_div_t; - -typedef enum e_bsp_clocks_source -{ - BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. - BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. - BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. - BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. - BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. - BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. - BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. -} bsp_clocks_source_t; - -typedef struct st_bsp_octaclk_settings -{ - bsp_clocks_source_t source_clock; ///< OCTACLK source clock - bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider -} bsp_octaclk_settings_t; - -void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); -void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); -fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); -void R_BSP_OctaclkUp2025-08-11(bsp_octaclk_settings_t * p_octaclk_setting); -void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_pn_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 41a88642b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BF3CFP - #define BSP_MCU_FEATURE_SET ('B') - #define BSP_ROM_SIZE_BYTES (1048576) - #define BSP_RAM_SIZE_BYTES (524288) - #define BSP_DATA_FLASH_SIZE_BYTES (8192) - #define BSP_PACKAGE_LQFP - #define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_family_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_family_cfg.h deleted file mode 100644 index a4c302306..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,394 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - - #include "bsp_mcu_device_pn_cfg.h" - #include "bsp_mcu_device_cfg.h" - #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" - #include "bsp_clock_cfg.h" - #define BSP_MCU_GROUP_RA6M5 (1) - #define BSP_LOCO_HZ (32768) - #define BSP_MOCO_HZ (8000000) - #define BSP_SUB_CLOCK_HZ (32768) - #if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (16000000) - #elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - - #define BSP_CFG_FLL_ENABLE (0) - - #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) - #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) - - #if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (0) - #endif - - /* TrustZone Settings */ - #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) - #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) - #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - - /* CMSIS TrustZone Settings */ - #define SCB_CSR_AIRCR_INIT (1) - #define SCB_AIRCR_BFHFNMINS_VAL (0) - #define SCB_AIRCR_SYSRESETREQS_VAL (1) - #define SCB_AIRCR_PRIS_VAL (0) - #define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL - #define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL - #define FPU_FPCCR_TS_VAL (1U) -#endif - #define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL - #define FPU_FPCCR_CLRONRET_VAL (1) -#endif - - /* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE - #define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - - /* Type 1 Peripheral Security Attribution */ - - /* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - - /* Type 2 Peripheral Security Attribution */ - - /* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR - /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ -#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) -#define BSP_TZ_CFG_LVDSAR (0U) -#else -#define BSP_TZ_CFG_LVDSAR (3U) -#endif -#endif - - /* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif - /* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - - /* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFE0E402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - - /* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - - /* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - - /* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - - /* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - - /* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - - /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED - #define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - - /* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - - /* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ - #define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - - /* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR - #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - - /* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA - /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ - #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - - /* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA - #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif - /* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB - #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - - /* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK - #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - - - #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) - #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) - #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) - #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) - #define OFS_SEQ5 (1 << 28) | (1 << 30) - #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - - /* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) -#else - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - - #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - - /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ - #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - - /* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL - #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - - /* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 - #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif - /* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 - #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif - /* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 - #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif - /* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 - #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif - /* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 - #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif - /* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 - #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif - /* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 - #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif - /* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 - #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif - /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 - #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif - /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 - #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif - /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 - #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif - /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 - #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif - /* Security Attribution for Bank Select Register */ -#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL - #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT - #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_info.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_info.h deleted file mode 100644 index 53c1844b3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mcu_info.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup BSP_MCU - * @defgroup BSP_MCU_RA6M5 RA6M5 - * @includedoc config_bsp_ra6m5_fsp.html - * @{ - **********************************************************************************************************************/ - -/** @} (end defgroup BSP_MCU_RA6M5) */ - -#ifndef BSP_MCU_INFO_H -#define BSP_MCU_INFO_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* BSP MCU Specific Includes. */ -#include "bsp_elc.h" -#include "bsp_feature.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -typedef elc_event_t bsp_interrupt_event_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mmf.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mmf.h deleted file mode 100644 index 9b7f1b143..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_mmf.h +++ /dev/null @@ -1,141 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MMF_H -#define BSP_MMF_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MEMORY_MIRROR_REG_KEY (0xDBU) -#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes -#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) - -/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ -#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Enum for state of Memory Mirror Function. */ -typedef enum e_mmf_state -{ - MEMORY_MIRROR_DISABLED = 0, - MEMORY_MIRROR_ENABLED = 1, -} mmf_state_t; - -/** Status instance of Memory Mirror Function. */ -typedef struct st_mmf_status -{ - mmf_state_t mmf_state; // Current state of Memory Mirror Region. - uint32_t mmf_cur_addr; // Current address in register MMSFR. -} mmf_status_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Get the current status of Memory Mirror. - * - * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. - * - * @retval FSP_SUCCESS MMF status retrieved successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. - * - * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that variable for storing the status of MMF was provided. */ - if (NULL == p_mmf_status) - { - return FSP_ERR_ASSERTION; - } - #endif - - p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; - p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_mmf_status); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/*******************************************************************************************************************//** - * Set address for MMF region. - * - * @param[in] addr Address of memory region to be mirrored into MMF region. - * - * @retval FSP_SUCCESS Address is set successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. - * - * This function sets the memory address to be mirrored by MMF. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that requested address is in supported range and must align with 128 */ - if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) - { - return FSP_ERR_INVALID_ADDRESS; - } - #endif - - /* If MMF is enabled, disable MMF before updating the address register. - * For disabling MMF, write 0xDB00 to register MMEN. */ - if (1U == R_MMF->MMEN_b.EN) - { - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); - } - - R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); - - /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into - * MMF region. */ - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(addr); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif - -/** @} (end addtogroup BSP_MCU) */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_module_stop.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_module_stop.h deleted file mode 100644 index d7312cbe8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_module_stop.h +++ /dev/null @@ -1,371 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MODULE_H -#define BSP_MODULE_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* MSTPCRA is located in R_MSTP for Star devices. */ - #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) -#else - -/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ - #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) -#endif - -/*******************************************************************************************************************//** - * Cancels the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= \ - (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/*******************************************************************************************************************//** - * Enables the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/** @} (end addtogroup BSP_MCU) */ - -#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) - #else - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - - #if BSP_MCU_GROUP_RA2A2 - -/* RA2A2 has a combination of AGT and AGTW. - * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) - * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) - * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) - * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) - */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + \ - BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); - - #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #else - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t -#else - #if (2U == BSP_FEATURE_ELC_VERSION) - #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #elif BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ - (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - \ - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #endif -#endif - -#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); - -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t - -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t -#else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#if BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); -#else - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#endif -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t -#if (BSP_PERIPHERAL_DAC8_PRESENT) - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t -#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_pin_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_pin_cfg.h deleted file mode 100644 index 9cef192cc..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_pin_cfg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_PIN_CFG_H_ -#define BSP_PIN_CFG_H_ -#include "r_ioport.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - - -extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BF3CFP.pincfg */ - -void BSP_PinConfigSecurityInit(); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif /* BSP_PIN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_register_protection.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_register_protection.h deleted file mode 100644 index ca4b64c20..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_register_protection.h +++ /dev/null @@ -1,60 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_REGISTER_PROTECTION_H -#define BSP_REGISTER_PROTECTION_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/** The different types of registers that can be protected. */ -typedef enum e_bsp_reg_protect -{ - /** Enables writing to the registers related to the clock generation circuit. */ - BSP_REG_PROTECT_CGC = 0, - - /** Enables writing to the registers related to operating modes, low power consumption, and battery backup - * function. */ - BSP_REG_PROTECT_OM_LPC_BATT, - - /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, - * LVD2CR1, LVD2SR. */ - BSP_REG_PROTECT_LVD, - - /** Enables writing to the registers related to the security function. */ - BSP_REG_PROTECT_SAR, -} bsp_reg_protect_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_register_protect_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_sdram.h deleted file mode 100644 index 5ba56a638..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SDRAM_H -#define BSP_SDRAM_H - -#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_SdramInit(bool init_memory); -void R_BSP_SdramSelfRefreshEnable(void); -void R_BSP_SdramSelfRefreshDisable(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_security.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_security.h deleted file mode 100644 index 3ceb51f92..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_security.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SECURITY_H -#define BSP_SECURITY_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_NonSecureEnter(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_tfu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_tfu.h deleted file mode 100644 index 98b09caee..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/bsp_tfu.h +++ /dev/null @@ -1,218 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_TFU -#define RENESAS_TFU - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* Mathematical Functions includes. */ -#ifdef __cplusplus - #include -#else - #include -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TFU_SUPPORTED - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - - #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f - - #ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) - -/* No form of inline is available, it happens only when -std=c89, gnu89 and - * above are OK */ - #warning \ - "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ - -/* gnu89 semantics of inline and extern inline are essentially the exact - * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) - #endif - #endif - #elif __ICCARM__ - #define BSP_TFU_INLINE - #else - #error "Compiler not supported!" - #endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Calculates sine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Sine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __sinf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - return R_TFU->SCDT1; -} - -/*******************************************************************************************************************//** - * Calculates cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __cosf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read cos from R_TFU->SCDT1 */ - return R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates sine and cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * @param[out] sin Sine value of an angle. - * @param[out] cos Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - *sin = R_TFU->SCDT1; - - /* Read sin from R_TFU->SCDT1 */ - *cos = R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-Axis cordinate value. - * @param[in] x_cord X-Axis cordinate value. - * - * @retval Arc tangent for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) -{ - /* Set X-cordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-cordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - return R_TFU->ATDT1; -} - -/*******************************************************************************************************************//** - * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * - * @retval Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * @param[out] atan2 Arc tangent for given values. - * @param[out] hypot Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - *atan2 = R_TFU->ATDT1; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - - #if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) - #endif - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif /* RENESAS_TFU */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_common_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_common_api.h deleted file mode 100644 index 871df7c5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_common_api.h +++ /dev/null @@ -1,380 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_COMMON_API_H -#define FSP_COMMON_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include -#include - -/* Includes FSP version macros. */ -#include "fsp_version.h" - -/*******************************************************************************************************************//** - * @ingroup RENESAS_COMMON - * @defgroup RENESAS_ERROR_CODES Common Error Codes - * All FSP modules share these common error codes. - * @{ - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing - * about using this implementation is that it does not take any extra RAM or ROM. */ - -#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) - -/** Determine if a C++ compiler is being used. - * If so, ensure that standard C is used to process the API information. */ -#if defined(__cplusplus) - #define FSP_CPP_HEADER extern "C" { - #define FSP_CPP_FOOTER } -#else - #define FSP_CPP_HEADER - #define FSP_CPP_FOOTER -#endif - -/** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically - * defined on the Secure side. */ -#define FSP_SECURE_ARGUMENT (NULL) - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Common error codes */ -typedef enum e_fsp_err -{ - FSP_SUCCESS = 0, - - FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed - FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location - FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter - FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist - FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode - FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API - FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open - FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy - FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h - FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked - FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP - FSP_ERR_OVERFLOW = 12, ///< Hardware overflow - FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow - FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration - FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result - FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason - FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met - FSP_ERR_ABORTED = 18, ///< An operation was aborted - FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled - FSP_ERR_TIMEOUT = 20, ///< Timeout error - FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied - FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied - FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation - FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed - FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed - FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made - FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition - FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU - FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state - FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed - FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed - FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete - FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found - FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback - FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer - FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed - - /* Start of RTOS only error codes */ - FSP_ERR_INTERNAL = 100, ///< Internal error - FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted - - /* Start of UART specific */ - FSP_ERR_FRAMING = 200, ///< Framing error occurs - FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects - FSP_ERR_PARITY = 202, ///< Parity error occurs - FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow - FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue - FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer - FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer - - /* Start of SPI specific */ - FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. - FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. - FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. - FSP_ERR_SPI_PARITY = 303, ///< Parity error. - FSP_ERR_OVERRUN = 304, ///< Overrun error. - - /* Start of CGC Specific */ - FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. - FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. - FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off - FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off - FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled - FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set - FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active - FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit - FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled - FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out - FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode - - /* Start of FLASH Specific */ - FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. - FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state - FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz - FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory - FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed - - /* Start of CAC Specific */ - FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate - - /* Start of IIRFA Specific */ - FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. - - /* Start of GLCD Specific */ - FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock - FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter - FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter - FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found - FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter - FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer - FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register up2025-08-11 - FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry - FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting - FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter - - /* Start of JPEG Specific */ - FSP_ERR_JPEG_ERR = 1100, ///< JPEG error - FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. - FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. - FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. - FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. - FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. - FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. - FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. - FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. - FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. - FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) - FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. - FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. - FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. - FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. - FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough - FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU - - /* Start of touch panel framework specific */ - FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed - - /* Start of IIRFA specific */ - FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected - FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected - - /* Start of IP specific */ - FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device - FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device - FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device - - /* Start of USB specific */ - FSP_ERR_USB_FAILED = 1500, - FSP_ERR_USB_BUSY = 1501, - FSP_ERR_USB_SIZE_SHORT = 1502, - FSP_ERR_USB_SIZE_OVER = 1503, - FSP_ERR_USB_NOT_OPEN = 1504, - FSP_ERR_USB_NOT_SUSPEND = 1505, - FSP_ERR_USB_PARAMETER = 1506, - - /* Start of Message framework specific */ - FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool - FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool - FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid - FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid - FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many - FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found - FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue - FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue - FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal - FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released - - /* Start of 2DG Driver specific */ - FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering - FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering - - /* Start of ETHER Driver specific */ - FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. - FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation - FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled - FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty - FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable - FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication - FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. - - /* Start of ETHER_PHY Driver specific */ - FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. - FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation - - /* Start of BYTEQ library specific */ - FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data - FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue - - /* Start of CTSU Driver specific */ - FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. - FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. - FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. - FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. - FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. - FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. - FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. - FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. - FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. - FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. - FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. - FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. - FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. - FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. - FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. - FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. - - /* Start of SDMMC specific */ - FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. - FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. - FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. - FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. - FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. - FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. - FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. - - /* Start of FX_IO specific */ - FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. - FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. - - /* Start of CAN specific */ - FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. - FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. - FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. - FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. - FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. - FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. - FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. - FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. - - /* Start of SF_WIFI Specific */ - FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. - FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. - FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed - FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode - FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. - FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. - FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point - FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error - FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter - FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value - FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result - FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured - FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure - FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure - FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error - - /* Start of SF_CELLULAR Specific */ - FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. - FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. - FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed - FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is upto2025-08-11 - FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed - FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. - FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. - FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed - - /* Start of SF_BLE specific */ - FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed - FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed - FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed - FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled - FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled - - /* Start of SF_BLE_ABS specific */ - FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. - FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. - - /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ - FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function - FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy - FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty - FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index - FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry - FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed - FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened - FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized - FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred - FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter - FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented - FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified - FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred - FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid - FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state - FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened - FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. - FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher - FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input 2025-08-11 is illegal. - FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. - - /* Start of Crypto RSIP specific (0x10100) */ - FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy - FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return - FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error - FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal - FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed - - /* Start of SF_CRYPTO specific */ - FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened - FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error - FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key - FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold - FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. - FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. - FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. - - /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. - * Refer to sf_cryoto_err.h for Crypto error codes. - */ - - /* Start of Sensor specific */ - FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. - FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. - FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. - - /* Start of COMMS specific */ - FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. -} fsp_err_t; - -/** @} */ - -/*********************************************************************************************************************** - * Function prototypes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_features.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_features.h deleted file mode 100644 index dd54197d7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_features.h +++ /dev/null @@ -1,297 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_FEATURES_H -#define FSP_FEATURES_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include - -/* Different compiler support. */ -#include "fsp_common_api.h" -#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Available modules. */ -typedef enum e_fsp_ip -{ - FSP_IP_CFLASH = 0, ///< Code Flash - FSP_IP_DFLASH = 1, ///< Data Flash - FSP_IP_RAM = 2, ///< RAM - FSP_IP_LVD = 3, ///< Low Voltage Detection - FSP_IP_CGC = 3, ///< Clock Generation Circuit - FSP_IP_LPM = 3, ///< Low Power Modes - FSP_IP_FCU = 4, ///< Flash Control Unit - FSP_IP_ICU = 6, ///< Interrupt Control Unit - FSP_IP_DMAC = 7, ///< DMA Controller - FSP_IP_DTC = 8, ///< Data Transfer Controller - FSP_IP_IOPORT = 9, ///< I/O Ports - FSP_IP_PFS = 10, ///< Pin Function Select - FSP_IP_ELC = 11, ///< Event Link Controller - FSP_IP_MPU = 13, ///< Memory Protection Unit - FSP_IP_MSTP = 14, ///< Module Stop - FSP_IP_MMF = 15, ///< Memory Mirror Function - FSP_IP_KEY = 16, ///< Key Interrupt Function - FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit - FSP_IP_DOC = 18, ///< Data Operation Circuit - FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator - FSP_IP_SCI = 20, ///< Serial Communications Interface - FSP_IP_IIC = 21, ///< I2C Bus Interface - FSP_IP_SPI = 22, ///< Serial Peripheral Interface - FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit - FSP_IP_SCE = 24, ///< Secure Cryptographic Engine - FSP_IP_SLCDC = 25, ///< Segment LCD Controller - FSP_IP_AES = 26, ///< Advanced Encryption Standard - FSP_IP_TRNG = 27, ///< True Random Number Generator - FSP_IP_FCACHE = 30, ///< Flash Cache - FSP_IP_SRAM = 31, ///< SRAM - FSP_IP_ADC = 32, ///< A/D Converter - FSP_IP_DAC = 33, ///< 12-Bit D/A Converter - FSP_IP_TSN = 34, ///< Temperature Sensor - FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit - FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator - FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator - FSP_IP_OPAMP = 38, ///< Operational Amplifier - FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter - FSP_IP_RTC = 40, ///< Real Time Clock - FSP_IP_WDT = 41, ///< Watch Dog Timer - FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer - FSP_IP_GPT = 43, ///< General PWM Timer - FSP_IP_POEG = 44, ///< Port Output Enable for GPT - FSP_IP_OPS = 45, ///< Output Phase Switch - FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer - FSP_IP_CAN = 48, ///< Controller Area Network - FSP_IP_IRDA = 49, ///< Infrared Data Association - FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface - FSP_IP_USBFS = 51, ///< USB Full Speed - FSP_IP_SDHI = 52, ///< SD/MMC Host Interface - FSP_IP_SRC = 53, ///< Sampling Rate Converter - FSP_IP_SSI = 54, ///< Serial Sound Interface - FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface - FSP_IP_ETHER = 64, ///< Ethernet MAC Controller - FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller - FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller - FSP_IP_PDC = 66, ///< Parallel Data Capture Unit - FSP_IP_GLCDC = 67, ///< Graphics LCD Controller - FSP_IP_DRW = 68, ///< 2D Drawing Engine - FSP_IP_JPEG = 69, ///< JPEG - FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter - FSP_IP_USBHS = 71, ///< USB High Speed - FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface - FSP_IP_CEC = 73, ///< HDMI CEC - FSP_IP_TFU = 74, ///< Trigonometric Function Unit - FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator - FSP_IP_CANFD = 76, ///< CAN-FD - FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT - FSP_IP_SAU = 78, ///< Serial Array Unit - FSP_IP_IICA = 79, ///< Serial Interface IICA - FSP_IP_UARTA = 80, ///< Serial Interface UARTA - FSP_IP_TAU = 81, ///< Timer Array Unit - FSP_IP_TML = 82, ///< 32-bit Interval Timer - FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator - FSP_IP_USBCC = 84, ///< USB Type-C Controller -} fsp_ip_t; - -/** Signals that can be mapped to an interrupt. */ -typedef enum e_fsp_signal -{ - FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH - FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH - FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END - FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B - FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A - FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B - FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ - FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ - FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A - FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B - FSP_SIGNAL_AGT_INT, ///< AGT INT - FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR - FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END - FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW - FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR - FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX - FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX - FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX - FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX - FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP - FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST - FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 - FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 - FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD - FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT - FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT - FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT - FSP_SIGNAL_CTSU_END = 0, ///< CTSU END - FSP_SIGNAL_CTSU_READ, ///< CTSU READ - FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE - FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI - FSP_SIGNAL_DALI_CLI, ///< DALI CLI - FSP_SIGNAL_DALI_SDI, ///< DALI SDI - FSP_SIGNAL_DALI_BPI, ///< DALI BPI - FSP_SIGNAL_DALI_FEI, ///< DALI FEI - FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI - FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT - FSP_SIGNAL_DOC_INT = 0, ///< DOC INT - FSP_SIGNAL_DRW_INT = 0, ///< DRW INT - FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE - FSP_SIGNAL_DTC_END, ///< DTC END - FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT - FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 - FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 - FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS - FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT - FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT - FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL - FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE - FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL - FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE - FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL - FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE - FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL - FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE - FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL - FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE - FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL - FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE - FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR - FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI - FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT - FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 - FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 - FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A - FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B - FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C - FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D - FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E - FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F - FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW - FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW - FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A - FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B - FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE - FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 - FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 - FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 - FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 - FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 - FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 - FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 - FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 - FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 - FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 - FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 - FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 - FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 - FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 - FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 - FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 - FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL - FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI - FSP_SIGNAL_IIC_RXI, ///< IIC RXI - FSP_SIGNAL_IIC_TEI, ///< IIC TEI - FSP_SIGNAL_IIC_TXI, ///< IIC TXI - FSP_SIGNAL_IIC_WUI, ///< IIC WUI - FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 - FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 - FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 - FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 - FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B - FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C - FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D - FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E - FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW - FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI - FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI - FSP_SIGNAL_KEY_INT = 0, ///< KEY INT - FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END - FSP_SIGNAL_PDC_INT, ///< PDC INT - FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY - FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT - FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT - FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM - FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD - FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY - FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY - FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY - FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG - FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY - FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 - FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 - FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK - FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY - FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 - FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 - FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 - FSP_SIGNAL_SCI_AM = 0, ///< SCI AM - FSP_SIGNAL_SCI_ERI, ///< SCI ERI - FSP_SIGNAL_SCI_RXI, ///< SCI RXI - FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI - FSP_SIGNAL_SCI_TEI, ///< SCI TEI - FSP_SIGNAL_SCI_TXI, ///< SCI TXI - FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI - FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND - FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND - FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS - FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD - FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ - FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO - FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI - FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE - FSP_SIGNAL_SPI_RXI, ///< SPI RXI - FSP_SIGNAL_SPI_TEI, ///< SPI TEI - FSP_SIGNAL_SPI_TXI, ///< SPI TXI - FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END - FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY - FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL - FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW - FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW - FSP_SIGNAL_SSI_INT = 0, ///< SSI INT - FSP_SIGNAL_SSI_RXI, ///< SSI RXI - FSP_SIGNAL_SSI_TXI, ///< SSI TXI - FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI - FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ - FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 - FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 - FSP_SIGNAL_USB_INT, ///< USB INT - FSP_SIGNAL_USB_RESUME, ///< USB RESUME - FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW - FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A - FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B - FSP_SIGNAL_ULPT_INT, ///< ULPT INT -} fsp_signal_t; - -typedef void (* fsp_vector_t)(void); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_version.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_version.h deleted file mode 100644 index 54b5c25ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/fsp_version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_VERSION_H - #define FSP_VERSION_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ - #include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup RENESAS_COMMON - * @{ - **********************************************************************************************************************/ - - #ifdef __cplusplus -extern "C" { - #endif - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** FSP pack major version. */ - #define FSP_VERSION_MAJOR (5U) - -/** FSP pack minor version. */ - #define FSP_VERSION_MINOR (8U) - -/** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) - -/** FSP pack version build number (currently unused). */ - #define FSP_VERSION_BUILD (0U) - -/** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.8.0") - -/** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.8.0") - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** FSP Pack version structure */ -typedef union st_fsp_pack_version -{ - /** Version id */ - uint32_t version_id; - - /** - * Code version parameters, little endian order. - */ - struct version_id_b_s - { - uint8_t build; ///< Build version of FSP Pack - uint8_t patch; ///< Patch version of FSP Pack - uint8_t minor; ///< Minor version of FSP Pack - uint8_t major; ///< Major version of FSP Pack - } version_id_b; -} fsp_pack_version_t; - -/** @} */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/instance/r_ioport.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/instance/r_ioport.h deleted file mode 100644 index 14abb229e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/instance/r_ioport.h +++ /dev/null @@ -1,522 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup IOPORT - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_H -#define R_IOPORT_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "r_ioport_api.h" -#if __has_include("r_ioport_cfg.h") - #include "r_ioport_cfg.h" -#endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ -typedef struct st_ioport_instance_ctrl -{ - uint32_t open; - void const * p_context; -} ioport_instance_ctrl_t; - -/* This typedef is here temporarily. See SWFLEX-144 for details. */ -/** Superset list of all possible IO port pins. */ -typedef enum e_ioport_port_pin_t -{ - IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 -} ioport_port_pin_t; - -#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #endif - - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an UARTA peripheral pin */ - IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; -#endif - -#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; -#endif - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const ioport_api_t g_ioport_on_ioport; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ - -fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); -fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); -fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); -fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); -fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); -fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); -fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t direction_values, - ioport_size_t mask); -fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); -fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t event_data, - ioport_size_t mask_value); -fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); -fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_IOPORT_H diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/periph/bsp_peripheral.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/periph/bsp_peripheral.h deleted file mode 100644 index bcaaf823c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/periph/bsp_peripheral.h +++ /dev/null @@ -1,211 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_PERIPHERAL_H -#define BSP_PERIPHERAL_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -// *UNCRUSTIFY-OFF* - -#define BSP_PERIPHERAL_ACMP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_PRESENT (1) -#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ADC_B_PRESENT (0) -#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_D_PRESENT (0) -#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AGT_PRESENT (1) -#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) -#define BSP_PERIPHERAL_AGTW_PRESENT (0) -#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AMI_PRESENT (0) -#define BSP_PERIPHERAL_ANALOG_PRESENT (1) -#define BSP_PERIPHERAL_BUS_PRESENT (1) -#define BSP_PERIPHERAL_CAC_PRESENT (1) -#define BSP_PERIPHERAL_CACHE_PRESENT (1) -#define BSP_PERIPHERAL_CAN_PRESENT (0) -#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_CANFD_PRESENT (1) -#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_CEC_PRESENT (1) -#define BSP_PERIPHERAL_CEU_PRESENT (0) -#define BSP_PERIPHERAL_CGC_PRESENT (1) -#define BSP_PERIPHERAL_CPSCU_PRESENT (1) -#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) -#define BSP_PERIPHERAL_CRC_PRESENT (1) -#define BSP_PERIPHERAL_CTSU_PRESENT (1) -#define BSP_PERIPHERAL_DAC_PRESENT (1) -#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DAC_B_PRESENT (0) -#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC8_PRESENT (0) -#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC12_PRESENT (1) -#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DEBUG_PRESENT (1) -#define BSP_PERIPHERAL_DMA_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) -#define BSP_PERIPHERAL_DOC_PRESENT (1) -#define BSP_PERIPHERAL_DOC_B_PRESENT (0) -#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) -#define BSP_PERIPHERAL_DRW_PRESENT (0) -#define BSP_PERIPHERAL_DSILINK_PRESENT (0) -#define BSP_PERIPHERAL_DTC_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ECCMB_PRESENT (1) -#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ELC_PRESENT (1) -#define BSP_PERIPHERAL_ELC_B_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_FACI_PRESENT (1) -#define BSP_PERIPHERAL_FCACHE_PRESENT (1) -#define BSP_PERIPHERAL_FLAD_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) -#define BSP_PERIPHERAL_GLCDC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_PRESENT (1) -#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) -#define BSP_PERIPHERAL_I3C_PRESENT (0) -#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ICU_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) -#define BSP_PERIPHERAL_IIC_PRESENT (1) -#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) -#define BSP_PERIPHERAL_IIC_B_PRESENT (0) -#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) -#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) -#define BSP_PERIPHERAL_IICA_PRESENT (0) -#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IPC_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_PRESENT (0) -#define BSP_PERIPHERAL_IRTC_PRESENT (0) -#define BSP_PERIPHERAL_IWDT_PRESENT (1) -#define BSP_PERIPHERAL_JPEG_PRESENT (0) -#define BSP_PERIPHERAL_KINT_PRESENT (0) -#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_MACL_PRESENT (0) -#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) -#define BSP_PERIPHERAL_MMF_PRESENT (0) -#define BSP_PERIPHERAL_MPU_PRESENT (1) -#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_MRMS_PRESENT (0) -#define BSP_PERIPHERAL_MRRGE_PRESENT (0) -#define BSP_PERIPHERAL_MSTP_PRESENT (1) -#define BSP_PERIPHERAL_OCD_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_OSPI_PRESENT (1) -#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) -#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) -#define BSP_PERIPHERAL_PDC_PRESENT (0) -#define BSP_PERIPHERAL_PFS_PRESENT (1) -#define BSP_PERIPHERAL_PFS_B_PRESENT (0) -#define BSP_PERIPHERAL_PMISC_PRESENT (0) -#define BSP_PERIPHERAL_PORGA_PRESENT (0) -#define BSP_PERIPHERAL_PORT_PRESENT (1) -#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) -#define BSP_PERIPHERAL_PSCU_PRESENT (1) -#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) -#define BSP_PERIPHERAL_QSPI_PRESENT (1) -#define BSP_PERIPHERAL_RADIO_PRESENT (0) -#define BSP_PERIPHERAL_RSIP_PRESENT (1) -#define BSP_PERIPHERAL_RTC_PRESENT (1) -#define BSP_PERIPHERAL_RTC_C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_PRESENT (0) -#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) -#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) -#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SCI_PRESENT (1) -#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_SCI_B_PRESENT (0) -#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDHI_PRESENT (1) -#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SLCDC_PRESENT (0) -#define BSP_PERIPHERAL_SPI_PRESENT (1) -#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_SPI_B_PRESENT (0) -#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SPMON_PRESENT (0) -#define BSP_PERIPHERAL_SRAM_PRESENT (1) -#define BSP_PERIPHERAL_SRC_PRESENT (0) -#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) -#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) -#define BSP_PERIPHERAL_TAU_PRESENT (0) -#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TFU_PRESENT (0) -#define BSP_PERIPHERAL_TML_PRESENT (0) -#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TRNG_PRESENT (0) -#define BSP_PERIPHERAL_TSD_PRESENT (1) -#define BSP_PERIPHERAL_TSN_PRESENT (1) -#define BSP_PERIPHERAL_TZF_PRESENT (1) -#define BSP_PERIPHERAL_UARTA_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ULPT_PRESENT (0) -#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_USB_PRESENT (1) -#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_USB_FS_PRESENT (1) -#define BSP_PERIPHERAL_USB_HS_PRESENT (1) -#define BSP_PERIPHERAL_USBCC_PRESENT (0) -#define BSP_PERIPHERAL_WDT_PRESENT (1) -#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_api.h deleted file mode 100644 index dcb104b06..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_SYSTEM_INTERFACES - * @defgroup IOPORT_API I/O Port Interface - * @brief Interface for accessing I/O ports and configuring I/O functionality. - * - * @section IOPORT_API_SUMMARY Summary - * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. - * Port and pin direction can be changed. - * - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_API_H -#define R_IOPORT_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common error codes and definitions. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -#ifndef BSP_OVERRIDE_IOPORT_SIZE_T - -/** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size -#endif - -/** Pin identifier and pin configuration value */ -typedef struct st_ioport_pin_cfg -{ - uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure - bsp_io_port_pin_t pin; ///< Pin identifier -} ioport_pin_cfg_t; - -/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ -typedef struct st_ioport_cfg -{ - uint16_t number_of_pins; ///< Number of pins for which there is configuration data - ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data - const void * p_extend; ///< Pointer to hardware extend configuration -} ioport_cfg_t; - -/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - */ -typedef void ioport_ctrl_t; - -/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ -typedef struct st_ioport_api -{ - /** Initialize internal driver data and initial pin configurations. Called during startup. Do - * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of - * multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Close the API. - * - * @param[in] p_ctrl Pointer to control structure. - **/ - fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); - - /** Configure multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Configure settings for an individual pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] cfg Configuration options for the pin. - */ - fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); - - /** Read the event input data of the specified pin and return the level. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_event Pointer to return the event data. - */ - fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); - - /** Write pin event data. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin event data is to be written to. - * @param[in] pin_value Level to be written to pin output event. - */ - fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); - - /** Read level of a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_value Pointer to return the pin level. - */ - fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); - - /** Write specified level to a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be written to. - * @param[in] level State to be written to the pin. - */ - fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); - - /** Set the direction of one or more pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port. - * @param[in] mask Mask controlling which pins on the port are to be configured. - */ - fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, - ioport_size_t mask); - - /** Read captured event data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_event_data Pointer to return the event data. - */ - fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); - - /** Write event output data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port event data will be written to. - * @param[in] event_data Data to be written as event data to specified port. - * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. - * being written to port. - */ - fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, - ioport_size_t mask_value); - - /** Read states of pins on the specified port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_port_value Pointer to return the port value. - */ - fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); - - /** Write to multiple pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be written to. - * @param[in] value Value to be written to the port. - * @param[in] mask Mask controlling which pins on the port are written to. - */ - fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); -} ioport_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_ioport_instance -{ - ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - ioport_api_t const * p_api; ///< Pointer to the API structure for this instance -} ioport_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT_API) - **********************************************************************************************************************/ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_cfg.h deleted file mode 100644 index d2688bf5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/r_ioport_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#ifdef __cplusplus -} -#endif -#endif /* R_IOPORT_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/renesas.h b/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/renesas.h deleted file mode 100644 index 41098a054..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/thirdparty/ra6m5bf/renesas.h +++ /dev/null @@ -1,154 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* Ensure Renesas MCU variation definitions are included to ensure MCU - * specific register variations are handled correctly. */ -#ifndef BSP_FEATURE_H - #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." -#endif - -/** @addtogroup Renesas - * @{ - */ - -/** @addtogroup RA - * @{ - */ - -#ifndef RA_H - #define RA_H - - #ifdef __cplusplus -extern "C" { - #endif - - #include "cmsis_compiler.h" - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - - #if BSP_MCU_GROUP_RA0E1 - #include "R7FA0E107.h" - #elif BSP_MCU_GROUP_RA2A1 - #include "R7FA2A1AB.h" - #elif BSP_MCU_GROUP_RA2A2 - #include "R7FA2A2AD.h" - #elif BSP_MCU_GROUP_RA2E1 - #include "R7FA2E1A9.h" - #elif BSP_MCU_GROUP_RA2E2 - #include "R7FA2E2A7.h" - #elif BSP_MCU_GROUP_RA2E3 - #include "R7FA2E307.h" - #elif BSP_MCU_GROUP_RA2L1 - #include "R7FA2L1AB.h" - #elif BSP_MCU_GROUP_RA4E1 - #include "R7FA4E10D.h" - #elif BSP_MCU_GROUP_RA4E2 - #include "R7FA4E2B9.h" - #elif BSP_MCU_GROUP_RA4M1 - #include "R7FA4M1AB.h" - #elif BSP_MCU_GROUP_RA4M2 - #include "R7FA4M2AD.h" - #elif BSP_MCU_GROUP_RA4M3 - #include "R7FA4M3AF.h" - #elif BSP_MCU_GROUP_RA4T1 - #include "R7FA4T1BB.h" - #elif BSP_MCU_GROUP_RA4W1 - #include "R7FA4W1AD.h" - #elif BSP_MCU_GROUP_RA4L1 - #include "R7FA4L1BD.h" - #elif BSP_MCU_GROUP_RA6E1 - #include "R7FA6E10F.h" - #elif BSP_MCU_GROUP_RA6E2 - #include "R7FA6E2BB.h" - #elif BSP_MCU_GROUP_RA6M1 - #include "R7FA6M1AD.h" - #elif BSP_MCU_GROUP_RA6M2 - #include "R7FA6M2AF.h" - #elif BSP_MCU_GROUP_RA6M3 - #include "R7FA6M3AH.h" - #elif BSP_MCU_GROUP_RA6M4 - #include "R7FA6M4AF.h" - #elif BSP_MCU_GROUP_RA6M5 - #include "R7FA6M5BH.h" - #elif BSP_MCU_GROUP_RA6T1 - #include "R7FA6T1AD.h" - #elif BSP_MCU_GROUP_RA6T2 - #include "R7FA6T2BD.h" - #elif BSP_MCU_GROUP_RA6T3 - #include "R7FA6T3BB.h" - #elif BSP_MCU_GROUP_RA8M1 - #include "R7FA8M1AH.h" - #elif BSP_MCU_GROUP_RA8D1 - #include "R7FA8D1BH.h" - #elif BSP_MCU_GROUP_RA8T1 - #include "R7FA8T1AH.h" - #elif BSP_MCU_GROUP_RA8E1 - #include "R7FA8E1AF.h" - #else - #if __has_include("renesas_internal.h") - #include "renesas_internal.h" - #else - #warning "Unsupported MCU" - #endif - #endif - -/* - * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB - * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 - * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: - * - * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | - * |-----------|------------|------------------------| - * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | - * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | - * - * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ - * - * IAR is currently the only toolchain producing the correct __ARM_ARCH value. - * - *- See https://github.com/ARM-software/CMSIS_6/issues/159 - */ - #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 - #undef __ARM_ARCH - #define __ARM_ARCH 801 - #endif - - #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M4 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) - #define RENESAS_CORTEX_M23 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M33 - #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M85 - #else - #warning Unsupported Architecture - #endif - - #ifdef __cplusplus -} - #endif - -#endif /* RA_H */ - -/** @} */ /* End of group RA */ - -/** @} */ /* End of group Renesas */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/R7FA6M5BH.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/R7FA6M5BH.h deleted file mode 100644 index ff08df73f..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/R7FA6M5BH.h +++ /dev/null @@ -1,29959 +0,0 @@ -/* - * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause - * - * @file ./out/R7FA6M5BH.h - * @brief CMSIS HeaderFile - * @version 1.10.08 - */ - -/** @addtogroup Renesas Electronics Corporation - * @{ - */ - -/** @addtogroup R7FA6M5BH - * @{ - */ - -#ifndef R7FA6M5BH_H - #define R7FA6M5BH_H - - #ifdef __cplusplus -extern "C" { - #endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ - #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ - #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ - #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ - #define __MPU_PRESENT 1 /*!< MPU present */ - #define __FPU_PRESENT 1 /*!< FPU present */ - #define __FPU_DP 0 /*!< Double Precision FPU */ - #define __DSP_PRESENT 1 /*!< DSP extension present */ - #define __SAUREGION_PRESENT 0 /*!< SAU region present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - - #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ - #include "system.h" /*!< R7FA6M5BH System */ - - #ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I - #endif - #ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O - #endif - #ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO - #endif - -/* ======================================== Start of section using anonymous unions ======================================== */ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined(__ICCARM__) - #pragma language=extended - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning 586 - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #else - #warning Not supported compiler type - #endif - -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - -/** - * @brief R_BUS_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ - - struct - { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; - }; - - union - { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ - - struct - { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; - }; - __IM uint32_t RESERVED1; -} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_CSb [CSb] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ - - struct - { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; - }; - __IM uint16_t RESERVED1[3]; - - union - { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ - - struct - { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; - }; - __IM uint16_t RESERVED2[2]; -} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ - - struct - { - __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint8_t : 3; - __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ - uint8_t : 2; - } SDCCR_b; - }; - - union - { - __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ - - struct - { - __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ - uint8_t : 7; - } SDCMOD_b; - }; - - union - { - __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ - - struct - { - __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ - uint8_t : 7; - } SDAMOD_b; - }; - __IM uint8_t RESERVED; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ - - struct - { - __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ - uint8_t : 7; - } SDSELF_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ - - struct - { - __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ - __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count - * Setting. ( REFW+1 Cycles ) */ - } SDRFCR_b; - }; - - union - { - __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ - - struct - { - __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ - uint8_t : 7; - } SDRFEN_b; - }; - __IM uint8_t RESERVED4; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ - - struct - { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ - - struct - { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; - - union - { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ - - struct - { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ - - struct - { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; - }; - - union - { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ - - struct - { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ - uint16_t : 1; - } SDMOD_b; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; - - union - { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ - - struct - { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; - }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ - -/** - * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ - } ADD_b; - }; - - union - { - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ - } STAT_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ - - struct - { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ - - struct - { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ - - struct - { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ - - struct - { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ - __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ - uint8_t : 2; - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - - struct - { - __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when - * a bus error occurs */ - uint32_t : 31; - } IRQEN_b; - }; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ - - struct - { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; - }; - }; - __IM uint32_t RESERVED3; -} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[36]; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ - - struct - { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } STAT_b; - }; - __IM uint8_t RESERVED1[7]; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ - - struct - { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } CLR_b; - }; -} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ - -/** - * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } MRE0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } FLBI_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S0BI_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S1BI_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S2BI_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S3BI_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } STBYSBI_b; - }; - __IM uint32_t RESERVED7; - - union - { - union - { - __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } ECBI_b; - }; - - union - { - __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI0BI_b; - }; - }; - __IM uint32_t RESERVED8; - - union - { - union - { - __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } EOBI_b; - }; - - union - { - __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI1BI_b; - }; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PBBI_b; - }; - __IM uint32_t RESERVED10; - - union - { - union - { - __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PABI_b; - }; - - union - { - __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU0SAHBI_b; - }; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PSBI_b; - }; -} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ - -/** - * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } FHBI_b; - }; - - union - { - __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } MRC0BI_b; - }; - }; - __IM uint32_t RESERVED[5]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S1BI_b; - }; -} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ - -/** - * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ - - struct - { - __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read - * Write. */ - - struct - { - __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write - * Status. */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - - struct - { - __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ - __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ - __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ - uint16_t : 13; - } BUSOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } BUSOADPT_b; - }; - __IM uint16_t RESERVED1[5]; - - union - { - __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection - * Register. */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ - } MSAOAD_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } MSAPT_b; - }; -} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ - -/** - * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ - - struct - { - __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ - __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ - __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ - __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ - __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ - __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ - __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ - __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ - __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ - __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ - __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ - __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ - __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ - __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ - __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ - __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ - __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ - __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ - __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ - __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ - __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ - __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ - __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ - __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ - __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ - __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ - __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ - __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ - __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ - __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ - __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ - __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ - } STAT_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ - - struct - { - __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ - __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ - __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ - __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ - __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ - __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ - __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ - __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ - __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ - __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ - __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ - __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ - __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ - __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ - __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ - __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ - __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ - __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ - __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ - __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ - __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ - __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ - __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ - __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ - __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ - __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ - __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ - __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ - __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ - __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ - __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ - __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ - } CLR_b; - }; -} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ - -/** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - - struct - { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ - uint16_t : 2; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ - uint16_t : 10; - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) - */ -typedef struct -{ - union - { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ - - struct - { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; - }; - - union - { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ - - struct - { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; - }; - - union - { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ - - struct - { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; - }; - - union - { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ - - struct - { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; - }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ - - struct - { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; - }; - - union - { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ - - struct - { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ - - struct - { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; - }; - - union - { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ - - struct - { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; - }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ - union - { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ - - struct - { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; - }; - - union - { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct - { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - - struct - { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - - struct - { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct - { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ - - struct - { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - - struct - { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - - struct - { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ - - struct - { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ - - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ - union - { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - - struct - { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; - }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ - union - { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ - - struct - { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; - }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) - */ -typedef struct -{ - union - { - __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ - uint16_t : 12; - } AC_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ - - struct - { - __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. - * NOTE: Some low-order bits are fixed to 0. */ - } S_b; - }; - - union - { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ - - struct - { - __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination. NOTE: Some low-order - * bits are fixed to 1. */ - } E_b; - }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } EN_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } ENPT_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_SEC_b; - }; - __IM uint16_t RESERVED3; - __IM uint32_t RESERVED4[60]; - __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ - __IM uint32_t RESERVED5[32]; -} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ - union - { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ - - struct - { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; - }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; - - union - { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union - { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union - { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; - - union - { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; - }; - __IM uint8_t RESERVED3[3]; - - union - { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; - - union - { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; - }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; - }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; - }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ - union - { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ - - struct - { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; - }; - - union - { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ - - struct - { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; - }; - - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; - - union - { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct - { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; - - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ - - struct - { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; - - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ - - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; - - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; - }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ - - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct - { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - - struct - { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ - - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct - { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ - - struct - { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED23[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ - - struct - { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; - }; - - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; - - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ - - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ - __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ - uint32_t : 2; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ - uint32_t : 27; - } MSSAR_b; - }; - - union - { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - - union - { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ - - struct - { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; - }; - - union - { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; - }; - - union - { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ - - struct - { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; - }; - - union - { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ - - struct - { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; - }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ - - union - { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - - union - { - __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ - }; - __IM uint32_t RESERVED4[58]; - - union - { - union - { - __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ - uint32_t : 31; - } BUSMABT_b; - }; - __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - }; - __IM uint32_t RESERVED5[46]; - - union - { - __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ - __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ - }; - __IM uint32_t RESERVED6[33]; - - union - { - __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ - - struct - { - __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ - uint32_t : 2; - __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ - uint32_t : 12; - __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ - uint32_t : 15; - } BUSDIVBYP_b; - }; - __IM uint32_t RESERVED7[63]; - - union - { - __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ - - struct - { - __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ - uint16_t : 15; - } BUSTHRPUT_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[255]; - __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED10[16]; - - union - { - __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address - * and Read/Write Status registers. */ - }; - __IM uint32_t RESERVED11[28]; - - union - { - __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ - __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ - }; - __IM uint32_t RESERVED12[16]; - __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED13[5]; - __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ -} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ - union - { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; - }; - - union - { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct - { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; - }; - - union - { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - - struct - { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; - - union - { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - - struct - { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; - }; - - union - { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ - - struct - { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - - union - { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; - }; - - union - { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ - - struct - { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; - }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; - }; - - union - { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - - struct - { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; - }; - - union - { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ - - struct - { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; - }; - - union - { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ - - struct - { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; - }; - - union - { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ - - struct - { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; - }; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - - struct - { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; - }; - - union - { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ - - struct - { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; - }; - - union - { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - - struct - { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; - }; - - union - { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; - }; - - union - { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; - }; - __IM uint32_t RESERVED3[18]; - - union - { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ - - struct - { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; - }; - __IM uint32_t RESERVED4[18]; - - union - { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ - - struct - { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; - }; - __IM uint32_t RESERVED5[18]; - - union - { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; - }; - __IM uint32_t RESERVED6[18]; - - union - { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct - { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; - }; - - union - { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; - }; - - union - { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ - - struct - { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; - }; - - union - { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; - }; - - union - { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; - }; - - union - { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ - - struct - { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; - }; - - union - { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ - - struct - { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; - }; - __IM uint32_t RESERVED7[2]; - - union - { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ - - struct - { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; - }; - __IM uint32_t RESERVED8[288]; - - union - { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ - - struct - { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; - }; - __IM uint32_t RESERVED9[288]; - - union - { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ - - struct - { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; - }; - __IM uint32_t RESERVED10[36]; - - union - { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ - - struct - { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; - }; - __IM uint32_t RESERVED11[36]; - - union - { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ - - struct - { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; - }; - __IM uint32_t RESERVED12[36]; - - union - { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ - - struct - { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; - }; - __IM uint32_t RESERVED13[36]; - - union - { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ - - struct - { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; - }; - __IM uint32_t RESERVED14[40]; - - union - { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; - }; - __IM uint32_t RESERVED15[6]; - - union - { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; - }; - __IM uint32_t RESERVED16[6]; - - union - { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; - }; - __IM uint32_t RESERVED17[6]; - - union - { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; - }; - __IM uint32_t RESERVED18[6]; - - union - { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; - }; - __IM uint32_t RESERVED19[6]; - - union - { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; - }; - __IM uint32_t RESERVED20[6]; - - union - { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; - }; - __IM uint32_t RESERVED21[6]; - - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; - - union - { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; - }; - __IM uint32_t RESERVED23[6]; - - union - { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; - }; - __IM uint32_t RESERVED24[6]; - - union - { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; - }; - __IM uint32_t RESERVED25[6]; - - union - { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; - }; - __IM uint32_t RESERVED26[6]; - - union - { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - - struct - { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; - }; - - union - { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ - - struct - { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; - }; - __IM uint32_t RESERVED27; - - union - { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; - }; - - union - { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ - - struct - { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; - }; - __IM uint32_t RESERVED28[24]; - - union - { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ - - struct - { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; - }; - __IM uint32_t RESERVED29[6]; - - union - { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ - - struct - { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; - }; - __IM uint32_t RESERVED30[6]; - - union - { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ - - struct - { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; - }; - __IM uint32_t RESERVED31[46]; - - union - { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ - - struct - { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; - }; - __IM uint32_t RESERVED32; - - union - { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ - - struct - { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; - }; - - union - { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ - - struct - { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; - }; - __IM uint32_t RESERVED33; - - union - { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ - - struct - { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; - }; - __IM uint32_t RESERVED34; - - union - { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ - - struct - { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; - }; - - union - { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ - - struct - { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ - - struct - { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ - - struct - { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; - - union - { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ - - struct - { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; - }; - - union - { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ - - struct - { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; - }; - __IM uint32_t RESERVED36[2]; - - union - { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ - - struct - { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; - }; - - union - { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ - - struct - { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; - }; - __IM uint32_t RESERVED37[2]; - - union - { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; - }; - __IM uint32_t RESERVED38[10]; - - union - { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ - - struct - { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; - }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; - - union - { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ - - struct - { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; - }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ - -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; - - union - { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - - struct - { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; - }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ - -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ - union - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - - struct - { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; - }; - - union - { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - - struct - { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; - }; - - union - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ - - struct - { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; - }; - - union - { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct - { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; - - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ - - struct - { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; - }; - - union - { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ - - struct - { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; - }; - - union - { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; - }; - - union - { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; - }; - - union - { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ - - struct - { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; - }; - - union - { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ - - struct - { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; - }; - - union - { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; - }; - - union - { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ - - struct - { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; - }; - - union - { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ - - struct - { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; - }; - - union - { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ - - struct - { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; - }; - - union - { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ - - struct - { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; - }; - - union - { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ - - struct - { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; - }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ - -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ - union - { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ - - struct - { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; - }; - - union - { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; - }; - - union - { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; - }; - - union - { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; - }; - - union - { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ - - struct - { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; - }; - - union - { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; - }; - - union - { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ - - struct - { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; - }; - __IM uint16_t RESERVED[9]; - - union - { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; - - union - { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ - - struct - { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ - union - { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct - { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct - { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 12; - __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ - __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; - __IM uint32_t RESERVED1[123]; - - union - { - __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ - - struct - { - __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ - __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ - uint32_t : 6; - __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ - uint32_t : 21; - } FSBLSTAT_b; - }; -} R_DEBUG_Type; /*!< Size = 516 (0x204) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ - -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ - union - { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ - - struct - { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ - - struct - { - __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ - uint8_t : 3; - __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ - uint8_t : 3; - } DMCTL_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[11]; - - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ - - struct - { - __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ - uint32_t : 4; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; - }; - __IM uint32_t RESERVED6[15]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ - union - { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ - - struct - { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; - }; - - union - { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ - - struct - { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; - }; - - union - { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; - }; - - union - { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; - }; - - union - { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ - - struct - { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ - - struct - { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; - }; - - union - { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ - - struct - { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-08-12 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-08-12 Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-08-12 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-08-12 Mode */ - } DMAMD_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ - - struct - { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-08-12 mode for transfer source or destination. */ - } DMOFR_b; - }; - - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ - - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - - union - { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ - - struct - { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; - }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ - - union - { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct - { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; - - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ - - struct - { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; - }; - - union - { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct - { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ - -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ - - struct - { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ - - struct - { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; - }; - - union - { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ - - struct - { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; - }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ - -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ - union - { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_b; - }; - - union - { - __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ - - struct - { - __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ - uint8_t : 7; - } DTCADMOD_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ - - struct - { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ - - struct - { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; - }; - - union - { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_SEC_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - - union - { - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_SEC_b; - }; - - union - { - __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ - - struct - { - __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ - } DTCDISP_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ - - struct - { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; - }; - - union - { - __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ - } DTCIBR_b; - }; - - union - { - __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ - - struct - { - __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ - uint8_t : 7; - } DTCOR_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ - - struct - { - __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ - uint16_t : 7; - __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ - } DTCSQE_b; - }; - __IM uint16_t RESERVED10; -} R_DTC_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ - union - { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; - }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; - - union - { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ - - struct - { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ - - struct - { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ - -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ -{ - union - { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ - - struct - { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ - - struct - { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ - - struct - { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ - - struct - { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ - - struct - { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ - - struct - { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; - }; - __IM uint32_t RESERVED5[5]; - - union - { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ - - struct - { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ - - struct - { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; - }; - - union - { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ - - struct - { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; - }; - - union - { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ - - struct - { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ - - struct - { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; - }; - - union - { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ - - struct - { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; - }; - __IM uint32_t RESERVED8[20]; - - union - { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ - - struct - { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ - - struct - { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ - - struct - { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ - - union - { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ - - struct - { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; - }; - - union - { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ - - struct - { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ - - struct - { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; - }; - - union - { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ - - struct - { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union - { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; - }; - - union - { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; - }; - - union - { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ - - struct - { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; - }; - - union - { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ - - struct - { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; - }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ - -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ -{ - union - { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ - - struct - { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ - - struct - { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ - - struct - { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ - - struct - { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ - - struct - { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ - - struct - { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ - - struct - { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; - }; - __IM uint32_t RESERVED11[2]; - - union - { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ - - struct - { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; - }; - - union - { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ - - struct - { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; - }; - - union - { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ - - struct - { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; - }; - - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ - - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ - - struct - { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; - }; - - union - { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ - - struct - { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; - }; - __IM uint32_t RESERVED13[18]; - - union - { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ - - struct - { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; - }; - - union - { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; - }; - __IM uint32_t RESERVED14; - - union - { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ - - struct - { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; - }; - - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ - union - { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ - -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ - - struct - { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; - - union - { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ - - struct - { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; - }; - - union - { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ - - struct - { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union - { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ - - struct - { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ - - struct - { - __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ - uint8_t : 5; - } FCNTSELR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR0_b; - }; - - union - { - __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR1_b; - }; - __IM uint32_t RESERVED12[9]; - - union - { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ - - struct - { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; - }; - __IM uint16_t RESERVED13; - - union - { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ - - struct - { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; - }; - __IM uint16_t RESERVED14; - - union - { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ - - struct - { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; - }; - - union - { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ - - struct - { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; - }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16; - - union - { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ - - struct - { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; - }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[4]; - - union - { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ - - struct - { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; - }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[11]; - - union - { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ - - struct - { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; - - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ - - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; - - union - { - union - { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ - - struct - { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; - }; - - union - { - __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ - - struct - { - __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address - * or the last blank checked address which is found in 'Blank - * Check' command execution. */ - uint32_t : 8; - } FBCADDR_b; - }; - }; - - union - { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ - - struct - { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; - }; - - union - { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ - - struct - { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ - - struct - { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ - - struct - { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; - }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; - - union - { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ - - struct - { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-08-12 Register */ - - struct - { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-08-12 Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; - - union - { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ - - struct - { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; - - union - { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ - - struct - { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ - uint16_t : 6; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ - __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ - uint16_t : 4; - __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ - } FSAR_b; - }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief General PWM Timer (R_GPT0) - */ - -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ - union - { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ - - struct - { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; - }; - - union - { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ - - struct - { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; - }; - - union - { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ - - struct - { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; - }; - - union - { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ - - struct - { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; - }; - - union - { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ - - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; - }; - - union - { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ - - struct - { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; - }; - - union - { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ - - struct - { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; - - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ - - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; - - union - { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ - - struct - { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ - uint32_t : 7; - } GTICASR_b; - }; - - union - { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ - - struct - { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ - uint32_t : 7; - } GTICBSR_b; - }; - - union - { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ - - struct - { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 3; - __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ - __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ - uint32_t : 2; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; - }; - - union - { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ - - struct - { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection - * timing setting */ - uint32_t : 3; - } GTUDDTYC_b; - }; - - union - { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ - - struct - { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-08-12.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-08-12.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; - }; - - union - { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ - - struct - { - __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; - }; - - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ - - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; - }; - - union - { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ - - struct - { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; - }; - - union - { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ - - struct - { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; - }; - - union - { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ - - struct - { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; - }; - - union - { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ - - struct - { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; - }; - - union - { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ - - struct - { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; - }; - - union - { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ - - struct - { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; - - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; - - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; - - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ - - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; - - union - { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; - }; - - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ - - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; - - union - { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; - }; - - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ - - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; - }; - - union - { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ - - struct - { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; - }; - - union - { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ - - struct - { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; - }; - - union - { - __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Control Register */ - - struct - { - __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter - * 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 - * Skipping Count Setting */ - __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping - * Counter 1 Initial Value */ - __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping - * Counter 1 */ - __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping - * 2 Skipping Count Setting */ - __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Initial Value */ - __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping - * Counter 2 */ - } GTADCMSC_b; - }; - - union - { - __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Setting Register */ - - struct - { - __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 9; - __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 9; - } GTADCMSS_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ - - struct - { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; - }; - - union - { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ - - struct - { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; - }; - __IM uint32_t RESERVED1[2]; - - union - { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ - - struct - { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; - }; - - union - { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ - - struct - { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; - }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ - -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ - union - { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ - - struct - { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; - }; - __IM uint32_t RESERVED[15]; - - union - { - __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection - * Register */ - - struct - { - __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ - uint16_t : 7; - __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ - } GTONCWP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling - * Register */ - - struct - { - __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ - uint16_t : 3; - __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ - __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ - uint16_t : 7; - } GTONCCR_b; - }; - __IM uint16_t RESERVED2; -} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ - -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ - union - { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ - - struct - { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 1; - __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; - }; - __IM uint32_t RESERVED[60]; - - union - { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - - struct - { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - - union - { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ - - struct - { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; - }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; - - union - { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ - - struct - { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; - }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; - - union - { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ - - struct - { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; - - union - { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - - struct - { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - - union - { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ - - struct - { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; - }; - - union - { - __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ - - struct - { - __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze - * Mode */ - uint32_t : 27; - } WUPEN2_b; - }; - __IM uint32_t RESERVED10[5]; - - union - { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ - - struct - { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; - }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; - __IM uint32_t RESERVED16[24]; - - union - { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ - - struct - { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; - }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ - union - { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ - - struct - { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; - }; - - union - { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ - - struct - { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; - }; - - union - { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ - - struct - { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; - }; - - union - { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ - - struct - { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; - }; - - union - { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ - - struct - { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; - }; - - union - { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ - - struct - { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; - }; - - union - { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ - - struct - { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; - }; - - union - { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ - - struct - { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; - }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ - - union - { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ - - struct - { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; - }; - - union - { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ - - struct - { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; - }; - - union - { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ - - struct - { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; - }; - - union - { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ - - struct - { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ - - struct - { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; - }; - - union - { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ - - struct - { - __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; - }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; - }; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; - - union - { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ - -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ - union - { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ - - struct - { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ - - struct - { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; - }; - - union - { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ - - struct - { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; - }; - - union - { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ - - struct - { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ - - struct - { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 2; - __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ - __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ - __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ - __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ - uint32_t : 3; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; - }; - - union - { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; - }; - - union - { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; - }; - - union - { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; - }; - - union - { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ - - struct - { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ - - struct - { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; - }; - __IM uint32_t RESERVED4[4]; - - union - { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ - - struct - { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ - - struct - { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; - }; - - union - { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ - - struct - { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ - uint32_t : 13; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; - }; - - union - { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ - - struct - { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; - }; - - union - { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ - - struct - { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; - }; - - union - { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ - - struct - { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; - }; - - union - { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ - - struct - { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; - }; - - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ - - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; - - union - { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ - - struct - { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; - }; - - union - { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ - - struct - { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; - }; - - union - { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ - - struct - { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ - - struct - { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ - - struct - { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; - }; - - union - { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ - - struct - { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; - }; - __IM uint32_t RESERVED9[2]; - - union - { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ - - struct - { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; - }; - __IM uint32_t RESERVED10[3]; - - union - { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ - - struct - { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; - }; - __IM uint32_t RESERVED11[23]; - - union - { - __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ - - struct - { - __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ - uint32_t : 31; - } STCTL_b; - }; - - union - { - __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ - - struct - { - __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ - __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ - __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ - uint32_t : 5; - __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ - uint32_t : 16; - } ATCTL_b; - }; - - union - { - __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ - - struct - { - __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ - uint32_t : 31; - } ATTRG_b; - }; - - union - { - __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ - - struct - { - __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, - * SC2. */ - uint32_t : 31; - } ATCCNTE_b; - }; - __IM uint32_t RESERVED12[4]; - - union - { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ - - struct - { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; - }; - __IM uint32_t RESERVED13[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED14[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - - union - { - __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ - - struct - { - __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ - } HCMDQP_b; - }; - - union - { - __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ - - struct - { - __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ - } HRSPQP_b; - }; - - union - { - __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ - - struct - { - __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ - } HTDTBP_b; - }; - - union - { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; - }; - - union - { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; - }; - __IM uint32_t RESERVED15[10]; - - union - { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ - - struct - { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; - }; - - union - { - __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ - uint32_t : 16; - } HQTHCTL_b; - }; - - union - { - __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold - * Control Register */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ - uint32_t : 5; - } HTBTHCTL_b; - }; - __IM uint32_t RESERVED16; - - union - { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ - - struct - { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 3; - __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ - uint32_t : 7; - } BST_b; - }; - - union - { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ - - struct - { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ - uint32_t : 7; - } BSTE_b; - }; - - union - { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ - - struct - { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ - uint32_t : 7; - } BIE_b; - }; - - union - { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ - - struct - { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 3; - __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ - uint32_t : 7; - } BSTFC_b; - }; - - union - { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; - }; - - union - { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; - }; - - union - { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; - }; - - union - { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; - }; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ - __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ - uint32_t : 1; - __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ - uint32_t : 22; - } HTST_b; - }; - - union - { - __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ - __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ - uint32_t : 22; - } HTSTE_b; - }; - - union - { - __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ - __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ - uint32_t : 22; - } HTIE_b; - }; - - union - { - __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ - __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ - uint32_t : 1; - __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ - uint32_t : 22; - } HTSTFC_b; - }; - - union - { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ - - struct - { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; - }; - - union - { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - - struct - { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ - uint32_t : 13; - } SVST_b; - }; - - union - { - __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ - - struct - { - __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; - }; - - union - { - __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ - - struct - { - __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ - } MRCCPT_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; - }; - __IM uint32_t RESERVED19; - - union - { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; - }; - __IM uint32_t RESERVED20; - - union - { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; - }; - __IM uint32_t RESERVED21; - - union - { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; - }; - __IM uint32_t RESERVED22; - - union - { - __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS4_b; - }; - __IM uint32_t RESERVED23; - - union - { - __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS5_b; - }; - __IM uint32_t RESERVED24; - - union - { - __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS6_b; - }; - __IM uint32_t RESERVED25; - - union - { - __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS7_b; - }; - __IM uint32_t RESERVED26[16]; - - union - { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - - struct - { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; - }; - __IM uint32_t RESERVED27[3]; - - union - { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; - }; - - union - { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; - }; - - union - { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; - }; - __IM uint32_t RESERVED28[5]; - - union - { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; - }; - - union - { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; - }; - - union - { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; - }; - - union - { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; - }; - - union - { - __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT4_b; - }; - - union - { - __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT5_b; - }; - - union - { - __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT6_b; - }; - - union - { - __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT7_b; - }; - __IM uint32_t RESERVED29[12]; - - union - { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - - struct - { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; - }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED30; - - union - { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; - }; - - union - { - __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD1_b; - }; - - union - { - __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD2_b; - }; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ - - struct - { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; - }; - - union - { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - - struct - { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; - }; - - union - { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ - - struct - { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; - }; - - union - { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ - - struct - { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; - }; - - union - { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - - struct - { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; - }; - - union - { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ - - struct - { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; - }; - - union - { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ - - struct - { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; - }; - - union - { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ - - struct - { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; - }; - - union - { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ - - struct - { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; - }; - - union - { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ - - struct - { - __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ - __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ - __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ - uint32_t : 5; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; - }; - - union - { - __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) - * Register */ - - struct - { - __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ - __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ - uint32_t : 4; - __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ - uint32_t : 24; - } CETSS_b; - }; - - union - { - __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ - - struct - { - __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ - __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ - __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ - uint32_t : 29; - } CGHDRCAP_b; - }; - - union - { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ - - struct - { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; - }; - __IM uint32_t RESERVED32[4]; - - union - { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; - }; - - union - { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; - }; - __IM uint32_t RESERVED33[9]; - - union - { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ - - struct - { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; - }; - - union - { - __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ - uint32_t : 16; - } HQSTLV_b; - }; - - union - { - __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ - uint32_t : 16; - } HDBSTLV_b; - }; - - union - { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - - struct - { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; - }; - - union - { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ - - struct - { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; - __IM uint32_t RESERVED34[3]; - - union - { - __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ - - struct - { - __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ - uint32_t : 16; - } SC1CPT_b; - }; - - union - { - __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ - - struct - { - __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ - uint32_t : 16; - } SC2CPT_b; - }; -} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OADPT_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[62]; - __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ - - struct - { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; - }; - - union - { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ - - struct - { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; - }; - - union - { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ - - struct - { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; - }; - - union - { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; - }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ - -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ - union - { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; - - struct - { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; - }; - - union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; - }; - - union - { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; - - struct - { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; - - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ - - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; - }; - - union - { - union - { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ - - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; - - struct - { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; - - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; - }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ - -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-MISC (R_PMISC) - */ - -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ - union - { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; - }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ - union - { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct - { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; - - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - - struct - { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; - - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; - - union - { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct - { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - - struct - { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; - - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ - - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; - }; - - union - { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct - { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct - { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ - __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using - * time error adjustment function inlow-consumption clock - * mode. */ - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; - }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; - - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; - - union - { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; - - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; - }; - __IM uint8_t RESERVED9; - - union - { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; - - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; - }; - __IM uint8_t RESERVED10; - - union - { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; - - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; - }; - __IM uint8_t RESERVED11; - - union - { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; - - union - { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; - }; - __IM uint8_t RESERVED12; - - union - { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; - - union - { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; - }; - - union - { - union - { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; - - union - { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ - - struct - { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; - }; - - union - { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - - struct - { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; - }; - - union - { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ - - struct - { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; - }; - __IM uint8_t RESERVED19; - - union - { - __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ - - struct - { - uint16_t : 5; - __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ - } RADJ2_b; - }; - __IM uint16_t RESERVED20[7]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ - -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ - union - { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; - - union - { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; - - union - { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; - - union - { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct - { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; - - union - { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF - * = 0, and MMR.MANEN = 1) */ - - struct - { - __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_MANC_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - union - { - __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ - __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ - uint16_t : 2; - __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ - uint16_t : 3; - } TDRHL_MAN_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - union - { - __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ - uint16_t : 2; - __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ - uint16_t : 3; - } RDRHL_MAN_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ - - struct - { - __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ - __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ - __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ - uint8_t : 1; - __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ - __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ - __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ - __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ - } MMR_b; - }; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; - }; - - union - { - __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ - __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ - uint8_t : 2; - } TMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ - - struct - { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; - }; - - union - { - __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ - __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ - uint8_t : 2; - } RMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ - - struct - { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; - }; - - union - { - __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ - - struct - { - __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ - __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ - uint8_t : 5; - } MESR_b; - }; - }; - - union - { - union - { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ - - struct - { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; - }; - - union - { - __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ - - struct - { - __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ - __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ - uint8_t : 5; - } MECR_b; - }; - }; - - union - { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ - - struct - { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; - }; - - union - { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ - - struct - { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; - - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct - { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ - - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ - - struct - { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ - - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ - - struct - { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ - - struct - { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; - - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct - { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ - __IM uint16_t RESERVED1[4]; - - union - { - __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ - - struct - { - __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ - uint8_t : 7; - } SCIMSKEN_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_SCI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ - -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ - union - { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ - - struct - { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ - - struct - { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; - }; - - union - { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - - struct - { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; - }; - - union - { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - - struct - { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; - }; - - union - { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - - struct - { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; - }; - - union - { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - - struct - { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; - }; - - union - { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - - struct - { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; - }; - - union - { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ - - struct - { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; - }; - - union - { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - - struct - { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; - }; - - union - { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ - - struct - { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; - }; - - union - { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - - struct - { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; - }; - - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ - - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; - - union - { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - - struct - { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; - }; - - union - { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; - }; - - union - { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ - - struct - { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; - }; - - union - { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; - }; - - union - { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct - { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; - }; - - union - { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct - { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; - }; - - union - { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ - - struct - { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; - }; - - union - { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - - struct - { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ - - struct - { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; - }; - - union - { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - - struct - { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; - }; - - union - { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ - - struct - { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - - struct - { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; - }; - __IM uint32_t RESERVED3[79]; - - union - { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ - - struct - { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; - }; - __IM uint32_t RESERVED4[3]; - - union - { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ - - struct - { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; - }; - __IM uint32_t RESERVED6[4]; - - union - { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ - - struct - { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; - }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ - - struct - { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; - }; - - union - { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - - struct - { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; - }; - - union - { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ - - struct - { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; - }; - - union - { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - - struct - { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ - }; - - union - { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ - - struct - { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; - }; - - union - { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - - struct - { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; - }; - - union - { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ - - struct - { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; - }; - - union - { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ - - struct - { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; - }; - - union - { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ - - struct - { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; - }; - - union - { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ - - struct - { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; - }; - - union - { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ - - struct - { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; - }; - - union - { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ - - struct - { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; - }; - - union - { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ - - struct - { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; - }; - - union - { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ - - struct - { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; - }; - - union - { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ - - struct - { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; - }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ - -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ - union - { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ - - struct - { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; - }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; - - union - { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ - - struct - { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; - }; - __IM uint8_t RESERVED3[179]; - - union - { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ - - struct - { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; - }; - - union - { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; - }; - - union - { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-08-12 Enable Register */ - - struct - { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-08-12 Enable */ - uint8_t : 7; - } ECC1STSEN_b; - }; - - union - { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; - }; - - union - { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; - }; - __IM uint8_t RESERVED4[11]; - - union - { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; - }; - __IM uint8_t RESERVED5[3]; - - union - { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ - - struct - { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; - }; - __IM uint8_t RESERVED6[3]; - - union - { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; - }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ -{ - union - { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ - - struct - { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; - }; - - union - { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ - - struct - { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ - - struct - { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 3; - __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ - uint32_t : 4; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; - }; - - union - { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ - - struct - { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; - }; - - union - { - union - { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - - struct - { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; - }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - - union - { - union - { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - - struct - { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; - }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - }; - - union - { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ - - struct - { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; - }; - - union - { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ - - struct - { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; - }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System Pins (R_SYSTEM) - */ - -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ - - struct - { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; - }; - - union - { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; - }; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ - - struct - { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ - - struct - { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; - }; - - union - { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ - - struct - { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; - }; - - union - { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ - - struct - { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ - - struct - { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; - }; - - union - { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ - - struct - { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; - }; - - union - { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; - }; - - union - { - __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register - * 2 */ - - struct - { - __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ - uint8_t : 1; - __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ - uint8_t : 2; - } HOCOCR2_b; - }; - - union - { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; - }; - - union - { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ - - struct - { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; - }; - - union - { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ - - struct - { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; - }; - - union - { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ - - struct - { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ - uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ - uint8_t : 1; - } OSCSF_b; - }; - __IM uint8_t RESERVED8; - - union - { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ - - struct - { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; - }; - - union - { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ - - struct - { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; - }; - - union - { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ - - struct - { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; - }; - - union - { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ - - struct - { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; - }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; - - union - { - __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ - - struct - { - __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ - uint16_t : 2; - } PLL2CCR_b; - }; - - union - { - __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ - - struct - { - __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ - uint8_t : 7; - } PLL2CR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ - - struct - { - __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock - * (valid only when LPOPTEN = 1) */ - __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ - __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W - * clock (valid only when LPOPT.LPOPTEN = 1) */ - uint8_t : 3; - __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ - } LPOPT_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ - - struct - { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ - - struct - { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; - }; - - union - { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ - - struct - { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; - }; - __IM uint32_t RESERVED15[3]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO - * trimming bits */ - } MOCOUTCR_b; - }; - - union - { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; - }; - __IM uint8_t RESERVED17; - __IM uint32_t RESERVED18[2]; - - union - { - __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ - - struct - { - __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ - uint8_t : 5; - } USBCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ - uint8_t : 5; - } OCTACKDIVCR_b; - }; - - union - { - __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ - uint8_t : 5; - } SCISPICKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ - - struct - { - __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ - uint8_t : 5; - } CANFDCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - - struct - { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; - }; - - union - { - __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ - - struct - { - __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ - uint8_t : 5; - } USB60CKDIVCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - - struct - { - __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ - uint8_t : 5; - } CECCKDIVCR_b; - }; - - union - { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ - - struct - { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ - - struct - { - __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ - uint8_t : 5; - } I3CCKDIVCR_b; - }; - __IM uint16_t RESERVED19; - - union - { - __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ - __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ - } USBCKCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ - - struct - { - __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ - uint8_t : 3; - __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ - __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ - } OCTACKCR_b; - }; - - union - { - __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ - - struct - { - __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ - uint8_t : 3; - __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ - __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ - } SCISPICKCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ - - struct - { - __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ - __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ - } CANFDCKCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - - struct - { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; - }; - - union - { - __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ - - struct - { - __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ - uint8_t : 2; - __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ - __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ - } USB60CKCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ - - struct - { - __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ - __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ - } CECCKCR_b; - }; - - union - { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ - - struct - { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ - - struct - { - __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ - uint8_t : 3; - __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ - __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ - } I3CCKCR_b; - }; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ - uint32_t : 29; - } SNZREQCR1_b; - }; - __IM uint32_t RESERVED22; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ - - struct - { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; - }; - __IM uint8_t RESERVED24; - - union - { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ - - struct - { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; - }; - - union - { - __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ - - struct - { - __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ - uint8_t : 7; - } SNZEDCR1_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ - - struct - { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; - }; - - union - { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ - - struct - { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; - }; - - union - { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ - - struct - { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; - }; - __IM uint8_t RESERVED27; - - union - { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ - - struct - { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; - }; - __IM uint8_t RESERVED28[2]; - - union - { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ - - struct - { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; - }; - __IM uint16_t RESERVED29[2]; - - union - { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ - - struct - { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; - }; - __IM uint8_t RESERVED30; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ - - struct - { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ - uint16_t : 1; - __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ - } RSTSR1_b; - }; - __IM uint16_t RESERVED32; - __IM uint32_t RESERVED33[3]; - - union - { - __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_ALT_b; - }; - - union - { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ - - struct - { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; - }; - __IM uint16_t RESERVED34; - __IM uint32_t RESERVED35[3]; - - union - { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; - }; - - union - { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; - }; - - union - { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; - }; - - union - { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; - }; - __IM uint32_t RESERVED36[183]; - - union - { - __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute - * Register */ - - struct - { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ - __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ - __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ - __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ - __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ - __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ - __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ - __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ - __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ - __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ - __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ - __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ - } CGFSAR_b; - }; - __IM uint32_t RESERVED37; - - union - { - __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - uint32_t : 1; - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 1; - __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - uint32_t : 3; - __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - uint32_t : 22; - } LPMSAR_b; - }; - - union - { - union - { - __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - uint32_t : 30; - } LVDSAR_b; - }; - - union - { - __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 29; - } RSTSAR_b; - }; - }; - - union - { - __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 13; - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - uint32_t : 8; - } BBFSAR_b; - }; - __IM uint32_t RESERVED38[3]; - - union - { - __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution - * Register */ - - struct - { - __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit - * 0 */ - __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit - * 1 */ - __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit - * 2 */ - __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit - * 3 */ - __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit - * 4 */ - __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit - * 5 */ - __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit - * 6 */ - __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit - * 7 */ - __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit - * 8 */ - __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit - * 9 */ - __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit - * 10 */ - __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit - * 11 */ - __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit - * 12 */ - __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit - * 13 */ - __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit - * 14 */ - __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit - * 15 */ - __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit - * 16 */ - __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit - * 17 */ - __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit - * 18 */ - __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit - * 19 */ - __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit - * 20 */ - uint32_t : 3; - __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit - * 24 */ - uint32_t : 1; - __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit - * 26 */ - __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit - * 27 */ - uint32_t : 4; - } DPFSAR_b; - }; - __IM uint32_t RESERVED39[6]; - __IM uint16_t RESERVED40; - - union - { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ - - struct - { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ - uint16_t : 3; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; - }; - - union - { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ - - struct - { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; - }; - - union - { - __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ - - struct - { - __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ - uint8_t : 2; - } DPSWCR_b; - }; - - union - { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ - - struct - { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; - }; - - union - { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ - - struct - { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; - }; - - union - { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ - - struct - { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; - }; - - union - { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 4; - } DPSIER3_b; - }; - - union - { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ - - struct - { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; - }; - - union - { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ - - struct - { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; - }; - - union - { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ - - struct - { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; - }; - - union - { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ - uint8_t : 4; - } DPSIFR3_b; - }; - - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; - }; - - union - { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; - }; - - union - { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ - - struct - { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; - }; - __IM uint8_t RESERVED41; - - union - { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ - - struct - { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; - }; - - union - { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ - - struct - { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; - }; - - union - { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ - - struct - { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; - }; - - union - { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ - - struct - { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; - }; - __IM uint8_t RESERVED42; - - union - { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; - }; - __IM uint16_t RESERVED43; - - union - { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ - - struct - { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; - }; - - union - { - union - { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; - }; - - union - { - __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 2; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ - } LVD1CMPCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - - struct - { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; - }; - - union - { - __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 4; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ - } LVD2CMPCR_b; - }; - }; - __IM uint8_t RESERVED44; - - union - { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; - }; - - union - { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; - }; - __IM uint8_t RESERVED45; - - union - { - __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select - * Register */ - - struct - { - __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ - uint8_t : 7; - } VBATTMNSELR_b; - }; - - union - { - __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ - - struct - { - __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ - uint8_t : 7; - } VBATTMONR_b; - }; - - union - { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ - - struct - { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; - }; - __IM uint32_t RESERVED46[8]; - - union - { - union - { - __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ - - struct - { - __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ - __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ - uint8_t : 2; - __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ - __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ - __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ - __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ - } DCDCCTL_b; - }; - - union - { - __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ - - struct - { - __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ - __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ - uint8_t : 6; - } LDOSCR_b; - }; - }; - - union - { - __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ - - struct - { - __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ - uint8_t : 6; - } VCCSEL_b; - }; - __IM uint16_t RESERVED47; - - union - { - __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ - - struct - { - __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ - uint8_t : 7; - } PL2LDOSCR_b; - }; - __IM uint8_t RESERVED48; - __IM uint16_t RESERVED49; - __IM uint32_t RESERVED50[14]; - - union - { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; - }; - - union - { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ - - struct - { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; - }; - - union - { - __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ - - struct - { - __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ - uint8_t : 6; - } SOMRG_b; - }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[3]; - - union - { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; - }; - __IM uint8_t RESERVED53; - - union - { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; - }; - __IM uint8_t RESERVED54; - __IM uint32_t RESERVED55[7]; - - union - { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; - }; - - union - { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ - - struct - { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; - }; - - union - { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ - - struct - { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; - }; - __IM uint8_t RESERVED56; - - union - { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ - - struct - { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; - }; - __IM uint8_t RESERVED57; - - union - { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ - - struct - { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; - }; - __IM uint8_t RESERVED58; - - union - { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; - }; - - union - { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ - - struct - { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; - }; - - union - { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ - - struct - { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; - }; - - union - { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ - - struct - { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; - }; - - union - { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ - - struct - { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; - }; - - union - { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ - - struct - { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; - }; - - union - { - __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ - uint8_t : 4; - } VBTBER_b; - }; - __IM uint8_t RESERVED59; - __IM uint16_t RESERVED60; - __IM uint32_t RESERVED61[15]; - - union - { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ - - struct - { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; - }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ - -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ - union - { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ - - struct - { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; - }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ - -typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ -{ - union - { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; - }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ - -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } DVCHGR_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ - uint16_t : 4; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - - union - { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - - struct - { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; - - union - { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ - - struct - { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ - - struct - { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; - - union - { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ - - struct - { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct - { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED23[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED25[5]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - __IM uint32_t RESERVED26[165]; - - union - { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ - - struct - { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union - { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ - - struct - { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ - -typedef struct /*!< (@ 0x40083400) R_WDT Structure */ -{ - union - { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ - - struct - { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; - }; - - union - { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; - }; - - union - { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/** - * @brief TrustZone Filter (R_TZF) - */ - -typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ -{ - union - { - __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFPT_b; - }; -} R_TZF_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief R_CACHE (R_CACHE) - */ - -typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ -{ - union - { - __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ - - struct - { - __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ - uint32_t : 31; - } CCACTL_b; - }; - - union - { - __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ - uint32_t : 31; - } CCAFCT_b; - }; - - union - { - __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ - uint32_t : 30; - } CCALCF_b; - }; - __IM uint32_t RESERVED[13]; - - union - { - __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ - - struct - { - __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ - uint32_t : 31; - } SCACTL_b; - }; - - union - { - __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ - uint32_t : 31; - } SCAFCT_b; - }; - - union - { - __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ - uint32_t : 30; - } SCALCF_b; - }; - __IM uint32_t RESERVED1[109]; - - union - { - __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection - * Register */ - - struct - { - __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint32_t : 31; - } CAPOAD_b; - }; - - union - { - __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ - - struct - { - __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ - __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ - uint32_t : 24; - } CAPRCR_b; - }; -} R_CACHE_Type; /*!< Size = 520 (0x208) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU System Security Control Unit (R_CPSCU) - */ - -typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ -{ - union - { - __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ - - struct - { - __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ - __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ - __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ - uint32_t : 29; - } CSAR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ - - struct - { - __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ - __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection - * 2 */ - __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ - uint32_t : 29; - } SRAMSAR_b; - }; - - union - { - __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ - - struct - { - __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ - uint32_t : 28; - } STBRAMSAR_b; - }; - __IM uint32_t RESERVED1[6]; - - union - { - __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ - uint32_t : 31; - } DTCSAR_b; - }; - - union - { - __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ - uint32_t : 31; - } DMACSAR_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ - - struct - { - __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ - uint32_t : 16; - } ICUSARA_b; - }; - - union - { - __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ - - struct - { - __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ - uint32_t : 31; - } ICUSARB_b; - }; - - union - { - __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ - - struct - { - __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ - uint32_t : 24; - } ICUSARC_b; - }; - - union - { - __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ - - struct - { - __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ - uint32_t : 31; - } ICUSARD_b; - }; - - union - { - __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ - - struct - { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 2; - __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ - } ICUSARE_b; - }; - - union - { - __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ - - struct - { - __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ - __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ - __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ - __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 3; - __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ - __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ - __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ - __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ - __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ - __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ - __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ - __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ - uint32_t : 17; - } ICUSARF_b; - }; - - union - { - __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ - - struct - { - __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ - __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ - __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ - __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ - __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ - __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ - __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ - uint32_t : 25; - } ICUSARM_b; - }; - __IM uint32_t RESERVED3[5]; - - union - { - __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ - } ICUSARG_b; - }; - - union - { - __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ - } ICUSARH_b; - }; - - union - { - __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ - } ICUSARI_b; - }; - __IM uint32_t RESERVED4[33]; - - union - { - __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ - - struct - { - __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ - uint32_t : 31; - } BUSSARA_b; - }; - - union - { - __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ - - struct - { - __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ - uint32_t : 31; - } BUSSARB_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ - - struct - { - __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ - uint32_t : 31; - } BUSSARC_b; - }; - - union - { - __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ - - struct - { - __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ - uint32_t : 31; - } BUSPARC_b; - }; - __IM uint32_t RESERVED6[6]; - - union - { - __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution - * Register A */ - - struct - { - __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ - uint32_t : 24; - } MMPUSARA_b; - }; - - union - { - __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution - * Register B */ - - struct - { - __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ - uint32_t : 31; - } MMPUSARB_b; - }; - __IM uint32_t RESERVED7[18]; - - union - { - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; - - union - { - __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ - - struct - { - __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ - uint32_t : 31; - } DEBUGSAR_b; - }; - }; - __IM uint32_t RESERVED8[7]; - - union - { - __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ - - struct - { - __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ - uint32_t : 24; - } DMACCHSAR_b; - }; - __IM uint32_t RESERVED9[3]; - - union - { - __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ - - struct - { - __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ - uint32_t : 31; - } CPUDSAR_b; - }; - __IM uint32_t RESERVED10[147]; - - union - { - __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register - * 0 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR0_b; - }; - - union - { - __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register - * 1 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR1_b; - }; - __IM uint32_t RESERVED11[126]; - - union - { - __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ - - struct - { - __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn - * and ELCSRn */ - uint32_t : 31; - } TEVTRCR_b; - }; -} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Consumer Electronics Control (R_CEC) - */ - -typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ -{ - union - { - __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ - - struct - { - __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ - __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device - * 1) */ - __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device - * 2) */ - __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ - __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ - __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ - __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ - __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ - __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ - __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device - * 3) */ - __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ - __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device - * 3) */ - __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ - __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ - __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ - uint16_t : 1; - } CADR_b; - }; - - union - { - __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ - - struct - { - __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ - __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing - * Select */ - __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ - __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ - __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ - __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ - } CECCTL1_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ - - struct - { - __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ - uint16_t : 7; - } STATB_b; - }; - - union - { - __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ - uint16_t : 7; - } STATL_b; - }; - - union - { - __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ - uint16_t : 7; - } LGC0L_b; - }; - - union - { - __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ - uint16_t : 7; - } LGC1L_b; - }; - - union - { - __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ - - struct - { - __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ - uint16_t : 7; - } DATB_b; - }; - - union - { - __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ - - struct - { - __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ - uint16_t : 7; - } NOMT_b; - }; - - union - { - __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ - uint16_t : 7; - } STATLL_b; - }; - - union - { - __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATLH_b; - }; - - union - { - __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ - uint16_t : 7; - } STATBL_b; - }; - - union - { - __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATBH_b; - }; - - union - { - __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LL_b; - }; - - union - { - __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LH_b; - }; - - union - { - __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ - uint16_t : 7; - } LGC1LL_b; - }; - - union - { - __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ - uint16_t : 7; - } LGC1LH_b; - }; - - union - { - __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ - uint16_t : 7; - } DATBL_b; - }; - - union - { - __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ - uint16_t : 7; - } DATBH_b; - }; - - union - { - __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ - - struct - { - __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ - uint16_t : 7; - } NOMP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ - __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ - uint8_t : 1; - __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ - } CECEXMD_b; - }; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ - - struct - { - __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ - __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ - uint8_t : 6; - } CECEXMON_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[10]; - __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ - __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ - - union - { - __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ - - struct - { - __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ - __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ - __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ - __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ - __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ - __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ - __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ - uint8_t : 1; - } CECES_b; - }; - - union - { - __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ - - struct - { - __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ - __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ - __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ - __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ - __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ - uint8_t : 2; - __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ - } CECS_b; - }; - - union - { - __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ - - struct - { - __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ - __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ - __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ - __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ - __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ - __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ - __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ - uint8_t : 1; - } CECFC_b; - }; - - union - { - __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ - - struct - { - __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ - __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ - __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ - __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ - __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ - __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ - } CECCTL0_b; - }; -} R_CEC_Type; /*!< Size = 70 (0x46) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Octa Serial Peripheral Interface (R_OSPI) - */ - -typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ -{ - union - { - __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ - - struct - { - __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ - __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ - uint32_t : 16; - } DCR_b; - }; - - union - { - __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ - - struct - { - __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ - __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ - __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ - __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ - } DAR_b; - }; - - union - { - __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ - - struct - { - __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ - __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ - uint32_t : 3; - __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ - __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ - __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ - __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ - __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ - __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ - __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ - uint32_t : 2; - } DCSR_b; - }; - - union - { - __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ - - struct - { - __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ - __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ - } DSR_b[2]; - }; - - union - { - __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ - - struct - { - __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ - __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ - __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ - __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ - __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ - uint32_t : 4; - } MDTR_b; - }; - - union - { - __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ - - struct - { - __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ - } ACTR_b; - }; - - union - { - __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ - - struct - { - __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ - } ACAR_b[2]; - }; - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ - __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ - __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ - __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ - __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DRCSTR_b; - }; - - union - { - __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ - __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ - __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ - __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ - __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DWCSTR_b; - }; - - union - { - __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ - __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ - __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ - uint32_t : 16; - } DCSTR_b; - }; - - union - { - __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ - - struct - { - __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ - __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ - __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ - __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ - uint32_t : 4; - __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device - * 0 */ - __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device - * 1 */ - __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ - uint32_t : 17; - __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ - } CDSR_b; - }; - - union - { - __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ - - struct - { - __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ - __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ - __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ - __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ - } MDLR_b; - }; - - union - { - __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ - - struct - { - __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ - __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ - __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ - __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ - } MRWCR_b[2]; - }; - - union - { - __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ - - struct - { - __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ - __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ - __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ - __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ - __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ - __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ - __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ - uint32_t : 1; - __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ - __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ - __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ - __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ - __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ - __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ - __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ - uint32_t : 1; - } MRWCSR_b; - }; - - union - { - __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ - - struct - { - __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ - __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ - uint32_t : 16; - } ESR_b; - }; - - union - { - __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ - - struct - { - __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ - } CWNDR_b; - }; - - union - { - __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ - - struct - { - __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ - __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ - __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ - __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ - } CWDR_b; - }; - - union - { - __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ - - struct - { - __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ - __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ - __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ - __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ - } CRR_b; - }; - - union - { - __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ - - struct - { - __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ - __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ - uint32_t : 26; - } ACSR_b; - }; - __IM uint32_t RESERVED1[5]; - - union - { - __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ - - struct - { - __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are - * Low in single continuous write of OctaRAM. */ - uint32_t : 7; - __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 - * are Low in single continuous read of OctaRAM. */ - uint32_t : 7; - } DCSMXR_b; - }; - - union - { - __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating - * size Register */ - - struct - { - __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single - * continuous write of device 0. */ - uint32_t : 5; - __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single - * continuous write of device 1. */ - uint32_t : 5; - } DWSCTSR_b; - }; -} R_OSPI_Type; /*!< Size = 132 (0x84) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 High-Speed Module (R_USB_HS0) - */ - -typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ - uint16_t : 7; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller - * Operation */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit - * when switching from device B to device A in OTGmode. If - * the HNPBTOA bit is 1, the internal function controlremains - * in the Suspend state until the HNP processing endseven - * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } CFIFO_b; - }; - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } D0FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write - * transmit data to the FIFO buffer by accessing these bits. */ - } D1FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-08-12 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be - * set only in the initial setting (before communications).The - * setting cannot be changed once communication starts. */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency - * can be improved by setting this bit to 1 if no low-speed - * device is connected directly or via FS-HUB to the USB port. */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ - - struct - { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected - * : read-only Host controller selected : read-write */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected - * : read-only Host controller selected : read-write */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected - * : read-only Host controller selected : read-write */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected - * : read-only Host controller selected : read-write */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected - * : read-only Host controller selected : read-write */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * destination function device for control transfer when the - * host controller function is selected. */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - - union - { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ - - struct - { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number - * of the selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - uint16_t : 1; - } PIPEBUF_b; - }; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the selected pipe.A size - * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * peripheral device when the host controller function is - * selected. */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the - * transfer interval timing for the selected pipe as n-th - * power of 2 of the frame timing. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for - * the next transaction of the relevant pipe. */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe - * is being used for the USB bus */ - __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is set for DATA1 */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is cleared to DATA0 */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto - * buffer clear mode for the relevant pipe */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto - * response mode for the relevant pipe. */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO - * buffer status for the relevant pipe in the transmitting - * direction. */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status - * for the relevant pipe. */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED14[11]; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED15[7]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED16[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED17; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ - - struct - { - __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset - * value for adjusting the terminating resistance. */ - uint16_t : 1; - } PHYTRIM1_b; - }; - - union - { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ - - struct - { - __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ - uint16_t : 1; - } PHYTRIM2_b; - }; - __IM uint32_t RESERVED19[3]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; -} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGTX0) - */ - -typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ -{ - union - { - __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ - __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ - }; -} R_AGTX0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CANFD ECC (R_ECCMB0) - */ - -typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ -{ - union - { - __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ - - struct - { - __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ - __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ - __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ - __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ - __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ - __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ - __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ - uint32_t : 2; - __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag - * Clear */ - __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ - __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ - uint32_t : 2; - __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ - __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ - __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ - uint32_t : 14; - } EC710CTL_b; - }; - - union - { - __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ - uint16_t : 5; - __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ - uint16_t : 6; - __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ - } EC710TMC_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ - - struct - { - __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ - } EC710TED_b; - }; - - union - { - __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ - - struct - { - __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ - uint32_t : 22; - } EC710EAD0_b; - }; -} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Flash (R_FLAD) - */ - -typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ -{ - __IM uint8_t RESERVED[64]; - - union - { - __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ - - struct - { - __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ - } FCKMHZ_b; - }; -} R_FLAD_Type; /*!< Size = 65 (0x41) */ - -/** @} */ /* End of group Device_Peripheral_peripherals */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ADC0_BASE 0x40170000UL - #define R_ADC1_BASE 0x40170200UL - #define R_PSCU_BASE 0x400E0000UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40083600UL - #define R_CANFD_BASE 0x400B0000UL - #define R_CRC_BASE 0x40108000UL - #define R_CTSU_BASE 0x400D0000UL - #define R_DAC_BASE 0x40171000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40109000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40082000UL - #define R_ETHERC0_BASE 0x40114100UL - #define R_ETHERC_EDMAC_BASE 0x40114000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GPT0_BASE 0x40169000UL - #define R_GPT1_BASE 0x40169100UL - #define R_GPT2_BASE 0x40169200UL - #define R_GPT3_BASE 0x40169300UL - #define R_GPT4_BASE 0x40169400UL - #define R_GPT5_BASE 0x40169500UL - #define R_GPT6_BASE 0x40169600UL - #define R_GPT7_BASE 0x40169700UL - #define R_GPT8_BASE 0x40169800UL - #define R_GPT9_BASE 0x40169900UL - #define R_GPT10_BASE 0x40169A00UL - #define R_GPT11_BASE 0x40169B00UL - #define R_GPT12_BASE 0x40169C00UL - #define R_GPT13_BASE 0x40169D00UL - #define R_GPT_OPS_BASE 0x40169A00UL - #define R_GPT_POEG0_BASE 0x4008A000UL - #define R_GPT_POEG1_BASE 0x4008A100UL - #define R_GPT_POEG2_BASE 0x4008A200UL - #define R_GPT_POEG3_BASE 0x4008A300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x4009F000UL - #define R_IIC1_BASE 0x4009F100UL - #define R_IIC2_BASE 0x4009F200UL - #define R_IWDT_BASE 0x40083200UL - #define R_I3C0_BASE 0x4011F000UL - #define R_I3C1_BASE 0x4011F400UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40084000UL - #define R_PORT0_BASE 0x40080000UL - #define R_PORT1_BASE 0x40080020UL - #define R_PORT2_BASE 0x40080040UL - #define R_PORT3_BASE 0x40080060UL - #define R_PORT4_BASE 0x40080080UL - #define R_PORT5_BASE 0x400800A0UL - #define R_PORT6_BASE 0x400800C0UL - #define R_PORT7_BASE 0x400800E0UL - #define R_PORT8_BASE 0x40080100UL - #define R_PORT9_BASE 0x40080120UL - #define R_PORT10_BASE 0x40080140UL - #define R_PORT11_BASE 0x40080160UL - #define R_PORT12_BASE 0x40080180UL - #define R_PORT13_BASE 0x400801A0UL - #define R_PORT14_BASE 0x400801C0UL - #define R_PFS_BASE 0x40080800UL - #define R_PMISC_BASE 0x40080D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40083000UL - #define R_SCI0_BASE 0x40118000UL - #define R_SCI1_BASE 0x40118100UL - #define R_SCI2_BASE 0x40118200UL - #define R_SCI3_BASE 0x40118300UL - #define R_SCI4_BASE 0x40118400UL - #define R_SCI5_BASE 0x40118500UL - #define R_SCI6_BASE 0x40118600UL - #define R_SCI7_BASE 0x40118700UL - #define R_SCI8_BASE 0x40118800UL - #define R_SCI9_BASE 0x40118900UL - #define R_SDHI0_BASE 0x40092000UL - #define R_SDHI1_BASE 0x40092400UL - #define R_SPI0_BASE 0x4011A000UL - #define R_SPI1_BASE 0x4011A100UL - #define R_SPI2_BASE 0x40072200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SSI0_BASE 0x4009D000UL - #define R_SSI1_BASE 0x4009D100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x400F3000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_WDT_BASE 0x40083400UL - #define R_TZF_BASE 0x40000E00UL - #define R_CACHE_BASE 0x40007000UL - #define R_CPSCU_BASE 0x40008000UL - #define R_CEC_BASE 0x400AC000UL - #define R_OSPI_BASE 0x400A6000UL - #define R_USB_HS0_BASE 0x40111000UL - #define R_AGTX0_BASE 0x400E8000UL - #define R_AGTX1_BASE 0x400E8100UL - #define R_AGTX2_BASE 0x400E8200UL - #define R_AGTX3_BASE 0x400E8300UL - #define R_AGTX4_BASE 0x400E8400UL - #define R_AGTX5_BASE 0x400E8500UL - #define R_AGTX6_BASE 0x400E8600UL - #define R_AGTX7_BASE 0x400E8700UL - #define R_AGTX8_BASE 0x400E8800UL - #define R_AGTX9_BASE 0x400E8900UL - #define R_ECCMB0_BASE 0x4036F200UL - #define R_ECCMB1_BASE 0x4036F300UL - #define R_FLAD_BASE 0x407FC000UL - #define R_WDT1_BASE 0x40044300UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) - #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) - #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) - #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - #define R_TZF ((R_TZF_Type *) R_TZF_BASE) - #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) - #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) - #define R_CEC ((R_CEC_Type *) R_CEC_BASE) - #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) - #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) - #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) - #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) - #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) - #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) - #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) - #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) - #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) - #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) - #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) - #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) - #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) - #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - -/* ========================================= End of section using anonymous unions ========================================= */ - #if defined(__CC_ARM) - #pragma pop - #elif defined(__ICCARM__) - -/* leave anonymous unions enabled */ - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning restore - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #endif - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_clusters - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ SDRAM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SDCCR ========================================================= */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCMOD ========================================================= */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDAMOD ========================================================= */ - #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ - #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDSELF ========================================================= */ - #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ - #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDRFCR ========================================================= */ - #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ - #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ -/* ======================================================== SDRFEN ========================================================= */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ -/* ========================================================= SDICR ========================================================= */ - #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ - #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SDIR ========================================================== */ - #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ - #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ - #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ - #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ -/* ========================================================= SDADR ========================================================= */ - #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ - #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ -/* ========================================================= SDTR ========================================================== */ - #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ - #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ - #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ - #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ - #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ - #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ -/* ========================================================= SDMOD ========================================================= */ - #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ - #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ -/* ========================================================= SDSR ========================================================== */ - #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ - #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ - #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ - #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= IRQEN ========================================================= */ - #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ - #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ DMACDTCERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FLBI ========================================================== */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== MRE0BI ========================================================= */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S2BI ========================================================== */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S3BI ========================================================== */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== STBYSBI ======================================================== */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= ECBI ========================================================== */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= EOBI ========================================================== */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI0BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI1BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PBBI ========================================================== */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PABI ========================================================== */ - #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PIBI ========================================================== */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PSBI ========================================================== */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU0SAHBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT1 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FHBI ========================================================== */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ======================================================== MRC0BI ========================================================= */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ BMSAERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ - #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ OAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BUSOAD ========================================================= */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSOADPT ======================================================== */ - #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== MSAOAD ========================================================= */ - #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= MSAPT ========================================================= */ - #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ MBWERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ - #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ - #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ - #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ ELSEGR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== BY =========================================================== */ - #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ - #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ - #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ - #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ ELSR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== HA =========================================================== */ - #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ - #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ SAR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== L =========================================================== */ - #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ - #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ -/* =========================================================== U =========================================================== */ - #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ - #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ - #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ REGION ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AC =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ -/* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ GROUP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== EN =========================================================== */ - #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= ENPT ========================================================== */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== RPT ========================================================== */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== RPT_SEC ======================================================== */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================== CTL ========================================================== */ - #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ - #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== SA =========================================================== */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== EA =========================================================== */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ PIN ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= PmnPFS_BY ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ======================================================= PmnPFS_HA ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ -/* ======================================================== PmnPFS ========================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PORT ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PMSAR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PMSAR ========================================================= */ - -/* =========================================================================================================================== */ -/* ================ RTCCR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RTCCR ========================================================= */ - #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ - #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ - #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ - #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RSEC ========================================================== */ - #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ - #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMIN ========================================================== */ - #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ - #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ -/* ========================================================== RHR ========================================================== */ - #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ - #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RDAY ========================================================== */ - #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ - #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMON ========================================================== */ - #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= AGTCR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTMR1 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ -/* ======================================================== AGTMR2 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ -/* ===================================================== AGTIOSEL_ALT ====================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ -/* ======================================================== AGTIOC ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTISR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTCMSR ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ -/* ======================================================= AGTIOSEL ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ AGT16 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ AGT32 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ - -/** @} */ /* End of group PosMask_clusters */ - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ADCSR ========================================================= */ - #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ - #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ - #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ - #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ - #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ - #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ - #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ - #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ - #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ - #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSA ========================================================= */ - #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ - #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADS ========================================================= */ - #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ - #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADC ========================================================= */ - #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ - #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ - #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ -/* ========================================================= ADCER ========================================================= */ - #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ - #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ - #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ - #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ - #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ - #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ - #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ - #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ - #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSTRGR ======================================================== */ - #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ - #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ - #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ - #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ -/* ======================================================== ADEXICR ======================================================== */ - #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ - #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ - #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ - #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ - #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ - #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ - #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ - #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ - #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSB ========================================================= */ - #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ - #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADDBLDR ======================================================== */ - #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ - #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADTSDR ========================================================= */ - #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ - #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADOCDR ========================================================= */ - #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ - #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADRD_RIGHT ======================================================= */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ -/* ======================================================= ADRD_LEFT ======================================================= */ - #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ - #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ========================================================= ADDR ========================================================== */ - #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ - #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADSHCR ========================================================= */ - #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ - #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ - #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ - #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ - #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ -/* ======================================================== ADDISCR ======================================================== */ - #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ - #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ - #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADSHMSR ======================================================== */ - #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ - #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADACSR ========================================================= */ - #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ - #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ -/* ======================================================== ADGSPCR ======================================================== */ - #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ - #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ - #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ - #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ -/* ========================================================= ADICR ========================================================= */ - #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ - #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ -/* ======================================================= ADDBLDRA ======================================================== */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADDBLDRB ======================================================== */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADHVREFCNT ======================================================= */ - #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= ADWINMON ======================================================== */ - #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ - #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ - #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ - #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPCR ======================================================== */ - #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ - #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ - #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ - #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ - #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ - #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ - #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCMPANSER ======================================================= */ - #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ - #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPLER ======================================================== */ - #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ - #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPANSR ======================================================= */ - #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ - #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPLR ======================================================== */ - #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ - #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPDR0 ======================================================== */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPDR1 ======================================================== */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADCMPSR ======================================================== */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPSER ======================================================== */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPBNSR ======================================================= */ - #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ - #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ -/* ======================================================= ADWINLLB ======================================================== */ - #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ - #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADWINULB ======================================================== */ - #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ - #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPBSR ======================================================== */ - #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ - #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSSTRL ======================================================== */ - #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRT ======================================================== */ - #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRO ======================================================== */ - #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTR ========================================================= */ - #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADPGACR ======================================================== */ - #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ - #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ - #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ - #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ - #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ - #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ - #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ - #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ - #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ - #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ - #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ - #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ - #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ - #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ - #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ - #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ - #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADRD ========================================================== */ - #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ -/* ========================================================= ADRST ========================================================= */ - #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ====================================================== VREFAMPCNT ======================================================= */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ - #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCALEXE ======================================================== */ - #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ - #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ - #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANIM ========================================================= */ - #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ - #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGAGS0 ======================================================== */ - #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ - #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= ADPGADCR0 ======================================================= */ - #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ - #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ - #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ - #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ - #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ - #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ - #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ - #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ - #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADREF ========================================================= */ - #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ - #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ - #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ -/* ======================================================== ADEXREF ======================================================== */ - #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ - #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADAMPOFF ======================================================== */ - #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ - #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ -/* ======================================================== ADTSTPR ======================================================== */ - #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ - #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ - #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================= ADDDACER ======================================================== */ - #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ - #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ - #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ - #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADEXTSTR ======================================================== */ - #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ - #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ - #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ - #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ -/* ======================================================== ADTSTRA ======================================================== */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ - #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ - #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADTSTRB ======================================================== */ - #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ - #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ -/* ======================================================== ADTSTRC ======================================================== */ - #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ - #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ - #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ADTSTRD ======================================================== */ - #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ - #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR0 ======================================================= */ - #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ - #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR1 ======================================================= */ - #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ - #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR2 ======================================================= */ - #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ - #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSWCR ========================================================= */ - #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ - #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ - #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ -/* ======================================================== ADGSCS ========================================================= */ - #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ - #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ - #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ -/* ========================================================= ADSER ========================================================= */ - #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ - #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ -/* ======================================================== ADBUF0 ========================================================= */ - #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF1 ========================================================= */ - #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF2 ========================================================= */ - #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF3 ========================================================= */ - #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF4 ========================================================= */ - #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF5 ========================================================= */ - #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF6 ========================================================= */ - #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF7 ========================================================= */ - #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF8 ========================================================= */ - #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF9 ========================================================= */ - #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF10 ======================================================== */ - #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF11 ======================================================== */ - #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF12 ======================================================== */ - #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF13 ======================================================== */ - #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF14 ======================================================== */ - #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF15 ======================================================== */ - #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUFEN ======================================================== */ - #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ - #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADBUFPTR ======================================================== */ - #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ - #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ - #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS0 ======================================================= */ - #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS1 ======================================================= */ - #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADREFMON ======================================================== */ - #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ - #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ - #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ - #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ - #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ - #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ - #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ - #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ - #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ - #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ - #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ - #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ - #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ - #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ - #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ - #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ - #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ - #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ - #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ - #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ - #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ - #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ - #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ - #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ - #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ - #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ - #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ - #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ - #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ -/* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ - #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ - #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ - #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ -/* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ -/* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ -/* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ - #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ -/* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ - #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSMABT ======================================================== */ - #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSDIVBYP ======================================================= */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSTHRPUT ======================================================= */ - #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ - #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CACR0 ========================================================= */ - #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ - #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR1 ========================================================= */ - #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ - #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ - #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ - #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR2 ========================================================= */ - #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ - #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ - #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ - #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ - #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ -/* ========================================================= CAICR ========================================================= */ - #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ - #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ - #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ - #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ - #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ - #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ - #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ -/* ========================================================= CASTR ========================================================= */ - #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ - #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ - #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ - #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ -/* ======================================================== CAULVR ========================================================= */ - #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ - #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CALLVR ========================================================= */ - #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ - #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CACNTBR ======================================================== */ - #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ - #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CRCCR0 ========================================================= */ - #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ - #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ - #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ - #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ -/* ======================================================== CRCCR1 ========================================================= */ - #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ - #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ - #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CRCDIR ========================================================= */ - #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ - #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDIR_BY ======================================================= */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCDOR ========================================================= */ - #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ - #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDOR_HA ======================================================= */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ -/* ======================================================= CRCDOR_BY ======================================================= */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCSAR ========================================================= */ - #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ - #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTSUCR0 ======================================================== */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ -/* ======================================================== CTSUCR1 ======================================================== */ - #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ - #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ - #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUSDPRS ======================================================= */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSST ======================================================== */ - #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ - #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ -/* ======================================================= CTSUMCH0 ======================================================== */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUMCH1 ======================================================== */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUCHAC ======================================================== */ - #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUCHTRC ======================================================= */ - #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUDCLKC ======================================================= */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== CTSUST ========================================================= */ - #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ - #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ - #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ - #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ - #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ - #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ -/* ======================================================== CTSUSSC ======================================================== */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSO0 ======================================================== */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ - #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ - #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ -/* ======================================================== CTSUSO1 ======================================================== */ - #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ - #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ -/* ======================================================== CTSUSC ========================================================= */ - #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ - #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ -/* ======================================================== CTSURC ========================================================= */ - #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ - #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ -/* ======================================================= CTSUERRS ======================================================== */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUTRMR ======================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DACR ========================================================== */ - #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ - #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ - #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ - #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ -/* ========================================================= DADR ========================================================== */ - #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ - #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DADPR ========================================================= */ - #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ - #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADSCR ======================================================== */ - #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ - #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ -/* ======================================================= DAVREFCR ======================================================== */ - #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ - #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ -/* ========================================================= DAPC ========================================================== */ - #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ - #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== DAAMPCR ======================================================== */ - #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ - #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DAASWCR ======================================================== */ - #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ - #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ - #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ - #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== DBGSTR ========================================================= */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ -/* ======================================================= DBGSTOPCR ======================================================= */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ -/* ======================================================= FSBLSTAT ======================================================== */ - #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ - #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ -/* ======================================================== DMECHR ========================================================= */ - #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ - #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ - #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ - #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ - #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ -/* ========================================================= DELSR ========================================================= */ - #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMSAR ========================================================= */ - #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ - #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMDAR ========================================================= */ - #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ - #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCRA ========================================================= */ - #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ - #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ - #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ - #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMCRB ========================================================= */ - #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ - #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ - #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMTMD ========================================================= */ - #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ - #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ - #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ - #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ - #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ - #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ -/* ========================================================= DMINT ========================================================= */ - #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ - #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ - #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ - #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ - #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ - #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMAMD ========================================================= */ - #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ - #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ - #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ - #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ - #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ - #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ - #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ -/* ========================================================= DMOFR ========================================================= */ - #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ - #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCNT ========================================================= */ - #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ - #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMREQ ========================================================= */ - #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ - #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ - #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSTS ========================================================= */ - #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ - #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ - #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ - #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSRR ========================================================= */ -/* ========================================================= DMDRR ========================================================= */ -/* ========================================================= DMSBS ========================================================= */ - #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ - #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ - #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMDBS ========================================================= */ - #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ - #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ - #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMBWR ========================================================= */ - #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ - #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DOCR ========================================================== */ - #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ - #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ - #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ - #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ - #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ -/* ========================================================= DODIR ========================================================= */ - #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ - #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DODSR ========================================================= */ - #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ - #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= DTCADMOD ======================================================== */ - #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ - #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ -/* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ -/* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ====================================================== DTCVBR_SEC ======================================================= */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DTCDISP ======================================================== */ - #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ - #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCIBR ========================================================= */ - #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ - #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ -/* ========================================================= DTCOR ========================================================= */ - #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ - #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSQE ========================================================= */ - #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ - #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARA ======================================================== */ - #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ - #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ - #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ - #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARB ======================================================== */ - #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ - #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ - #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ - #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ - #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ - #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ - #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ - #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ - #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ - #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ - #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ - #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ - #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ - #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ - #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ - #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ - #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARC ======================================================== */ - #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ - #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ - #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ - #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ECMR ========================================================== */ - #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ - #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ - #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ - #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ - #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ - #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ - #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ - #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ - #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ - #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ - #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ - #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ - #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ -/* ========================================================= RFLR ========================================================== */ - #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ - #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ - #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ - #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ - #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ - #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ - #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ -/* ======================================================== ECSIPR ========================================================= */ - #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ - #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ - #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ - #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ -/* ========================================================== PIR ========================================================== */ - #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ - #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ - #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ - #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ - #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ -/* ========================================================== PSR ========================================================== */ - #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ - #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ -/* ========================================================= RDMLR ========================================================= */ - #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ - #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ -/* ========================================================= IPGR ========================================================== */ - #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ - #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ -/* ========================================================== APR ========================================================== */ - #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ - #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ -/* ========================================================== MPR ========================================================== */ - #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ - #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFCF ========================================================== */ - #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ - #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ -/* ======================================================== TPAUSER ======================================================== */ - #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ - #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ -/* ======================================================= TPAUSECR ======================================================== */ -/* ========================================================= BCFRR ========================================================= */ - #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ - #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ -/* ========================================================= MAHR ========================================================== */ - #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ - #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MALR ========================================================== */ - #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ - #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ -/* ========================================================= TROCR ========================================================= */ - #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ - #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CDCR ========================================================== */ -/* ========================================================= LCCR ========================================================== */ - #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ - #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CNDCR ========================================================= */ - #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ - #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CEFCR ========================================================= */ - #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ - #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= FRECR ========================================================= */ - #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ - #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TSFRCR ========================================================= */ - #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ - #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TLFRCR ========================================================= */ - #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ - #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RFCR ========================================================== */ - #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ - #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MAFCR ========================================================= */ - #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ - #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= EDMR ========================================================== */ - #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ - #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ - #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDTRR ========================================================= */ - #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ - #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDRRR ========================================================= */ - #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ - #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ -/* ========================================================= TDLAR ========================================================= */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDLAR ========================================================= */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= EESR ========================================================== */ - #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ - #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ - #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ - #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ - #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ - #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ - #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ - #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ - #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ - #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ - #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ - #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ - #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ - #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ - #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ - #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ - #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ -/* ======================================================== EESIPR ========================================================= */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ -/* ======================================================== TRSCER ========================================================= */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ -/* ========================================================= RMFCR ========================================================= */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= TFTR ========================================================== */ - #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ - #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ -/* ========================================================== FDR ========================================================== */ - #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ - #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ - #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ - #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ -/* ========================================================= RMCR ========================================================== */ - #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ - #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ -/* ========================================================= TFUCR ========================================================= */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFOCR ========================================================= */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ -/* ========================================================= IOSR ========================================================== */ - #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ - #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ -/* ========================================================= FCFTR ========================================================= */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ -/* ======================================================== RPADIR ========================================================= */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ -/* ========================================================= TRIMD ========================================================= */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ -/* ========================================================= RBWAR ========================================================= */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDFAR ========================================================= */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TBRAR ========================================================= */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TDFAR ========================================================= */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/* ====================================================== FACI_CMD16 ======================================================= */ -/* ======================================================= FACI_CMD8 ======================================================= */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ -/* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FMEPROT ======================================================== */ - #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ - #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT0 ======================================================== */ - #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ - #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT1 ======================================================== */ - #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ - #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ - #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ - #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ - #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ -/* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ -/* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ -/* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ -/* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ -/* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ -/* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== FBCADDR ======================================================== */ - #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ - #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ -/* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ -/* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ -/* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ -/* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ -/* ======================================================= FCNTSELR ======================================================== */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ -/* ====================================================== FCNTDATAR0 ======================================================= */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FCNTDATAR1 ======================================================= */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ -/* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ -/* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ -/* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ - #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ - #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ - #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ - #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= GTWP ========================================================== */ - #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ - #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ - #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ - #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ - #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTR ========================================================= */ - #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ - #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTP ========================================================= */ - #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ - #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCLR ========================================================= */ - #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ - #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSSR ========================================================= */ - #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ - #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ - #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ - #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ - #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ - #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ - #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ - #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ - #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ - #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ - #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ - #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ - #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTPSR ========================================================= */ - #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ - #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ - #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ - #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ - #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ - #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ - #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ - #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ - #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ - #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ - #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ - #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ - #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCSR ========================================================= */ - #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ - #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ - #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ - #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ - #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ - #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ - #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ - #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ - #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ - #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ - #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ - #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ - #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ - #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ - #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTUPSR ========================================================= */ - #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ - #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ - #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ - #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ - #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ - #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ - #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ - #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ - #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ - #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ - #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ - #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ - #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTDNSR ========================================================= */ - #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ - #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ - #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ - #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ - #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ - #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ - #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ - #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ - #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ - #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ - #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ - #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ - #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICASR ======================================================== */ - #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ - #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ - #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ - #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ - #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ - #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ - #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ - #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ - #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ - #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ - #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ - #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ - #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICBSR ======================================================== */ - #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ - #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ - #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ - #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ - #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ - #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ - #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ - #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ - #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ - #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ - #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ - #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ - #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ - #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ - #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ - #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ - #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ - #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ - #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ - #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ - #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ - #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ - #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ -/* ======================================================= GTUDDTYC ======================================================== */ - #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ - #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ - #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ - #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ - #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ - #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ - #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ - #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ -/* ========================================================= GTIOR ========================================================= */ - #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ - #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ - #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ - #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ - #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ - #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ - #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ - #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ - #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ - #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ - #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ - #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ - #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ - #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ - #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ - #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ - #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ - #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ - #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTINTAD ======================================================== */ - #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ - #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ - #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ - #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ - #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ - #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ - #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ - #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ - #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ - #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ - #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ - #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTST ========================================================== */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ - #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ - #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ - #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ - #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ - #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ - #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ - #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ - #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ - #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ - #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ - #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ - #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ - #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ - #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ - #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ - #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ - #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ - #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTBER ========================================================= */ - #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ - #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ - #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ - #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ - #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ - #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ - #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ - #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ - #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ - #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ - #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ - #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ - #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ - #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ -/* ========================================================= GTITC ========================================================= */ - #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ - #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ - #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ - #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ - #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ - #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ - #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ - #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ - #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ - #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ - #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCNT ========================================================= */ - #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ - #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTCCR ========================================================= */ - #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ - #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPR ========================================================== */ - #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ - #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPBR ========================================================= */ - #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ - #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTPDBR ========================================================= */ - #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ - #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRA ======================================================== */ - #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ - #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRB ======================================================== */ - #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ - #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRA ======================================================== */ - #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ - #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRB ======================================================== */ - #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ - #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRA ======================================================= */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRB ======================================================= */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTDTCR ========================================================= */ - #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ - #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ - #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ - #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ - #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ -/* ========================================================= GTDVU ========================================================= */ - #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDVD ========================================================= */ - #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ - #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBU ========================================================= */ - #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBD ========================================================= */ - #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ - #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTSOS ========================================================= */ - #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ - #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ -/* ======================================================== GTSOTR ========================================================= */ - #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ - #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTADSMR ======================================================== */ - #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ - #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ - #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ - #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ - #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTEITC ========================================================= */ - #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ - #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ - #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ - #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ - #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ - #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ - #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ - #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= GTEITLI1 ======================================================== */ - #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ - #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ - #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ - #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ - #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ - #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ - #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ - #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ - #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ -/* ======================================================= GTEITLI2 ======================================================== */ - #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ - #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ - #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ -/* ======================================================== GTEITLB ======================================================== */ - #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ - #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ - #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ - #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ - #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ - #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ - #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ - #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ -/* ======================================================== GTICLF ========================================================= */ - #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ - #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ - #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ - #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ - #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ - #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ -/* ========================================================= GTPC ========================================================== */ - #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ - #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ - #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ - #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ -/* ======================================================= GTADCMSC ======================================================== */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ - #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ - #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ -/* ======================================================= GTADCMSS ======================================================== */ - #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ - #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ -/* ======================================================== GTSECSR ======================================================== */ - #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ - #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ - #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ - #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ - #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ - #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ - #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ - #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ - #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ - #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ - #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTSECR ========================================================= */ - #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ - #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ - #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ - #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ - #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ - #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ - #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ - #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ - #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ - #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ - #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ - #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ - #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ -/* ======================================================== GTBER2 ========================================================= */ - #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ - #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ - #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ - #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ - #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ - #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ - #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ - #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ - #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ - #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ - #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ - #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ - #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ - #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ - #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ - #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ - #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ - #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ - #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ - #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ - #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ -/* ======================================================== GTOLBR ========================================================= */ - #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ - #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ - #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTICCR ========================================================= */ - #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ - #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ - #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ - #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ - #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ - #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ - #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ - #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ - #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ - #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ - #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ - #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ - #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ - #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ - #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ - #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ - #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ - #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ - #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ - #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ - #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= OPSCR ========================================================= */ - #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ - #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ - #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ - #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ - #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ - #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ - #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ - #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ - #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ - #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ - #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ - #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ - #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ - #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ - #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ -/* ======================================================== GTONCWP ======================================================== */ - #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== GTONCCR ======================================================== */ - #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ - #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ - #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ - #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ - #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ - #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ -/* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ -/* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ -/* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ -/* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ -/* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN2 ========================================================= */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ICCR1 ========================================================= */ - #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ - #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ - #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ - #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ - #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ - #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ - #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ - #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ - #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ -/* ========================================================= ICCR2 ========================================================= */ - #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ - #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ - #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ - #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ - #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ - #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ - #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR1 ========================================================= */ - #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ - #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ - #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ - #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ -/* ========================================================= ICMR2 ========================================================= */ - #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ - #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ - #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ - #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ - #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ - #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR3 ========================================================= */ - #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ - #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ - #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ - #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ - #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ - #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ - #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ - #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ -/* ========================================================= ICFER ========================================================= */ - #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ - #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ - #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ - #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ - #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ - #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ - #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ - #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ - #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSER ========================================================= */ - #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ - #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ - #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ - #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ - #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ - #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ - #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ -/* ========================================================= ICIER ========================================================= */ - #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ - #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ - #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ - #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ - #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ - #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ - #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ - #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR1 ========================================================= */ - #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ - #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ - #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ - #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ - #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ - #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ - #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR2 ========================================================= */ - #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ - #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ - #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ - #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ - #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ - #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ - #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ -/* ========================================================= ICBRL ========================================================= */ - #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ - #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICBRH ========================================================= */ - #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ - #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICDRT ========================================================= */ - #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ - #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ -/* ========================================================= ICDRR ========================================================= */ - #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ - #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ -/* ========================================================= ICWUR ========================================================= */ - #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ - #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ - #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ - #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ - #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ - #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICWUR2 ========================================================= */ - #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ - #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ - #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ - #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== IWDTRR ========================================================= */ - #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ - #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ -/* ======================================================== IWDTCR ========================================================= */ - #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ======================================================== IWDTSR ========================================================= */ - #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== IWDTRCR ======================================================== */ - #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= IWDTCSTPR ======================================================= */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PRTS ========================================================== */ - #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ - #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ -/* ========================================================= CECTL ========================================================= */ - #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ - #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ -/* ========================================================= BCTL ========================================================== */ - #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ - #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ - #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ - #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ - #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ - #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ - #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSDVAD ========================================================= */ - #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ - #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ - #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTCTL ========================================================= */ - #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ - #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ - #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ - #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ - #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ - #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ - #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ - #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ - #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ - #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ - #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ - #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ - #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ -/* ========================================================= PRSST ========================================================= */ - #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ - #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ - #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ - #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ -/* ========================================================= INST ========================================================== */ - #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ - #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ -/* ========================================================= INSTE ========================================================= */ - #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ - #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ -/* ========================================================= INIE ========================================================== */ - #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ - #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== INSTFC ========================================================= */ - #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ - #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= DVCT ========================================================== */ - #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ - #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ -/* ======================================================== IBINCTL ======================================================== */ - #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ - #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ - #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ -/* ========================================================= BFCTL ========================================================= */ - #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ - #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ - #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ - #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ - #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ - #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ - #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ - #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ -/* ========================================================= SVCTL ========================================================= */ - #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ - #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ - #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ - #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ - #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ -/* ======================================================= REFCKCTL ======================================================== */ - #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ - #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ -/* ========================================================= STDBR ========================================================= */ - #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ - #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ - #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ - #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ - #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ - #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ -/* ========================================================= EXTBR ========================================================= */ - #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ - #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ - #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ - #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ - #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ -/* ======================================================== BFRECDT ======================================================== */ - #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ - #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BAVLCDT ======================================================== */ - #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ - #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BIDLCDT ======================================================== */ - #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ - #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== OUTCTL ========================================================= */ - #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ - #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ - #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ - #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ - #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ - #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ - #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ - #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ -/* ========================================================= INCTL ========================================================= */ - #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ - #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ - #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ - #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ -/* ======================================================== TMOCTL ========================================================= */ - #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ - #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ - #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ - #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ - #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ - #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ -/* ========================================================= WUCTL ========================================================= */ - #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ - #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ - #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ - #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ - #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ -/* ======================================================== ACKCTL ========================================================= */ - #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ - #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ - #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ - #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTRCTL ======================================================== */ - #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ - #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ - #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTLCTL ======================================================== */ - #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ - #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ - #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ - #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ - #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ - #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ - #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SVTDLG0 ======================================================== */ - #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ - #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= STCTL ========================================================= */ - #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ - #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ATCTL ========================================================= */ - #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ - #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ - #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ - #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ - #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ -/* ========================================================= ATTRG ========================================================= */ - #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ - #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== ATCCNTE ======================================================== */ - #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ - #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ -/* ======================================================== CNDCTL ========================================================= */ - #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ - #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ - #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ - #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ -/* ======================================================== NCMDQP ========================================================= */ -/* ======================================================== NRSPQP ========================================================= */ -/* ======================================================== NTDTBP0 ======================================================== */ -/* ======================================================== NIBIQP ========================================================= */ -/* ========================================================= NRSQP ========================================================= */ -/* ======================================================== HCMDQP ========================================================= */ - #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ - #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HRSPQP ========================================================= */ - #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ - #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HTDTBP ========================================================= */ - #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ - #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== NQTHCTL ======================================================== */ - #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ - #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= NTBTHCTL0 ======================================================= */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ======================================================= NRQTHCTL ======================================================== */ - #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ - #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ -/* ======================================================== HQTHCTL ======================================================== */ - #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= HTBTHCTL ======================================================== */ - #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ========================================================== BST ========================================================== */ - #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ - #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ - #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ - #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ - #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ - #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ - #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ - #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ - #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTE ========================================================== */ - #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ - #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ - #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ - #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ - #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ - #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ - #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ - #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ - #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ -/* ========================================================== BIE ========================================================== */ - #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ - #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ - #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ - #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ - #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ - #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ - #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ - #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ - #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTFC ========================================================= */ - #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ - #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ - #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ - #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ - #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ - #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ - #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ - #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ - #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= NTST ========================================================== */ - #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ - #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ - #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ - #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ - #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ -/* ========================================================= NTSTE ========================================================= */ - #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ - #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ - #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ - #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ - #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ -/* ========================================================= NTIE ========================================================== */ - #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ - #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ - #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ - #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ - #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ -/* ======================================================== NTSTFC ========================================================= */ - #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ - #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ - #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ - #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ -/* ========================================================= HTST ========================================================== */ - #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ - #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ - #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ -/* ========================================================= HTSTE ========================================================= */ - #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ - #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ - #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ -/* ========================================================= HTIE ========================================================== */ - #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ - #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ - #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== HTSTFC ========================================================= */ - #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ - #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ - #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= BCST ========================================================== */ - #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ - #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ - #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ - #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ -/* ========================================================= SVST ========================================================== */ - #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ - #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ - #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ - #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ - #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ -/* ========================================================= WUST ========================================================== */ - #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ - #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ -/* ======================================================== MRCCPT ========================================================= */ - #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ - #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DATBAS0 ======================================================== */ - #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS1 ======================================================== */ - #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS2 ======================================================== */ - #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS3 ======================================================== */ - #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS4 ======================================================== */ - #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS5 ======================================================== */ - #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS6 ======================================================== */ - #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS7 ======================================================== */ - #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= EXDATBAS ======================================================== */ - #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ - #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ - #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ - #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ - #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= SDATBAS0 ======================================================== */ - #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS1 ======================================================== */ - #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS2 ======================================================== */ - #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================== MSDCT0 ========================================================= */ - #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT1 ========================================================= */ - #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT2 ========================================================= */ - #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT3 ========================================================= */ - #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT4 ========================================================= */ - #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT5 ========================================================= */ - #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT6 ========================================================= */ - #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT7 ========================================================= */ - #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ========================================================= SVDCT ========================================================= */ - #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ - #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ - #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ - #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ - #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ - #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ - #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ - #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================= SDCTPIDL ======================================================== */ -/* ======================================================= SDCTPIDH ======================================================== */ -/* ======================================================== SVDVAD0 ======================================================== */ - #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD1 ======================================================== */ - #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD2 ======================================================== */ - #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== CSECMD ========================================================= */ - #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ - #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ - #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ - #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ -/* ======================================================== CEACTST ======================================================== */ - #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ - #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CMWLG ========================================================= */ - #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ - #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= CMRLG ========================================================= */ - #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ - #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ - #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ - #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ -/* ======================================================== CETSTMD ======================================================== */ - #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ - #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ -/* ======================================================== CGDVST ========================================================= */ - #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ - #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ - #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ - #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ - #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ - #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ - #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ -/* ======================================================== CMDSPW ========================================================= */ - #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ - #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPR ========================================================= */ - #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ - #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ - #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ - #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPT ========================================================= */ - #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ - #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ - #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ - #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ -/* ========================================================= CETSM ========================================================= */ - #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ - #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ - #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ - #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ - #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ - #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ - #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ -/* ========================================================= CETSS ========================================================= */ - #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ - #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ - #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ - #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ - #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ -/* ======================================================= CGHDRCAP ======================================================== */ - #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ - #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ - #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ - #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BITCNT ========================================================= */ - #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ - #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ - #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ - #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ -/* ======================================================== NQSTLV ========================================================= */ - #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ - #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ - #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ - #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================= NDBSTLV0 ======================================================== */ - #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================= NRSQSTLV ======================================================== */ - #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ - #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HQSTLV ========================================================= */ - #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ - #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HDBSTLV ======================================================== */ - #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================== PRSTDBG ======================================================== */ - #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ - #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ - #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ - #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ - #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ -/* ======================================================= MSERRCNT ======================================================== */ - #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ - #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ -/* ======================================================== SC1CPT ========================================================= */ - #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ - #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ -/* ======================================================== SC2CPT ========================================================= */ - #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ - #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= OADPT ========================================================= */ - #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== MSTPCRA ======================================================== */ - #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRB ======================================================== */ - #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ - #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRC ======================================================== */ - #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ - #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRD ======================================================== */ - #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ - #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRE ======================================================== */ - #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ - #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ -/* ======================================================= LSMRWDIS ======================================================== */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ - #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PODR ========================================================== */ - #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ========================================================== PDR ========================================================== */ - #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EIDR ========================================================== */ - #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ - #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ -/* ========================================================= PIDR ========================================================== */ - #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PORR ========================================================== */ - #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ - #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ -/* ========================================================= POSR ========================================================== */ - #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EORR ========================================================== */ - #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ - #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ -/* ========================================================= EOSR ========================================================== */ - #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PFENET ========================================================= */ - #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ - #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ - #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ - #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================== PRWCNTR ======================================================== */ - #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ - #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SFMSMD ========================================================= */ - #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ - #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ - #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ - #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ - #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ - #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ - #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ - #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ - #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ - #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ - #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ -/* ======================================================== SFMSSC ========================================================= */ - #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ - #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ - #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ - #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSKC ========================================================= */ - #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ - #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ - #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMSST ========================================================= */ - #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ - #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ - #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ - #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMCOM ========================================================= */ - #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ - #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMCMD ========================================================= */ - #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ - #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCST ========================================================= */ - #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ - #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ - #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMSIC ========================================================= */ - #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ - #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMSAC ========================================================= */ - #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ - #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ - #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMSDC ========================================================= */ - #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ - #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ - #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ - #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ - #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ - #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSPC ========================================================= */ - #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ - #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ - #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMPMD ========================================================= */ - #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ - #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCNT1 ======================================================== */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ - #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ - #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ - #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECCNT ======================================================== */ - #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ - #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINCNT ======================================================== */ - #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ - #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ -/* ======================================================== RHRCNT ========================================================= */ - #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ - #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ -/* ======================================================== RWKCNT ========================================================= */ - #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================== RDAYCNT ======================================================== */ - #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RMONCNT ======================================================== */ - #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RYRCNT ========================================================= */ - #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT0AR ======================================================== */ - #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ - #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECAR ========================================================= */ - #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT1AR ======================================================== */ - #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ - #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINAR ========================================================= */ - #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT2AR ======================================================== */ - #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ - #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RHRAR ========================================================= */ - #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT3AR ======================================================== */ - #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ - #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RWKAR ========================================================= */ - #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================= BCNT0AER ======================================================== */ - #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RDAYAR ========================================================= */ - #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT1AER ======================================================== */ - #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RMONAR ========================================================= */ - #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT2AER ======================================================== */ - #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ========================================================= RYRAR ========================================================= */ - #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT3AER ======================================================== */ - #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RYRAREN ======================================================== */ - #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR1 ========================================================== */ - #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ - #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ - #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ - #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ - #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ - #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ - #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR2 ========================================================== */ - #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ - #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ - #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ - #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ - #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ - #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ - #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ - #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ - #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR4 ========================================================== */ - #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ - #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ - #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRH ========================================================== */ - #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ - #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRL ========================================================== */ - #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= RADJ ========================================================== */ - #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ - #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ - #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ - #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ -/* ========================================================= RADJ2 ========================================================= */ - #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ - #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SMR ========================================================== */ - #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ - #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ - #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ - #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ======================================================= SMR_SMCI ======================================================== */ - #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ - #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ - #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ - #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ - #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ========================================================== BRR ========================================================== */ - #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ - #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ -/* ========================================================== SCR ========================================================== */ - #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ======================================================= SCR_SMCI ======================================================== */ - #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ========================================================== TDR ========================================================== */ - #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ - #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ -/* ========================================================== SSR ========================================================== */ - #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_FIFO ======================================================== */ - #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ - #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ - #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_MANC ======================================================== */ - #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ - #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_SMCI ======================================================== */ - #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ - #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ========================================================== RDR ========================================================== */ - #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ - #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ -/* ========================================================= SCMR ========================================================== */ - #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ - #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ - #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ - #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ - #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ - #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ -/* ========================================================= SEMR ========================================================== */ - #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ - #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ - #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ - #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ - #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ - #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ - #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ - #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ - #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= SNFR ========================================================== */ - #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ - #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ -/* ========================================================= SIMR1 ========================================================= */ - #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ - #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ - #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ - #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR2 ========================================================= */ - #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ - #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ - #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ - #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR3 ========================================================= */ - #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ - #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ - #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ - #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ - #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ - #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SISR ========================================================== */ - #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ - #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ -/* ========================================================= SPMR ========================================================== */ - #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ - #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ - #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ - #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ - #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ - #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ - #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ - #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ -/* ========================================================= TDRHL ========================================================= */ - #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ - #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FTDRHL ========================================================= */ - #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ -/* ========================================================= FTDRH ========================================================= */ - #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ - #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ - #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FTDRL ========================================================= */ - #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ - #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= RDRHL ========================================================= */ - #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ - #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FRDRHL ========================================================= */ - #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ - #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ - #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ - #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ - #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ - #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ -/* ======================================================= TDRHL_MAN ======================================================= */ - #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ -/* ======================================================= RDRHL_MAN ======================================================= */ - #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRH ========================================================= */ - #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ - #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ - #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRL ========================================================= */ - #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ - #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= MDDR ========================================================== */ - #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ - #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ -/* ========================================================= DCCR ========================================================== */ - #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ - #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ - #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ - #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ - #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ - #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ -/* ========================================================== FCR ========================================================== */ - #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ - #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ - #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ - #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ - #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ - #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ - #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ - #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ -/* ========================================================== FDR ========================================================== */ - #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ - #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ - #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ - #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ -/* ========================================================== LSR ========================================================== */ - #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ - #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ - #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ - #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ -/* ========================================================== CDR ========================================================== */ - #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ - #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ -/* ========================================================= SPTR ========================================================== */ - #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ - #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ - #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ - #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ - #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ - #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ - #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ - #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ACTR ========================================================== */ - #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ - #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ - #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ - #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ - #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ - #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ -/* ========================================================= ESMER ========================================================= */ - #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ - #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR0 ========================================================== */ - #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ - #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ - #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ - #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR1 ========================================================== */ - #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ - #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ - #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ - #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ - #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ - #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ -/* ========================================================== CR2 ========================================================== */ - #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ - #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ - #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ - #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ - #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ -/* ========================================================== CR3 ========================================================== */ - #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ - #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ -/* ========================================================== PCR ========================================================== */ - #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ - #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ - #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ - #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ -/* ========================================================== ICR ========================================================== */ - #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ - #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ - #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ - #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ - #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ - #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ - #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ - #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ - #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ - #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ - #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ - #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ - #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ -/* ========================================================= STCR ========================================================== */ - #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ - #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ - #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ - #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ - #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ - #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ - #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0DR ========================================================= */ -/* ========================================================= CF0CR ========================================================= */ - #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ - #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ - #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ - #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ - #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ - #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ - #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ - #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ - #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0RR ========================================================= */ -/* ======================================================== PCF1DR ========================================================= */ -/* ======================================================== SCF1DR ========================================================= */ -/* ========================================================= CF1CR ========================================================= */ - #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ - #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ - #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ - #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ - #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ - #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ - #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ - #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ - #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF1RR ========================================================= */ -/* ========================================================== TCR ========================================================== */ - #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ - #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ -/* ========================================================== TMR ========================================================== */ - #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ - #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ - #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ - #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ - #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ -/* ========================================================= TPRE ========================================================== */ -/* ========================================================= TCNT ========================================================== */ -/* ======================================================= SCIMSKEN ======================================================== */ - #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ - #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== MMR ========================================================== */ - #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ - #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ - #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ - #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ - #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ - #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ - #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ - #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ -/* ========================================================= TMPR ========================================================== */ - #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ - #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ - #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= RMPR ========================================================== */ - #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ - #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ - #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= MESR ========================================================== */ - #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ - #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ - #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ - #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ -/* ========================================================= MECR ========================================================== */ - #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ - #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ - #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ - #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SD_CMD ========================================================= */ - #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ - #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ - #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ - #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ - #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ - #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ - #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ - #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ -/* ======================================================== SD_ARG ========================================================= */ - #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ - #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_ARG1 ======================================================== */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== SD_STOP ======================================================== */ - #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ - #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ - #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_SECCNT ======================================================= */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SD_RSP10 ======================================================== */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP1 ======================================================== */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP32 ======================================================== */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP3 ======================================================== */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP54 ======================================================== */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP5 ======================================================== */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP76 ======================================================== */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ -/* ======================================================== SD_RSP7 ======================================================== */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ -/* ======================================================= SD_INFO1 ======================================================== */ - #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ - #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ - #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ - #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_INFO2 ======================================================== */ - #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ - #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ - #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ - #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ - #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ - #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ - #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ - #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ - #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ - #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ - #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ - #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO1_MASK ===================================================== */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO2_MASK ===================================================== */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_CLK_CTRL ====================================================== */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ -/* ======================================================== SD_SIZE ======================================================== */ - #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ - #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= SD_OPTION ======================================================= */ - #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ - #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ - #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ - #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ - #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ -/* ====================================================== SD_ERR_STS1 ====================================================== */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_ERR_STS2 ====================================================== */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SD_BUF0 ======================================================== */ - #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ - #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SDIO_MODE ======================================================= */ - #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ - #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ - #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ - #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SDIO_INFO1 ======================================================= */ - #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ -/* ==================================================== SDIO_INFO1_MASK ==================================================== */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_DMAEN ======================================================== */ - #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ - #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ -/* ======================================================= SOFT_RST ======================================================== */ - #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ - #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ -/* ======================================================= SDIF_MODE ======================================================= */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ -/* ======================================================= EXT_SWAP ======================================================== */ - #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ - #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SPCR ========================================================== */ - #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ - #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ - #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ - #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ - #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ - #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ - #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ - #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ - #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ -/* ========================================================= SSLP ========================================================== */ - #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ - #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ - #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ - #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ - #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ - #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ - #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ - #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ - #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPCR ========================================================= */ - #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ - #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ - #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ - #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ - #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSR ========================================================== */ - #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ - #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ - #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ - #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ - #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ - #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ - #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ - #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ - #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ -/* ========================================================= SPDR ========================================================== */ -/* ======================================================== SPDR_HA ======================================================== */ -/* ======================================================== SPDR_BY ======================================================== */ -/* ========================================================= SPSCR ========================================================= */ - #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ - #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ -/* ========================================================= SPBR ========================================================== */ - #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ - #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ -/* ========================================================= SPDCR ========================================================= */ - #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ - #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ - #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ - #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ - #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ - #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= SPCKD ========================================================= */ - #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ - #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SSLND ========================================================= */ - #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ - #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPND ========================================================== */ - #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ - #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR2 ========================================================= */ - #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ - #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ - #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ - #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ - #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ - #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ - #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCMD ========================================================= */ - #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ - #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ - #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ - #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ - #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ - #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ - #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ - #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ - #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ - #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ - #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ - #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ -/* ======================================================== SPDCR2 ========================================================= */ - #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ - #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ - #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSSR ========================================================= */ - #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ - #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ - #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR3 ========================================================= */ - #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ - #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ - #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ - #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPR ========================================================== */ - #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ - #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ - #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ - #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PARIOAD ======================================================== */ - #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR ======================================================== */ - #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMWTSC ======================================================== */ -/* ======================================================== ECCMODE ======================================================== */ - #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ - #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== ECC2STS ======================================================== */ - #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ - #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECC1STSEN ======================================================= */ - #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ - #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ECC1STS ======================================================== */ - #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ - #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCPRCR ======================================================== */ - #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECCPRCR2 ======================================================== */ - #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ - #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCETST ======================================================== */ - #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ - #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCOAD ========================================================= */ - #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR2 ======================================================= */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ - #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SSICR ========================================================= */ - #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ - #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ - #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ - #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ - #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ - #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ - #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ - #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ - #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ - #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ - #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ - #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ - #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ - #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ - #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ - #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ - #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ - #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ - #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ - #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ - #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ - #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ -/* ========================================================= SSISR ========================================================= */ - #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ - #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ - #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ - #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ - #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ - #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ - #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ - #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ - #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ - #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ - #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFCR ========================================================= */ - #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ - #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ - #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ - #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ - #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ - #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ - #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ - #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ - #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ - #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFSR ========================================================= */ - #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ - #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ - #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ - #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ - #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFTDR ======================================================== */ - #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ - #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFTDR16 ======================================================= */ -/* ======================================================= SSIFTDR8 ======================================================== */ -/* ======================================================== SSIFRDR ======================================================== */ - #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ - #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFRDR16 ======================================================= */ -/* ======================================================= SSIFRDR8 ======================================================== */ -/* ======================================================== SSIOFR ========================================================= */ - #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ - #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ - #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ - #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== SSISCR ========================================================= */ - #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ - #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ - #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ - #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ -/* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ -/* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ -/* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ -/* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ -/* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ -/* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR2 ======================================================== */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ -/* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ -/* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ -/* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ -/* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ -/* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ -/* ========================================================= LPOPT ========================================================= */ - #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ - #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ - #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ -/* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ -/* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ -/* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ -/* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ -/* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ -/* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ -/* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ -/* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ -/* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ -/* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ -/* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ -/* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ -/* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ -/* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LDOSCR ========================================================= */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ -/* ======================================================= PL2LDOSCR ======================================================= */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ -/* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ -/* ========================================================= SOMRG ========================================================= */ - #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ - #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ -/* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ -/* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ -/* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ -/* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ -/* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== SCISPICKDIVCR ===================================================== */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== CANFDCKDIVCR ====================================================== */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== GPTCKDIVCR ======================================================= */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== USB60CKDIVCR ====================================================== */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== CECCKDIVCR ======================================================= */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== I3CCKDIVCR ======================================================= */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== IICCKDIVCR ======================================================= */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ -/* ====================================================== SCISPICKCR ======================================================= */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= CANFDCKCR ======================================================= */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== GPTCKCR ======================================================== */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= USB60CKCR ======================================================= */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCKCR ======================================================== */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== IICCKCR ======================================================== */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== I3CCKCR ======================================================== */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ - #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ -/* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ -/* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ -/* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCDR ========================================================= */ - #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ - #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCR ========================================================== */ - #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ - #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ - #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ - #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ - #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ - #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ========================================================= CFIFO ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DVCHGR ========================================================= */ - #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ - #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ - #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ - #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ====================================================== USBBCCTRL0 ======================================================= */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ -/* ======================================================== UCKSEL ========================================================= */ - #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ - #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ -/* ========================================================= USBMC ========================================================= */ - #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ - #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ - #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSLEW ======================================================== */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR0R_FS ======================================================= */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR1R_FS ======================================================= */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= WDTRR ========================================================= */ - #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ - #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ -/* ========================================================= WDTCR ========================================================= */ - #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ========================================================= WDTSR ========================================================= */ - #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== WDTRCR ========================================================= */ - #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= WDTCSTPR ======================================================== */ - #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFOAD ========================================================= */ - #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ========================================================= TZFPT ========================================================= */ - #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CCACTL ========================================================= */ - #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ - #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCAFCT ========================================================= */ - #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ - #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCALCF ========================================================= */ - #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ - #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ -/* ======================================================== SCACTL ========================================================= */ - #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ - #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCAFCT ========================================================= */ - #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCALCF ========================================================= */ - #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ -/* ======================================================== CAPOAD ========================================================= */ - #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================== CAPRCR ========================================================= */ - #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ - #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ - #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CSAR ========================================================== */ - #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ - #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ - #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ - #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ -/* ======================================================== SRAMSAR ======================================================== */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ -/* ======================================================= STBRAMSAR ======================================================= */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DTCSAR ========================================================= */ - #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ - #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACSAR ======================================================== */ - #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ - #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARA ======================================================== */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ -/* ======================================================== ICUSARB ======================================================== */ - #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ - #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARC ======================================================== */ - #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ - #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ -/* ======================================================== ICUSARD ======================================================== */ - #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ - #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARE ======================================================== */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARF ======================================================== */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARG ======================================================== */ - #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARH ======================================================== */ - #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARI ======================================================== */ - #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARM ======================================================== */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARA ======================================================== */ - #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ - #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARB ======================================================== */ - #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ - #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARC ======================================================== */ - #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ - #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSPARC ======================================================== */ - #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ - #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MMPUSARA ======================================================== */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ -/* ======================================================= MMPUSARB ======================================================== */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGSAR ======================================================== */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DMACCHSAR ======================================================= */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ -/* ======================================================== CPUDSAR ======================================================== */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SRAMSABAR0 ======================================================= */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ====================================================== SRAMSABAR1 ======================================================= */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ======================================================== TEVTRCR ======================================================== */ - #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ - #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CADR ========================================================== */ - #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ - #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ - #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ - #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ - #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ - #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ - #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ - #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ - #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ - #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ - #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ - #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ - #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ - #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ - #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ - #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL1 ======================================================== */ - #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ - #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ - #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ - #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ - #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ - #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ - #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= STATB ========================================================= */ - #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ - #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= STATL ========================================================= */ - #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ - #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC0L ========================================================= */ - #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ - #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC1L ========================================================= */ - #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ - #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATB ========================================================== */ - #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ - #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMT ========================================================== */ - #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ - #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLL ========================================================= */ - #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ - #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLH ========================================================= */ - #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ - #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBL ========================================================= */ - #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ - #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBH ========================================================= */ - #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ - #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LL ========================================================= */ - #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ - #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LH ========================================================= */ - #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ - #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LL ========================================================= */ - #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ - #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LH ========================================================= */ - #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ - #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBL ========================================================= */ - #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ - #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBH ========================================================= */ - #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ - #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMP ========================================================== */ - #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ - #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CECEXMD ======================================================== */ - #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ - #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ - #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= CECEXMON ======================================================== */ - #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ - #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ - #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ -/* ========================================================= CTXD ========================================================== */ -/* ========================================================= CRXD ========================================================== */ -/* ========================================================= CECES ========================================================= */ - #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ - #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ - #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ - #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ - #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ - #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ - #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ - #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ -/* ========================================================= CECS ========================================================== */ - #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ - #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ - #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ - #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ - #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ - #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ - #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ -/* ========================================================= CECFC ========================================================= */ - #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ - #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ - #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ - #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ - #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ - #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ - #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ - #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL0 ======================================================== */ - #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ - #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ - #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ - #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ - #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ - #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ - #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ - #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DCR ========================================================== */ - #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ - #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ - #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ -/* ========================================================== DAR ========================================================== */ - #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ - #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ - #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ - #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ - #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= DCSR ========================================================== */ - #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ - #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ - #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ - #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ - #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ - #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ - #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ - #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ - #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ - #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ -/* ========================================================== DSR ========================================================== */ - #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ - #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ - #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ - #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ -/* ========================================================= MDTR ========================================================== */ - #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ - #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ - #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ - #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ - #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ - #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ -/* ========================================================= ACTR ========================================================== */ - #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ - #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ACAR ========================================================== */ - #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ - #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DRCSTR ========================================================= */ - #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ - #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ - #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ - #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ - #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ - #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ - #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ - #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ - #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ -/* ======================================================== DWCSTR ========================================================= */ - #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ - #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ - #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ - #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ - #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ - #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ - #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ - #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ - #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ - #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ - #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ -/* ========================================================= DCSTR ========================================================= */ - #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ - #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ - #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ - #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ -/* ========================================================= CDSR ========================================================== */ - #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ - #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ - #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ - #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ - #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ - #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ - #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ - #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ - #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ -/* ========================================================= MDLR ========================================================== */ - #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ - #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ - #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ - #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ - #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ -/* ========================================================= MRWCR ========================================================= */ - #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ - #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ - #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ - #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ - #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ -/* ======================================================== MRWCSR ========================================================= */ - #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ - #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ - #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ - #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ - #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ - #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ - #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ - #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ - #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ - #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ - #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ - #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ - #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ - #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ - #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ -/* ========================================================== ESR ========================================================== */ - #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ - #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ - #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ - #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ -/* ========================================================= CWNDR ========================================================= */ - #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ - #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CWDR ========================================================== */ - #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ - #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ - #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ - #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ - #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ -/* ========================================================== CRR ========================================================== */ - #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ - #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ - #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ - #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ - #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= ACSR ========================================================== */ - #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ - #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ - #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ -/* ======================================================== DCSMXR ========================================================= */ - #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ - #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ - #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ - #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== DWSCTSR ======================================================== */ - #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ - #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ - #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ - #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ - #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CFIFO ========================================================= */ - #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ - #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ - #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPEBUF ======================================================== */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================= PHYTRIM1 ======================================================== */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ -/* ======================================================= PHYTRIM2 ======================================================== */ - #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ - #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ - #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ - #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= EC710CTL ======================================================== */ - #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ - #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ - #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ - #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ - #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ - #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ - #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ - #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ -/* ======================================================= EC710TMC ======================================================== */ - #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ - #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ - #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ -/* ======================================================= EC710TED ======================================================== */ - #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ - #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= EC710EAD0 ======================================================= */ - #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ - #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCKMHZ ========================================================= */ - #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ - #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ - -/** @} */ /* End of group PosMask_peripherals */ - - #ifdef __cplusplus -} - #endif - -#endif /* R7FA6M5BH_H */ - -/** @} */ /* End of group R7FA6M5BH */ - -/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_cfg.h deleted file mode 100644 index 825f8cd32..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BOARD_CFG_H_ -#define BOARD_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - void bsp_init(void * p_args); - - #ifdef __cplusplus - } - #endif -#endif /* BOARD_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_sdram.h deleted file mode 100644 index 2d5eb7405..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/board_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BOARD_SDRAM_H -#define BOARD_SDRAM_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. - * It is only present if the new support has not been enabled. */ -#if 1 != BSP_CFG_SDRAM_ENABLED - #define bsp_sdram_init() R_BSP_SdramInit(true) -#endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_api.h deleted file mode 100644 index d912bc0ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_api.h +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_API_H -#define BSP_API_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* FSP Common Includes. */ -#include "fsp_common_api.h" - -/* Gets MCU configuration information. */ -#include "bsp_cfg.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic push - -/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. - * We are not modifying these files so we will ignore these warnings temporarily. */ - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" -#endif - -/* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_exceptions.h" -#include "vector_data.h" - -/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ -#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" -#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic pop -#endif - -#if defined(BSP_API_OVERRIDE) - #include BSP_API_OVERRIDE -#else - -/* BSP Common Includes. */ - #include "../../src/bsp/mcu/all/bsp_common.h" - -/* BSP MCU Specific Includes. */ - #include "../../src/bsp/mcu/all/bsp_register_protection.h" - #include "../../src/bsp/mcu/all/bsp_irq.h" - #include "../../src/bsp/mcu/all/bsp_io.h" - #include "../../src/bsp/mcu/all/bsp_group_irq.h" - #include "../../src/bsp/mcu/all/bsp_clocks.h" - #include "../../src/bsp/mcu/all/bsp_module_stop.h" - #include "../../src/bsp/mcu/all/bsp_security.h" - -/* Factory MCU information. */ - #include "../../inc/fsp_features.h" - -/* BSP Common Includes (Other than bsp_common.h) */ - #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" - - #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") - #include "../../src/bsp/mcu/all/internal/bsp_internal.h" - #endif - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_cfg.h deleted file mode 100644 index 8074418ad..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_cfg.h +++ /dev/null @@ -1,61 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - #include "bsp_clock_cfg.h" - #include "bsp_mcu_family_cfg.h" - #include "board_cfg.h" - #define RA_NOT_DEFINED 0 - #ifndef BSP_CFG_RTOS - #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else - #define BSP_CFG_RTOS (0) - #endif - #endif - #ifndef BSP_CFG_RTC_USED - #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) - #endif - #undef RA_NOT_DEFINED - #if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif - #define BSP_CFG_MCU_VCC_MV (3300) - #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0) - #define BSP_CFG_PARAM_CHECKING_ENABLE (0) - #define BSP_CFG_ASSERT (0) - - #define BSP_CFG_PFS_PROTECT ((1)) - - #define BSP_CFG_C_RUNTIME_INIT ((1)) - #define BSP_CFG_EARLY_INIT ((0)) - - #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED - #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - #endif - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE - #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE - #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS - #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - #endif - - #ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_clocks.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_clocks.h deleted file mode 100644 index 7eb0f69cf..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_clocks.h +++ /dev/null @@ -1,1727 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_CLOCKS_H -#define BSP_CLOCKS_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_clock_cfg.h" -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match SCKCR.CKSEL values. */ -#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. - #endif - #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. - #endif - #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. - #endif -#else - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ - #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. - #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. - -/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ - #define BSP_PRV_OSTC_OFFSET (0x7FU) - -#endif - -/* PLLs are not supported in the following scenarios: - * - When using low voltage mode - * - When using an MCU that does not have a PLL - * - When the PLL only accepts the main oscillator as a source and XTAL is not used - */ -#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) - #define BSP_PRV_PLL_SUPPORTED (1) - #if BSP_FEATURE_CGC_HAS_PLL2 - #define BSP_PRV_PLL2_SUPPORTED (1) - #else - #define BSP_PRV_PLL2_SUPPORTED (0) - #endif -#else - #define BSP_PRV_PLL_SUPPORTED (0) - #define BSP_PRV_PLL2_SUPPORTED (0) -#endif - -/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency - * calculated here is also used to initialize the g_clock_freq array. */ -#if BSP_PRV_PLL_SUPPORTED - #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ - (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif -#if BSP_PRV_PLL2_SUPPORTED - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif - -#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) - -/* Frequencies of clocks with fixed freqencies. */ -#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz -#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz - -#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #endif - #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ - (BSP_CFG_PLL_DIV + 1U)) - #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ - (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) - #endif -#endif - -/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ -#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) -#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) -#else - #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) -#endif - -#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) -#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) -#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) -#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) -#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) -#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) -#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) -#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) - -/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have - * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ -#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) -#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) -#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) -#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) -#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) -#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) -#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) -#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) -#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) -#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) - -/* System clock divider options. */ -#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. -#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. -#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. -#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. -#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. -#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. -#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. -#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). -#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. -#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. -#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. -#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. - -/* USB clock divider options. */ -#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 -#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 -#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 -#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 -#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 -#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 -#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 -#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 -#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 -#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 - -/* USB60 clock divider options. */ -#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 -#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 -#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 -#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 -#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 -#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 -#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 -#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 -#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 -#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 - -/* GLCD clock divider options. */ -#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 -#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 -#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 -#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 -#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 -#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 -#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 -#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 -#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 -#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 - -/* OCTA clock divider options. */ -#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 - -/* CANFD clock divider options. */ -#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 - -/* SCI clock divider options. */ -#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 -#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 -#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 -#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 -#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 -#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 -#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 -#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 -#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 -#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 - -/* SPI clock divider options. */ -#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 -#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 -#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 -#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 -#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 -#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 -#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 -#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 -#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 -#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 - -/* SCISPI clock divider options. */ -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 - -/* GPT clock divider options. */ -#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 -#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 -#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 -#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 -#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 -#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 -#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 -#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 -#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 -#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 - -/* IIC clock divider options. */ -#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 -#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 -#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 -#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 -#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 - -/* CEC clock divider options. */ -#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 -#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 - -/* I3C clock divider options. */ -#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 -#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 -#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 -#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 -#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 -#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 -#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 -#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 -#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 -#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 - -/* ADC clock divider options. */ -#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 -#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 -#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 -#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 -#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 -#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 -#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 -#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 -#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 -#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 - -/* SAU clock divider options. */ -#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 -#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 -#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 -#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 -#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 -#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 - -/* Extra peripheral 0 clock divider options. */ -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 - -/* PLL divider options. */ -#define BSP_CLOCKS_PLL_DIV_1 (0) -#define BSP_CLOCKS_PLL_DIV_2 (1) -#define BSP_CLOCKS_PLL_DIV_3 (2) -#define BSP_CLOCKS_PLL_DIV_4 (3) -#define BSP_CLOCKS_PLL_DIV_5 (4) -#define BSP_CLOCKS_PLL_DIV_6 (5) -#define BSP_CLOCKS_PLL_DIV_8 (7) -#define BSP_CLOCKS_PLL_DIV_9 (8) -#define BSP_CLOCKS_PLL_DIV_1_5 (9) -#define BSP_CLOCKS_PLL_DIV_16 (15) - -/* PLL multiplier options. */ -#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - -/* Offset from decimal multiplier to register value for PLLCCR type 4. */ - #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) - -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) - -#else - - #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U))) - -#endif - -/* Configuration option used to disable clock output. */ -#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) - -/* HOCO cycles per microsecond. */ -#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) - -/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ -#if BSP_HOCO_HZ < 48000000U - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) -#else - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) -#endif - -/* Create a mask of valid bits in SCKDIVCR. */ -#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) -#else - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) -#else - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) -#else - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) -#else - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB - #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) -#else - #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#else - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) -#else - #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) -#endif -#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ - BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ - BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ - BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) - -/* FLL is only used when enabled, present and the subclock is populated. */ -#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_PRV_HOCO_USE_FLL (1) - #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US - #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) - #endif -#else - #define BSP_PRV_HOCO_USE_FLL (0) - #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) -#endif - -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR - #define BSP_PRV_RTC_RESET_DELAY_US (200) -#endif - -/* Operating power control modes. */ -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed -#else - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed - #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed -#endif -#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -typedef struct -{ - uint32_t pll_freq; -} bsp_clock_up2025-08-12_callback_args_t; - - #if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_up2025-08-12_callback_t)(bsp_clock_up2025-08-12_callback_args_t * - p_callback_args); - #elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_up2025-08-12_callback_t)(bsp_clock_up2025-08-12_callback_args_t * - p_callback_args); - #endif - -#endif - -/** PLL multiplier values */ -typedef enum e_cgc_pll_mul -{ - CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 - CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 - CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 - CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 - CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 - CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 - CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 - CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 - CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 - CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 - CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 - CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 - CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 - CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 - CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 - CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 - CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 - CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 - CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 - CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 - CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 - CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 - CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 - CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 - CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 - CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 - CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 - CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 - CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 - CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 - CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 - CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 - CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 - CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 - CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 - CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 - CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 - CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 - CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 - CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 - CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 - CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 - CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 - CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 - CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 - CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 - CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 - CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 - CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 - CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 - CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 - CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 - CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 - CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 - CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 - CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 - CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 - CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 - CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 - CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 - CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 - CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 - CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 - CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 - CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 - CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 - CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 - CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 - CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 - CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 - CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 - CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 - CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 - CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 - CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 - CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 - CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 - CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 - CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 - CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 - CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 - CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 - CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 - CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 - CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 - CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 - CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 - CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 - CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 - CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 - CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 - CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 - CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 - CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 - CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 - CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 - CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 - CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 - CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 - CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 - CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 - CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 - CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 - CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 - CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 - CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 - CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 - CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 - CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 - CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 - CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 - CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 - CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 - CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 - CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 - CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 - CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 - CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 - CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 - CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 - CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 - CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 - CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 - CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 - CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 - CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 - CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 - CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 - CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 - CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 - CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 - CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 - CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 - CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 - CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 - CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 - CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 - CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 - CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 - CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 - CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 - CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 - CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 - CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 - CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 - CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 - CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 - CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 - CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 - CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 - CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 - CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 - CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 - CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 - CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 - CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 - CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 - CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 - CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 - CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 - CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 - CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 - CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 - CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 - CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 - CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 - CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 - CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 - CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 - CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 - CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 - CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 - CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 - CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 - CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 - CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 - CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 - CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 - CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 - CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 - CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 - CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 - CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 - CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 - CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 - CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 - CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 - CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 - CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 - CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 - CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 - CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 - CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 - CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 - CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 - CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 - CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 - CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 - CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 - CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 - CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 - CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 - CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 - CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 - CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 - CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 - CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 - CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 - CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 - CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 - CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 - CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 - CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 - CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 - CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 - CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 - CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 - CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 - CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 - CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 - CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 - CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 - CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 - CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 - CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 - CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 - CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 - CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 - CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 - CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 - CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 - CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 - CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 - CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 - CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 - CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 - CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 - CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 - CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 - CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 - CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 - CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 - CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 - CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 - CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 - CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 - CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 - CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 - CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 - CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 - CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 - CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 - CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 - CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 - CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 - CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 - CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 - CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 - CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 - CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 - CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 - CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 - CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 - CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 - CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 - CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 - CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 - CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 - CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 - CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 - CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 - CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 - CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 - CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 - CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 - CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 - CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 - CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 - CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 - CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 - CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 - CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 - CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 - CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 - CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 - CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 - CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 - CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 - CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 - CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 - CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 - CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 - CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 - CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 - CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 - CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 - CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 - CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 - CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 - CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 - CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 - CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 - CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 - CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 - CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 - CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 - CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 - CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 - CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 - CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 - CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 - CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 - CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 - CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 - CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 - CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 - CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 - CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 - CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 - CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 - CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 - CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 - CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 - CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 - CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 - CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 - CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 - CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 - CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 - CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 - CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 - CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 - CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 - CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 - CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 - CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 - CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 - CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 - CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 - CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 - CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 - CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 - CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 - CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 - CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 - CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 - CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 - CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 - CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 - CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 - CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 - CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 - CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 - CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 - CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 - CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 - CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 - CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 - CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 - CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 - CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 - CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 - CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 - CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 - CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 - CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 - CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 - CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 - CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 - CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 - CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 - CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 - CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 - CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 - CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 - CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 - CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 - CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 - CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 - CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 - CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 - CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 - CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 - CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 - CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 - CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 - CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 - CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 - CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 - CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 - CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 - CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 - CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 - CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 - CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 - CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 - CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 - CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 - CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 - CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 - CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 - CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 - CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 - CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 - CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 - CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 - CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 - CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 - CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 - CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 - CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 - CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 - CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 - CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 - CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 - CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 - CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 - CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 - CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 - CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 - CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 - CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 - CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 - CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 - CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 - CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 - CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 - CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 - CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 - CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 - CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 - CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 - CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 - CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 - CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 - CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 - CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 - CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 - CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 - CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 - CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 - CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 - CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 - CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 - CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 - CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 - CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 - CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 - CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 - CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 - CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 - CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 - CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 - CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 - CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 - CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 - CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 - CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 - CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 - CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 - CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 - CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 - CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 - CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 - CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 - CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 - CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 - CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 - CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 - CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 - CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 - CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 - CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 - CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 - CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 - CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 - CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 - CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 - CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 - CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 - CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 - CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 - CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 - CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 - CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 - CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 - CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 - CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 - CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 - CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 - CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 - CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 - CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 - CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 - CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 - CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 - CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 - CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 - CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 - CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 - CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 - CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 - CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 - CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 - CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 - CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 - CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 - CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 - CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 - CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 - CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 - CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 - CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 - CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 - CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 - CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 - CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 - CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 - CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 - CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 - CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 - CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 - CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 - CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 - CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 - CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 - CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 - CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 - CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 - CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 - CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 - CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 - CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 - CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 - CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 - CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 - CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 - CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 - CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 - CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 - CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 - CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 - CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 - CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 - CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 - CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 - CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 - CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 - CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 - CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 - CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 - CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 - CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 - CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 - CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 - CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 - CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 - CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 - CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 - CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 - CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 - CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 - CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 - CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 - CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 - CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 - CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 - CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 - CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 - CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 - CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 - CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 - CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 - CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 - CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 - CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 - CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 - CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 - CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 - CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 - CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 - CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 - CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 - CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 - CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 - CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 - CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 - CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 - CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 - CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 - CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 - CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 - CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 - CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 - CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 - CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 - CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 - CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 - CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 - CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 - CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 - CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 - CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 - CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 - CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 - CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 - CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 - CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 - CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 - CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 - CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 - CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 - CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 - CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 - CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 - CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 - CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 - CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 - CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 - CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 - CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 - CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 - CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 - CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 - CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 - CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 - CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 - CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 - CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 - CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 - CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 - CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 - CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 - CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 - CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 - CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 - CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 - CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 - CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 - CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 - CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 - CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 - CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 - CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 - CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 - CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 - CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 - CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 - CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 - CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 - CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 - CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 - CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 - CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 - CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 - CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 - CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 - CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 - CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 - CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 - CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 - CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 - CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 - CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 - CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 - CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 - CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 - CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 - CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 - CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 - CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 - CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 - CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 - CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 - CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 - CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 - CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 - CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 - CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 - CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 - CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 - CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 - CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 - CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 - CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 - CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 - CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 - CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 - CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 - CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 - CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 - CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 - CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 - CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 - CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 - CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 - CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 - CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 - CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 - CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 - CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 - CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 - CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 - CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 - CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 - CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 - CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 - CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 - CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 - CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 - CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 - CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 - CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 - CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 - CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 - CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 - CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 - CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 - CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 - CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 - CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 - CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 - CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 - CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 - CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 - CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 - CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 - CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 - CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 - CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 - CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 - CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 - CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 - CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 - CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 - CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 - CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 - CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 - CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 - CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 - CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 - CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 - CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 - CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 - CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 - CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 - CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 - CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 - CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 - CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 - CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 - CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 - CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 - CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 - CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 - CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 - CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 - CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 - CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 - CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 - CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 - CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 - CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 - CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 - CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 - CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 - CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 - CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 - CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 - CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 - CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 - CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 - CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 - CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 - CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 - CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 - CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 - CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 - CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 - CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 - CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 - CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 - CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 - CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 - CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 - CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 - CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 - CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 - CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 - CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 - CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 - CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 - CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 - CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 - CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 - CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 - CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 - CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 - CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 - CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 - CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 - CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 - CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 - CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 - CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 - CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 - CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 - CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 - CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 - CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 - CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 - CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 - CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 - CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 - CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 - CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 - CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 - CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 - CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 - CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 - CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 - CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 - CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 - CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 - CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 - CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 - CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 - CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 - CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 - CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 - CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 - CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 - CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 - CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 - CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 - CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 - CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 - CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 - CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 - CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 - CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 - CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 - CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 - CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 - CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 - CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 - CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 - CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 - CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 - CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 - CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 - CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 - CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 - CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 - CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 - CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 - CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 - CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 - CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 - CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 - CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 - CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 - CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 - CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 - CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 - CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 - CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 - CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 - CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 - CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 - CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 - CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 - CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 - CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 - CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 - CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 - CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 - CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 - CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 - CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 - CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 - CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 - CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 - CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 - CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 - CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 - CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 - CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 - CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 - CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 - CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 - CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 - CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 - CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 - CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 - CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 - CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 - CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 - CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 - CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 - CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 - CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 - CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 - CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 - CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 - CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 - CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 - CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 - CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 - CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 - CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 - CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 - CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 - CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 - CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 - CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 - CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 - CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 - CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 - CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 - CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 - CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 - CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 - CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 - CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 - CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 - CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 - CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 - CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 - CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 - CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 - CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 - CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 - CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 - CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 - CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 - CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 - CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 - CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 - CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 - CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 - CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 - CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 - CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 - CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 - CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 - CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 - CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 - CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 - CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 - CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 - CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 - CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 - CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 - CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 - CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 - CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 - CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 - CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 - CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 - CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 - CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 - CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 - CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 - CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 - CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 - CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 - CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 - CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 - CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 - CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 - CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 - CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 - CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 - CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 - CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 - CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 - CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 - CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 - CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 - CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 - CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 - CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 - CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 - CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 - CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 - CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 - CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 - CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 - CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 - CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 - CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 - CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 - CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 - CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 - CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 - CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 - CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 - CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 - CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 - CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 - CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 - CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 - CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 - CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 - CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 - CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 - CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 - CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 - CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 - CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 - CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 - CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 - CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 - CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 - CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 - CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 - CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 - CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 - CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 - CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 - CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 - CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 - CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 - CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 - CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 - CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 - CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 - CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 - CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 - CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 - CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 - CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 - CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 - CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 - CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 - CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 - CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 - CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 - CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 - CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 - CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 - CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 - CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 - CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 - CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 - CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 - CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 - CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 - CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 - CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 - CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 - CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 - CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 - CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 - CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 - CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 - CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 - CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 - CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 - CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 - CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 - CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 - CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 - CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 - CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 - CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 - CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 - CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 - CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 - CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 - CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 - CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 - CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 - CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 - CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 - CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 - CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 - CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 - CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 - CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 - CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 - CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 - CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 - CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 - CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 - CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 - CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 - CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 - CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 - CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 - CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 - CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 - CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 - CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 - CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 - CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 - CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 - CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 - CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 - CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 - CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 - CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 - CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 - CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 - CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 - CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 - CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 - CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 - CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 - CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 - CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 - CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 - CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 - CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 - CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 - CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 - CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 - CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 - CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 - CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 - CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 - CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 - CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 - CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 - CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 - CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 - CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 - CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 - CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 - CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 - CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 - CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 - CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 - CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 - CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 - CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 - CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 - CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 - CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 - CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 - CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 - CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 - CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 - CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 - CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 -} cgc_pll_mul_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_clock_init(void); // Used internally by BSP - -#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD -void bsp_clock_freq_var_init(void); // Used internally by BSP - -#endif - -#if BSP_TZ_SECURE_BUILD -void r_bsp_clock_up2025-08-12_callback_set(bsp_clock_up2025-08-12_callback_t p_callback, - bsp_clock_up2025-08-12_callback_args_t * p_callback_memory); - -#endif - -/* Used internally by CGC */ - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE -void bsp_prv_operating_mode_set(uint8_t operating_mode); - -#endif - -#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED -uint32_t bsp_prv_power_change_mstp_set(void); -void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); - -#endif - -void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); - -#if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); - -#else -void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); -uint32_t bsp_prv_clock_source_get(void); - -#endif - -/* RTC Initialization */ -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR -void R_BSP_Init_RTC(void); - -#endif - -#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE -bool bsp_prv_rtc_register_clock_set(bool enable); - -#endif - -#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE -bool bsp_prv_clock_prepare_pre_sleep(void); -void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); - -#endif - -/* The public function is used to get state or initialize the sub-clock. */ -#if BSP_FEATURE_RTC_IS_IRTC -fsp_err_t R_BSP_SubclockStatusGet(); -fsp_err_t R_BSP_SubclockInitialize(); - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_common.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_common.h deleted file mode 100644 index 6214a694b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_common.h +++ /dev/null @@ -1,623 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_COMMON_H -#define BSP_COMMON_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include -#include - -/* Different compiler support. */ -#include "../../inc/api/fsp_common_api.h" -#include "bsp_compiler_support.h" - -/* BSP TFU Includes. */ -#include "../../src/bsp/mcu/all/bsp_tfu.h" - -#include "../../src/bsp/mcu/all/bsp_sdram.h" - -/* BSP MMF Includes. */ -#include "../../src/bsp/mcu/all/bsp_mmf.h" - -#include "bsp_cfg.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** Used to signify that an ELC event is not able to be used as an interrupt. */ -#define BSP_IRQ_DISABLED (0xFFU) - -/* Version of this module's code and API. */ - -#if 1 == BSP_CFG_RTOS /* ThreadX */ - #include "tx_user.h" - #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) - #include "tx_port.h" - #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); - #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); - #else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE - #endif -#else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE -#endif - -/** Macro that can be defined in order to enable logging in FSP modules. */ -#ifndef FSP_LOG_PRINT - #define FSP_LOG_PRINT(X) -#endif - -/** Macro to log and return error without an assertion. */ -#ifndef FSP_RETURN - - #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ - return err; -#endif - -/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in - * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ -#if (1 == BSP_CFG_ASSERT) - - #ifndef FSP_ERROR_LOG - #define FSP_ERROR_LOG(err) \ - fsp_error_log((err), __FILE__, __LINE__); - #endif -#else - - #define FSP_ERROR_LOG(err) -#endif - -/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP - * functions. */ -#if (3 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) -#elif (2 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) {assert(a);} -#else - #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) -#endif // ifndef FSP_ASSERT - -/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used - * to identify runtime errors in FSP functions. */ - -#define FSP_ERROR_RETURN(a, err) \ - { \ - if ((a)) \ - { \ - (void) 0; /* Do nothing */ \ - } \ - else \ - { \ - FSP_ERROR_LOG(err); \ - return err; \ - } \ - } - -/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register up2025-08-12s. - * This macro can be redefined to add a timeout if necessary. */ -#ifndef FSP_HARDWARE_REGISTER_WAIT - #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} -#endif - -#ifndef FSP_REGISTER_READ - -/* Read a register and discard the result. */ - #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); -#endif - -/**************************************************************** - * - * This check is performed to select suitable ASM API with respect to core - * - * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so - * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ - -#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) - #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) - #endif -#else - #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #endif - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) -#endif - -/* This macro defines a variable for saving previous mask value */ -#ifndef FSP_CRITICAL_SECTION_DEFINE - - #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U -#endif - -/* These macros abstract methods to save and restore the interrupt state for different architectures. */ -#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK - #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) -#else - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI - #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ - (8U - __NVIC_PRIO_BITS))) -#endif - -/** This macro temporarily saves the current interrupt state and disables interrupts. */ -#ifndef FSP_CRITICAL_SECTION_ENTER - #define FSP_CRITICAL_SECTION_ENTER \ - old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ - FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) -#endif - -/** This macro restores the previously saved interrupt state, reenabling interrupts. */ -#ifndef FSP_CRITICAL_SECTION_EXIT - #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) -#endif - -/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ -#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) - -/** Used to signify that the requested IRQ vector is not defined in this system. */ -#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) - -/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ -#if (BSP_CFG_MCU_PART_SERIES == 8) - #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) -#else - #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) -#endif - -/* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE - #define FSP_PRIV_TZ_USE_SECURE_REGS (1) -#else - #define FSP_PRIV_TZ_USE_SECURE_REGS (0) -#endif - -/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ -#if BSP_CFG_EARLY_INIT - #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) -#else - #define BSP_SECTION_EARLY_INIT -#endif - -#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 -BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); - -#endif - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/* - * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register - * from the secure application using the provided non-secure callable functions. - */ - #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) - #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) - #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) -#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/*******************************************************************************************************************//** - * Read a non-secure 8-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) -{ - p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 16-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) -{ - p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 32-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) -{ - p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/* - * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register - * using the non-secure aliased address. - */ - #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) - #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) - #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) -#else - #define FSP_STYPE3_REG8_READ(X, S) (X) - #define FSP_STYPE3_REG16_READ(X, S) (X) - #define FSP_STYPE3_REG32_READ(X, S) (X) -#endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Different warm start entry locations in the BSP. */ -typedef enum e_bsp_warm_start_event -{ - BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. - BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. - BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up -} bsp_warm_start_event_t; - -/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ -typedef enum e_fsp_priv_clock -{ - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_PCLKE = 20, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, - FSP_PRIV_CLOCK_CPUCLK = 32, -} fsp_priv_clock_t; - -/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ -typedef enum e_fsp_priv_source_clock -{ - FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator - FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator - FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator - FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator - FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator - FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output - FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output - FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output - FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output - FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output - FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output - FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output - FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output -} fsp_priv_source_clock_t; - -typedef struct st_bsp_unique_id -{ - union - { - uint32_t unique_id_words[4]; - uint8_t unique_id_bytes[16]; - }; -} bsp_unique_id_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); - -/*********************************************************************************************************************** - * Global variables (defined in other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Return active interrupt vector number value - * - * @return Active interrupt vector number value - **********************************************************************************************************************/ -__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) -{ - xPSR_Type xpsr_value; - xpsr_value.w = __get_xPSR(); - - return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); -} - -/*******************************************************************************************************************//** - * Gets the frequency of a system clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) -{ -#if !BSP_FEATURE_CGC_REGISTER_SET_B - uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; - - #if BSP_FEATURE_CGC_HAS_CPUCLK - if (FSP_PRIV_CLOCK_CPUCLK == clock) - { - return SystemCoreClock; - } - - /* Get CPUCLK divisor */ - uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; - - /* Determine if either divisor is a multiple of 3 */ - if ((cpuclk_div | clock_div) & 8U) - { - /* Convert divisor settings to their actual values */ - cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); - clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); - - /* Calculate clock with multiplication and division instead of shifting */ - return (SystemCoreClock * cpuclk_div) / clock_div; - } - else - { - return (SystemCoreClock << cpuclk_div) >> clock_div; - } - - #else - uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; - - return (SystemCoreClock << iclk_div) >> clock_div; - #endif -#else - FSP_PARAMETER_NOT_USED(clock); - - return SystemCoreClock; -#endif -} - -/*******************************************************************************************************************//** - * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). - * - * @return Clock Divider - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) -{ - if (2U >= ckdivcr) - { - - /* clock_div: - * - Clock Divided by 1: 0 - * - Clock Divided by 2: 1 - * - Clock Divided by 4: 2 - */ - return 1U << ckdivcr; - } - else if (3U == ckdivcr) - { - - /* Clock Divided by 6 */ - return 6U; - } - else if (4U == ckdivcr) - { - - /* Clock Divided by 8 */ - return 8U; - } - else if (5U == ckdivcr) - { - - /* Clock Divided by 3 */ - return 3U; - } - else if (6U == ckdivcr) - { - - /* Clock Divided by 5 */ - return 5; - } - else if (7U == ckdivcr) - { - - /* Clock Divided by 10 */ - return 10; - } - else - { - /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ - } - - /* Clock Divided by 16 */ - return 16U; -} - -#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI/SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) -{ - uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; - uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; - - return R_BSP_SourceClockHzGet(scispicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) -{ - uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = - (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> - R_SYSTEM_SPICKCR_CKSEL_Pos); - - return R_BSP_SourceClockHzGet(spicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SCI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) -{ - uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = - (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> - R_SYSTEM_SCICKCR_SCICKSEL_Pos); - - return R_BSP_SourceClockHzGet(scicksel) / clock_div; -} - -#endif - -/*******************************************************************************************************************//** - * Get unique ID for this device. - * - * @return A pointer to the unique identifier structure - **********************************************************************************************************************/ -__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) -{ -#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 - - return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); -#else - - return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; -#endif -} - -/*******************************************************************************************************************//** - * Disables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheDisable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 - - /* Writeback and flush cache when disabling - * MREF_INTERNAL_12 */ - if (R_CACHE->CCAWTA_b.WT) - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; - } - else - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; - } - - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #else - - /* Disable the C-Cache. */ - R_CACHE->CCACTL = 0U; - #endif -#endif -} - -/*******************************************************************************************************************//** - * Enables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheEnable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invali2025-08-12 the flash cache and wait until it is invali2025-08-12d. (See section 55.3.2.2 "Operation" of the Flash Cache - * in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 - - /* Configure the C-Cache line size. */ - R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; - #else - - /* Check that no flush or writeback are ongoing before enabling - * MREF_INTERNAL_13 */ - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #endif - - /* Enable the C-Cache. */ - R_CACHE->CCACTL = 1U; -#endif -} - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -#if (1 == BSP_CFG_ASSERT) - -/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ -void fsp_error_log(fsp_err_t err, const char * file, int32_t line); - -#endif - -/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will - * alert the user of the error. The user can override this default behavior by defining their own - * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. - */ -#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) - - #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_compiler_support.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_compiler_support.h deleted file mode 100644 index 39f752c3c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_compiler_support.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_COMPILER_SUPPORT_H - #define BSP_COMPILER_SUPPORT_H - - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - #include "arm_cmse.h" - #endif - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - #if defined(__ARMCC_VERSION) /* AC6 compiler */ - -/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load - * memory (ROM) is reserved unnecessarily. */ - #define BSP_UNINIT_SECTION_PREFIX ".bss" - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__GNUC__) /* GCC compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__ICCARM__) /* IAR compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP "HEAP" - #endif - #define BSP_DONT_REMOVE __root - #define BSP_ATTRIBUTE_STACKLESS __stackless - #define BSP_FORCE_INLINE _Pragma("inline=forced") - #endif - - #ifndef BSP_SECTION_STACK - #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" - #endif - #ifndef BSP_SECTION_FLASH_GAP - #define BSP_SECTION_FLASH_GAP - #endif - #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" - #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - #define BSP_SECTION_ROM_REGISTERS ".rom_registers" - #define BSP_SECTION_ID_CODE ".id_code" - -/* Compiler neutral macros. */ - #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - - #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) - - #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED - - #define BSP_WEAK_REFERENCE __attribute__((weak)) - -/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ - #define BSP_STACK_ALIGNMENT (8) - -/*********************************************************************************************************************** - * TrustZone definitions - **********************************************************************************************************************/ - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) - #if defined(__ICCARM__) /* IAR compiler */ - #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call - #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry - #else - #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) - #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) - #endif - #else - #define BSP_CMSE_NONSECURE_CALL - #define BSP_CMSE_NONSECURE_ENTRY - #endif - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/** @} (end of addtogroup BSP_MCU) */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_delay.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_delay.h deleted file mode 100644 index 94a13ccff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_delay.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_DELAY_H -#define BSP_DELAY_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "bsp_compiler_support.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The number of cycles required per software delay loop. */ -#ifndef BSP_DELAY_LOOP_CYCLES - #if defined(RENESAS_CORTEX_M85) - -/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for - * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in - * this case. */ - #if defined(__ICCARM__) - #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) - #else - #define BSP_DELAY_LOOP_CYCLES (1) - #endif - #else - #define BSP_DELAY_LOOP_CYCLES (4) - #endif -#endif - -/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle - * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures - * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count - * of 0. */ -#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) - -/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ -typedef enum -{ - BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds - BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds - BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds -} bsp_delay_units_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_elc.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_elc.h deleted file mode 100644 index 9a2207791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_elc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_ELC_H -#define BSP_ELC_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU_RA6M5 - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* UNCRUSTIFY-OFF */ - -/** Sources of event signals to be linked to other peripherals or the CPU - * @note This list is device specific. - * */ -typedef enum e_elc_event_ra6m5 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end - ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end - ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end - ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end - ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end - ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete - ELC_EVENT_DTC_END = (0x02A), // DTC transfer end - ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode - ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt - ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt - ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry - ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B - ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt - ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A - ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B - ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt - ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A - ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B - ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt - ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A - ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B - ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt - ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A - ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt - ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt - ELC_EVENT_CAN_GLERR = (0x05A), // Global error - ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 - ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 - ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 - ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 - ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 - ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 - ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 - ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 - ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt - ELC_EVENT_CAN0_CHERR = (0x064), // Channel error - ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt - ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request - ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt - ELC_EVENT_CAN1_CHERR = (0x068), // Channel error - ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt - ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request - ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x073), // Receive data full - ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x075), // Transmit end - ELC_EVENT_IIC0_ERI = (0x076), // Transfer error - ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x078), // Receive data full - ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x080), // Transfer error - ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request - ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full - ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt - ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt - ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt - ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow - ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow - ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow - ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow - ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch - ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt - ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x180), // Receive data full - ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x182), // Transmit end - ELC_EVENT_SCI0_ERI = (0x183), // Receive error - ELC_EVENT_SCI0_AM = (0x184), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x186), // Receive data full - ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x188), // Transmit end - ELC_EVENT_SCI1_ERI = (0x189), // Receive error - ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI2_ERI = (0x18F), // Receive error - ELC_EVENT_SCI3_RXI = (0x192), // Receive data full - ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x194), // Transmit end - ELC_EVENT_SCI3_ERI = (0x195), // Receive error - ELC_EVENT_SCI3_AM = (0x196), // Address match event - ELC_EVENT_SCI4_RXI = (0x198), // Receive data full - ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI4_ERI = (0x19B), // Receive error - ELC_EVENT_SCI4_AM = (0x19C), // Address match event - ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI5_AM = (0x1A2), // Address match event - ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI6_AM = (0x1A8), // Address match event - ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI7_AM = (0x1AE), // Address match event - ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error - ELC_EVENT_SCI8_AM = (0x1B4), // Address match event - ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error - ELC_EVENT_SCI9_AM = (0x1BA), // Address match event - ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle - ELC_EVENT_SPI0_ERI = (0x1C7), // Error - ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle - ELC_EVENT_SPI1_ERI = (0x1CC), // Error - ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event - ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error - ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error - ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error - ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt - ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt - ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt -} elc_event_t; - -#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) - -#define ELC_PERIPHERAL_NUM (19U) -#define BSP_OVERRIDE_ELC_PERIPHERAL_T -/** Possible peripherals to be linked to event signals - * @note This list is device specific. - * */ -typedef enum e_elc_peripheral -{ - ELC_PERIPHERAL_GPT_A = (0), - ELC_PERIPHERAL_GPT_B = (1), - ELC_PERIPHERAL_GPT_C = (2), - ELC_PERIPHERAL_GPT_D = (3), - ELC_PERIPHERAL_GPT_E = (4), - ELC_PERIPHERAL_GPT_F = (5), - ELC_PERIPHERAL_GPT_G = (6), - ELC_PERIPHERAL_GPT_H = (7), - ELC_PERIPHERAL_ADC0 = (8), - ELC_PERIPHERAL_ADC0_B = (9), - ELC_PERIPHERAL_ADC1 = (10), - ELC_PERIPHERAL_ADC1_B = (11), - ELC_PERIPHERAL_DAC0 = (12), - ELC_PERIPHERAL_DAC1 = (13), - ELC_PERIPHERAL_IOPORT1 = (14), - ELC_PERIPHERAL_IOPORT2 = (15), - ELC_PERIPHERAL_IOPORT3 = (16), - ELC_PERIPHERAL_IOPORT4 = (17), - ELC_PERIPHERAL_CTSU = (18) -} elc_peripheral_t; - -/** Positions of event link set registers (ELSRs) available on this MCU */ -#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) - -/* UNCRUSTIFY-ON */ -/** @} (end addtogroup BSP_MCU_RA6M5) */ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_exceptions.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_exceptions.h deleted file mode 100644 index f388be329..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_exceptions.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_EXCEPTIONS_H - #define BSP_EXCEPTIONS_H - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ -typedef enum IRQn -{ - Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ -} IRQn_Type; - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_feature.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_feature.h deleted file mode 100644 index 29f6b43f1..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_feature.h +++ /dev/null @@ -1,588 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_FEATURE_H -#define BSP_FEATURE_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "bsp_peripheral.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ -#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) -#if (BSP_CFG_XTAL_HZ >= (20000000)) - #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (16000000)) - #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (8000000)) - #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#else - #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#endif - -// *UNCRUSTIFY-OFF* - -#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. -#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. -#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0xFFFFUL) // Create the mask for the valid calibration data provided by TSCDR. -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. -#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FFUL) // Mask of available channels in ADC unit 0. -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007UL) // Mask of available channels in ADC unit 1. -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. - -#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. -#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. -#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. -#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. - -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. -#define BSP_FEATURE_BSP_FLASH_CACHE (1UL) // Flash cache is present. -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. -#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. -#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1UL) // Indicates there is a separate clock for the CEC. -#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. -#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. -#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. -#define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. -#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. -#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. -#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0UL) // Indicates there is a separate clock for the I3C. -#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. -#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. -#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. -#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. -#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. -#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. -#define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. -#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. -#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. -#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. -#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. -#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. -#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. -#define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. -#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. -#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. -#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. -#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. -#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. -#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. -#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. -#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. -#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. -#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. - -#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. -#define BSP_FEATURE_CANFD_LITE (0UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. -#define BSP_FEATURE_CANFD_NUM_CHANNELS (2UL) // Number of CANFD channels per CANFD peripheral instance. -#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. - -#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. -#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. -#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. -#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. -#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. -#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. -#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. -#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. -#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. -#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. -#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. -#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. -#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. -#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. -#define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. -#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. -#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. -#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. -#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000UL) // Maximum input frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. -#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. -#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000UL) // PLL VCO maximum frequency. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. -#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. -#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. -#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. -#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. - -#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. -#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. -#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. - -#define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA (1UL) // RSA support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1UL) // RSA support with key-wrapping is available. - -#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. -#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. - -#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. -#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. -#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. -#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. -#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. - -#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) -#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. - -#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. -#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. - -#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. - -#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. - -#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. - -#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. - -#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. - -#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1UL) // Number of available ethernet PHYs. -#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. - -#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. -#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. -#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. -#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. -#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. -#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. -#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). -#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). -#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. - -#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. -#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. -#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. - -#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x03FFUL) // Mask of channels that support event count input (has GTUPSR register). -#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. -#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. -#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x03FFUL) // Mask of channels that support dead time control. -#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. -#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. -#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. - -#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. -#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. -#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. -#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. -#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. -#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. -#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. -#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FF0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. - -#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. - -#define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. -#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. - -#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. -#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. - -#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. -#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. -#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. -#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. -#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. -#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. -#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. -#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. -#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. -#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. - -#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. -#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. -#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. -#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. -#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. -#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. -#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. -#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. - -#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. - -#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000UL) // Start address of the CS0 memory mapped region for OSPI. -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000UL) // Start address of the CS1 memory mapped region for OSPI. - -#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. -#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. - -#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. - -#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. -#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. -#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RISP_E11A. -#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. -#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. -#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. -#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. -#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. -#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. -#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. -#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. - -#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. -#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. -#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. -#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. -#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. -#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. - -#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x03F9UL) // Mask of channels with data compare match (DCCR) available. -#define BSP_FEATURE_SCI_CHANNELS (0x03FFUL) // Mask of available SCI channels. -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. -#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. -#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x06UL) // Mask of channels that can support LIN. -#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x06UL) // List of channels that do not support ABCSE functionality. -#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9UL) // Mask of channels which support CTS external pins. -#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x03F9UL) // Mask of channels which support the UART FIFO. -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. -#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. - -#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. - -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. - -#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. - -#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. -#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. -#define BSP_FEATURE_SPI_MAX_CHANNEL (2UL) // Number of available SPI channels. -#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. - -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. - -#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. - -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. - -#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. - -#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. - -#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) -#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. -#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. -#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. - -#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) -#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. -#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. - -#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) -#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. -#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. -#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. -#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. -#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. -#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. -#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. -#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. -#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. -#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_group_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_group_irq.h deleted file mode 100644 index 5aede0736..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_group_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GROUP_IRQ_H -#define BSP_GROUP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#ifndef BSP_OVERRIDE_GROUP_IRQ_T - -/** Which interrupts can have callbacks registered. */ -typedef enum e_bsp_grp_irq -{ - BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred - BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred - BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt - BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt - BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt - BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected - BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt - BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error - BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error - BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error - BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error - BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error - BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error - BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error -} bsp_grp_irq_t; - -#endif - -/* Callback type. */ -typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_group_interrupt_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_guard.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_guard.h deleted file mode 100644 index 100463ded..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_guard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GUARD_H -#define BSP_GUARD_H - -#include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUp2025-08-12CallbackSet(bsp_clock_up2025-08-12_callback_t p_callback, - bsp_clock_up2025-08-12_callback_args_t * p_callback_memory); - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_io.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_io.h deleted file mode 100644 index 418c75380..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_io.h +++ /dev/null @@ -1,465 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @defgroup BSP_IO BSP I/O access - * @ingroup RENESAS_COMMON - * @brief This module provides basic read/write access to port pins. - * - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_IO_H -#define BSP_IO_H - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) -#define BSP_IO_PRV_8BIT_MASK (0xFF) -#define BSP_IO_PWPR_B0WI_OFFSET (7U) -#define BSP_IO_PWPR_PFSWE_OFFSET (6U) -#define BSP_IO_PFS_PDR_OUTPUT (4U) -#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Levels that can be set and read for individual pins */ -typedef enum e_bsp_io_level -{ - BSP_IO_LEVEL_LOW = 0, ///< Low - BSP_IO_LEVEL_HIGH ///< High -} bsp_io_level_t; - -/** Direction of individual pins */ -typedef enum e_bsp_io_dir -{ - BSP_IO_DIRECTION_INPUT = 0, ///< Input - BSP_IO_DIRECTION_OUTPUT ///< Output -} bsp_io_direction_t; - -/** Superset list of all possible IO ports. */ -typedef enum e_bsp_io_port -{ - BSP_IO_PORT_00 = 0x0000, ///< IO port 0 - BSP_IO_PORT_01 = 0x0100, ///< IO port 1 - BSP_IO_PORT_02 = 0x0200, ///< IO port 2 - BSP_IO_PORT_03 = 0x0300, ///< IO port 3 - BSP_IO_PORT_04 = 0x0400, ///< IO port 4 - BSP_IO_PORT_05 = 0x0500, ///< IO port 5 - BSP_IO_PORT_06 = 0x0600, ///< IO port 6 - BSP_IO_PORT_07 = 0x0700, ///< IO port 7 - BSP_IO_PORT_08 = 0x0800, ///< IO port 8 - BSP_IO_PORT_09 = 0x0900, ///< IO port 9 - BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 - BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 - BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 - BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 - BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 -} bsp_io_port_t; - -/** Superset list of all possible IO port pins. */ -typedef enum e_bsp_io_port_pin_t -{ - BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 - BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port -} bsp_io_port_pin_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern volatile uint32_t g_protect_pfswe_counter; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Read the current input level of the pin. - * - * @param[in] pin The pin - * - * @retval Current input level - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) -{ - /* Read pin level. */ - return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; -} - -/*******************************************************************************************************************//** - * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS - * protection using R_BSP_PinAccessEnable() before calling this function. - * - * @param[in] pin The pin - * @param[in] level The level - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) -{ - /* Clear PMR, ASEL, ISEL and PODR bits. */ - uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; - pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; - - /* Set output level and pin direction to output. */ - uint32_t lvl = ((uint32_t) level | pfs_bits); -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); -#endif -} - -/*******************************************************************************************************************//** - * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling - * this function. - * - * @param[in] pin The pin - * @param[in] cfg Configuration for the pin (PmnPFS register setting) - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) -{ - /* Configure a pin. */ -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; -#endif -} - -/*******************************************************************************************************************//** - * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur - * via multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessEnable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** If this is first entry then allow writing of PFS. */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #endif - } - - /** Increment the protect counter */ - g_protect_pfswe_counter++; - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/*******************************************************************************************************************//** - * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via - * multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessDisable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** Is it safe to disable PFS register? */ - if (0 != g_protect_pfswe_counter) - { - /* Decrement the protect counter */ - g_protect_pfswe_counter--; - } - - /** Is it safe to disable writing of PFS? */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled - #endif - } - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/** @} (end addtogroup BSP_IO) */ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_irq.h deleted file mode 100644 index ad971f32e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_irq.h +++ /dev/null @@ -1,238 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_IRQ_H -#define BSP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @brief Sets the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @param[in] p_context ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - gp_renesas_isr_context[irq] = p_context; -} - -/*******************************************************************************************************************//** - * @brief Finds the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @return ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - return gp_renesas_isr_context[irq]; -} - -#if BSP_CFG_INLINE_IRQ_FUNCTIONS - - #if BSP_FEATURE_ICU_HAS_IELSR - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit - * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) -{ - /* Clear the IR bit in the selected IELSR register. */ - R_ICU->IELSR_b[irq].IR = 0U; - - /* Read back the IELSR register to ensure that the IR bit is cleared. - * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ - FSP_REGISTER_READ(R_ICU->IELSR[irq]); -} - - #endif - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) -{ - #if BSP_FEATURE_ICU_HAS_IELSR - - /* Clear the IR bit in the selected IELSR register. */ - R_BSP_IrqStatusClear(irq); - - /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ - __DMB(); - #endif - - /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context. - * - * @param[in] irq The IRQ to configure. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions - * every time a priority is configured in the NVIC. */ - #if (4U == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (33 == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (23 == __CORTEX_M) - NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); - #else - NVIC_SetPriority(irq, priority); - #endif - - /* Store the context. The context is recovered in the ISR. */ - R_FSP_IsrContextSet(irq, p_context); -} - -/*******************************************************************************************************************//** - * Enable the IRQ in the NVIC (Without clearing the pending bit). - * - * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex - * Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) -{ - /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions - * every time an interrupt is enabled in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - - __COMPILER_BARRIER(); - NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - __COMPILER_BARRIER(); -} - -/*******************************************************************************************************************//** - * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed - * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) -{ - /* Clear pending interrupts in the ICU and NVIC. */ - R_BSP_IrqClearPending(irq); - - /* Enable the IRQ in the NVIC. */ - R_BSP_IrqEnableNoClear(irq); -} - -/*******************************************************************************************************************//** - * Disables interrupts in the NVIC. - * - * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) -{ - /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - - __DSB(); - __ISB(); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. - * - * @param[in] irq Interrupt number. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - R_BSP_IrqCfg(irq, priority, p_context); - R_BSP_IrqEnable(irq); -} - -#else - #if BSP_FEATURE_ICU_HAS_IELSR -void R_BSP_IrqStatusClear(IRQn_Type irq); - - #endif -void R_BSP_IrqClearPending(IRQn_Type irq); -void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); -void R_BSP_IrqEnableNoClear(IRQn_Type const irq); -void R_BSP_IrqEnable(IRQn_Type const irq); -void R_BSP_IrqDisable(IRQn_Type const irq); -void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); - -#endif - -/*******************************************************************************************************************//** - * @internal - * @addtogroup BSP_MCU_PRV Internal BSP Documentation - * @ingroup RENESAS_INTERNAL - * @{ - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_irq_cfg(void); // Used internally by BSP - -/** @} (end addtogroup BSP_MCU_PRV) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_macl.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_macl.h deleted file mode 100644 index 416228d5c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_macl.h +++ /dev/null @@ -1,164 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_MACL -#define RENESAS_MACL - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include -#include "bsp_api.h" - -#if BSP_FEATURE_MACL_SUPPORTED - #if __has_include("arm_math_types.h") - -/* Ignore certain math warnings in ARM CMSIS DSP headers */ - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wsign-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" - #elif defined(__GNUC__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wfloat-conversion" - #endif - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_suppress=Pe223 - #endif - - #include "arm_math_types.h" - #include "dsp/basic_math_functions.h" - #include "dsp/matrix_functions.h" - #include "dsp/filtering_functions.h" - #include "dsp/support_functions.h" - #include "dsp/fast_math_functions.h" - - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_default=Pe223 - #endif - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - #pragma GCC diagnostic pop - #endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MACL - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Common macro used by MACL */ - #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) - #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) - - #define BSP_MACL_SHIFT_SIGN (0x80) - #define BSP_MACL_SHIFT_1_BIT (1U) - #define BSP_MACL_SHIFT_30_BIT (30U) - #define BSP_MACL_SHIFT_31_BIT (31U) - #define BSP_MACL_SHIFT_32_BIT (32U) - - #define BSP_MACL_32_BIT (32U) - - #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 - #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 - - #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 - #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 - - #define BSP_MACL_CLEAR_MULR_REG (0x0U) - - #define BSP_MACL_POSITIVE_NUM (0U) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, - const arm_matrix_instance_q31 * p_src_b, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); -void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, - q31_t scale_fract, - int32_t shift, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); -void R_BSP_MaclConvQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); -arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst, - uint32_t first_idx, - uint32_t num_points); - -void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); - -void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - q31_t * p_scratch_in, - uint32_t block_size); - -void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); - -/******************************************************************************************************************//** - * @} (end addtogroup BSP_MACL) - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - - #endif -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_api.h deleted file mode 100644 index 62e376705..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_api.h +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MCU_API_H -#define BSP_MCU_API_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -typedef struct st_bsp_event_info -{ - IRQn_Type irq; - elc_event_t event; -} bsp_event_info_t; - -typedef enum e_bsp_clocks_octaclk_div -{ - BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 - BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 - BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 - BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 - BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 - BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 - BSP_CLOCKS_OCTACLK_DIV_5 ///< Divide OCTA source clock by 5 -} bsp_clocks_octaclk_div_t; - -typedef enum e_bsp_clocks_source -{ - BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. - BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. - BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. - BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. - BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. - BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. - BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. -} bsp_clocks_source_t; - -typedef struct st_bsp_octaclk_settings -{ - bsp_clocks_source_t source_clock; ///< OCTACLK source clock - bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider -} bsp_octaclk_settings_t; - -void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); -void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); -fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); -void R_BSP_OctaclkUp2025-08-12(bsp_octaclk_settings_t * p_octaclk_setting); -void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_pn_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index f13b34efa..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BG3CFP - #define BSP_MCU_FEATURE_SET ('B') - #define BSP_ROM_SIZE_BYTES (1572864) - #define BSP_RAM_SIZE_BYTES (524288) - #define BSP_DATA_FLASH_SIZE_BYTES (8192) - #define BSP_PACKAGE_LQFP - #define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_family_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_family_cfg.h deleted file mode 100644 index a4c302306..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,394 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - - #include "bsp_mcu_device_pn_cfg.h" - #include "bsp_mcu_device_cfg.h" - #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" - #include "bsp_clock_cfg.h" - #define BSP_MCU_GROUP_RA6M5 (1) - #define BSP_LOCO_HZ (32768) - #define BSP_MOCO_HZ (8000000) - #define BSP_SUB_CLOCK_HZ (32768) - #if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (16000000) - #elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - - #define BSP_CFG_FLL_ENABLE (0) - - #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) - #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) - - #if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (0) - #endif - - /* TrustZone Settings */ - #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) - #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) - #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - - /* CMSIS TrustZone Settings */ - #define SCB_CSR_AIRCR_INIT (1) - #define SCB_AIRCR_BFHFNMINS_VAL (0) - #define SCB_AIRCR_SYSRESETREQS_VAL (1) - #define SCB_AIRCR_PRIS_VAL (0) - #define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL - #define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL - #define FPU_FPCCR_TS_VAL (1U) -#endif - #define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL - #define FPU_FPCCR_CLRONRET_VAL (1) -#endif - - /* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE - #define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - - /* Type 1 Peripheral Security Attribution */ - - /* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - - /* Type 2 Peripheral Security Attribution */ - - /* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR - /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ -#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) -#define BSP_TZ_CFG_LVDSAR (0U) -#else -#define BSP_TZ_CFG_LVDSAR (3U) -#endif -#endif - - /* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif - /* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - - /* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFE0E402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - - /* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - - /* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - - /* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - - /* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - - /* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - - /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED - #define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - - /* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - - /* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ - #define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - - /* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR - #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - - /* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA - /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ - #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - - /* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA - #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif - /* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB - #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - - /* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK - #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - - - #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) - #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) - #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) - #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) - #define OFS_SEQ5 (1 << 28) | (1 << 30) - #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - - /* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) -#else - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - - #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - - /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ - #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - - /* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL - #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - - /* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 - #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif - /* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 - #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif - /* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 - #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif - /* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 - #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif - /* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 - #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif - /* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 - #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif - /* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 - #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif - /* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 - #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif - /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 - #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif - /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 - #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif - /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 - #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif - /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 - #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif - /* Security Attribution for Bank Select Register */ -#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL - #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT - #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_info.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_info.h deleted file mode 100644 index 53c1844b3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mcu_info.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup BSP_MCU - * @defgroup BSP_MCU_RA6M5 RA6M5 - * @includedoc config_bsp_ra6m5_fsp.html - * @{ - **********************************************************************************************************************/ - -/** @} (end defgroup BSP_MCU_RA6M5) */ - -#ifndef BSP_MCU_INFO_H -#define BSP_MCU_INFO_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* BSP MCU Specific Includes. */ -#include "bsp_elc.h" -#include "bsp_feature.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -typedef elc_event_t bsp_interrupt_event_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mmf.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mmf.h deleted file mode 100644 index 9b7f1b143..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_mmf.h +++ /dev/null @@ -1,141 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MMF_H -#define BSP_MMF_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MEMORY_MIRROR_REG_KEY (0xDBU) -#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes -#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) - -/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ -#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Enum for state of Memory Mirror Function. */ -typedef enum e_mmf_state -{ - MEMORY_MIRROR_DISABLED = 0, - MEMORY_MIRROR_ENABLED = 1, -} mmf_state_t; - -/** Status instance of Memory Mirror Function. */ -typedef struct st_mmf_status -{ - mmf_state_t mmf_state; // Current state of Memory Mirror Region. - uint32_t mmf_cur_addr; // Current address in register MMSFR. -} mmf_status_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Get the current status of Memory Mirror. - * - * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. - * - * @retval FSP_SUCCESS MMF status retrieved successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. - * - * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that variable for storing the status of MMF was provided. */ - if (NULL == p_mmf_status) - { - return FSP_ERR_ASSERTION; - } - #endif - - p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; - p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_mmf_status); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/*******************************************************************************************************************//** - * Set address for MMF region. - * - * @param[in] addr Address of memory region to be mirrored into MMF region. - * - * @retval FSP_SUCCESS Address is set successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. - * - * This function sets the memory address to be mirrored by MMF. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that requested address is in supported range and must align with 128 */ - if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) - { - return FSP_ERR_INVALID_ADDRESS; - } - #endif - - /* If MMF is enabled, disable MMF before updating the address register. - * For disabling MMF, write 0xDB00 to register MMEN. */ - if (1U == R_MMF->MMEN_b.EN) - { - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); - } - - R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); - - /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into - * MMF region. */ - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(addr); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif - -/** @} (end addtogroup BSP_MCU) */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_module_stop.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_module_stop.h deleted file mode 100644 index d7312cbe8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_module_stop.h +++ /dev/null @@ -1,371 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MODULE_H -#define BSP_MODULE_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* MSTPCRA is located in R_MSTP for Star devices. */ - #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) -#else - -/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ - #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) -#endif - -/*******************************************************************************************************************//** - * Cancels the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= \ - (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/*******************************************************************************************************************//** - * Enables the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/** @} (end addtogroup BSP_MCU) */ - -#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) - #else - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - - #if BSP_MCU_GROUP_RA2A2 - -/* RA2A2 has a combination of AGT and AGTW. - * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) - * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) - * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) - * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) - */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + \ - BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); - - #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #else - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t -#else - #if (2U == BSP_FEATURE_ELC_VERSION) - #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #elif BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ - (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - \ - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #endif -#endif - -#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); - -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t - -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t -#else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#if BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); -#else - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#endif -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t -#if (BSP_PERIPHERAL_DAC8_PRESENT) - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t -#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_pin_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_pin_cfg.h deleted file mode 100644 index bcca52bd5..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_pin_cfg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_PIN_CFG_H_ -#define BSP_PIN_CFG_H_ -#include "r_ioport.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - - -extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BG3CFP.pincfg */ - -void BSP_PinConfigSecurityInit(); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif /* BSP_PIN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_register_protection.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_register_protection.h deleted file mode 100644 index ca4b64c20..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_register_protection.h +++ /dev/null @@ -1,60 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_REGISTER_PROTECTION_H -#define BSP_REGISTER_PROTECTION_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/** The different types of registers that can be protected. */ -typedef enum e_bsp_reg_protect -{ - /** Enables writing to the registers related to the clock generation circuit. */ - BSP_REG_PROTECT_CGC = 0, - - /** Enables writing to the registers related to operating modes, low power consumption, and battery backup - * function. */ - BSP_REG_PROTECT_OM_LPC_BATT, - - /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, - * LVD2CR1, LVD2SR. */ - BSP_REG_PROTECT_LVD, - - /** Enables writing to the registers related to the security function. */ - BSP_REG_PROTECT_SAR, -} bsp_reg_protect_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_register_protect_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_sdram.h deleted file mode 100644 index 5ba56a638..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SDRAM_H -#define BSP_SDRAM_H - -#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_SdramInit(bool init_memory); -void R_BSP_SdramSelfRefreshEnable(void); -void R_BSP_SdramSelfRefreshDisable(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_security.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_security.h deleted file mode 100644 index 3ceb51f92..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_security.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SECURITY_H -#define BSP_SECURITY_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_NonSecureEnter(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_tfu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_tfu.h deleted file mode 100644 index 98b09caee..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/bsp_tfu.h +++ /dev/null @@ -1,218 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_TFU -#define RENESAS_TFU - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* Mathematical Functions includes. */ -#ifdef __cplusplus - #include -#else - #include -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TFU_SUPPORTED - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - - #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f - - #ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) - -/* No form of inline is available, it happens only when -std=c89, gnu89 and - * above are OK */ - #warning \ - "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ - -/* gnu89 semantics of inline and extern inline are essentially the exact - * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) - #endif - #endif - #elif __ICCARM__ - #define BSP_TFU_INLINE - #else - #error "Compiler not supported!" - #endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Calculates sine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Sine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __sinf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - return R_TFU->SCDT1; -} - -/*******************************************************************************************************************//** - * Calculates cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __cosf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read cos from R_TFU->SCDT1 */ - return R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates sine and cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * @param[out] sin Sine value of an angle. - * @param[out] cos Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - *sin = R_TFU->SCDT1; - - /* Read sin from R_TFU->SCDT1 */ - *cos = R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-Axis cordinate value. - * @param[in] x_cord X-Axis cordinate value. - * - * @retval Arc tangent for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) -{ - /* Set X-cordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-cordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - return R_TFU->ATDT1; -} - -/*******************************************************************************************************************//** - * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * - * @retval Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * @param[out] atan2 Arc tangent for given values. - * @param[out] hypot Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - *atan2 = R_TFU->ATDT1; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - - #if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) - #endif - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif /* RENESAS_TFU */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_common_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_common_api.h deleted file mode 100644 index 0a9983a9a..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_common_api.h +++ /dev/null @@ -1,380 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_COMMON_API_H -#define FSP_COMMON_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include -#include - -/* Includes FSP version macros. */ -#include "fsp_version.h" - -/*******************************************************************************************************************//** - * @ingroup RENESAS_COMMON - * @defgroup RENESAS_ERROR_CODES Common Error Codes - * All FSP modules share these common error codes. - * @{ - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing - * about using this implementation is that it does not take any extra RAM or ROM. */ - -#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) - -/** Determine if a C++ compiler is being used. - * If so, ensure that standard C is used to process the API information. */ -#if defined(__cplusplus) - #define FSP_CPP_HEADER extern "C" { - #define FSP_CPP_FOOTER } -#else - #define FSP_CPP_HEADER - #define FSP_CPP_FOOTER -#endif - -/** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically - * defined on the Secure side. */ -#define FSP_SECURE_ARGUMENT (NULL) - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Common error codes */ -typedef enum e_fsp_err -{ - FSP_SUCCESS = 0, - - FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed - FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location - FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter - FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist - FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode - FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API - FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open - FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy - FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h - FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked - FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP - FSP_ERR_OVERFLOW = 12, ///< Hardware overflow - FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow - FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration - FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result - FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason - FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met - FSP_ERR_ABORTED = 18, ///< An operation was aborted - FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled - FSP_ERR_TIMEOUT = 20, ///< Timeout error - FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied - FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied - FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation - FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed - FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed - FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made - FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition - FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU - FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state - FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed - FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed - FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete - FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found - FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback - FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer - FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed - - /* Start of RTOS only error codes */ - FSP_ERR_INTERNAL = 100, ///< Internal error - FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted - - /* Start of UART specific */ - FSP_ERR_FRAMING = 200, ///< Framing error occurs - FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects - FSP_ERR_PARITY = 202, ///< Parity error occurs - FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow - FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue - FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer - FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer - - /* Start of SPI specific */ - FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. - FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. - FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. - FSP_ERR_SPI_PARITY = 303, ///< Parity error. - FSP_ERR_OVERRUN = 304, ///< Overrun error. - - /* Start of CGC Specific */ - FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. - FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. - FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off - FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off - FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled - FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set - FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active - FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit - FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled - FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out - FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode - - /* Start of FLASH Specific */ - FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. - FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state - FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz - FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory - FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed - - /* Start of CAC Specific */ - FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate - - /* Start of IIRFA Specific */ - FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. - - /* Start of GLCD Specific */ - FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock - FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter - FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter - FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found - FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter - FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer - FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register up2025-08-12 - FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry - FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting - FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter - - /* Start of JPEG Specific */ - FSP_ERR_JPEG_ERR = 1100, ///< JPEG error - FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. - FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. - FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. - FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. - FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. - FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. - FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. - FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. - FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. - FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) - FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. - FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. - FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. - FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. - FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough - FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU - - /* Start of touch panel framework specific */ - FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed - - /* Start of IIRFA specific */ - FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected - FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected - - /* Start of IP specific */ - FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device - FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device - FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device - - /* Start of USB specific */ - FSP_ERR_USB_FAILED = 1500, - FSP_ERR_USB_BUSY = 1501, - FSP_ERR_USB_SIZE_SHORT = 1502, - FSP_ERR_USB_SIZE_OVER = 1503, - FSP_ERR_USB_NOT_OPEN = 1504, - FSP_ERR_USB_NOT_SUSPEND = 1505, - FSP_ERR_USB_PARAMETER = 1506, - - /* Start of Message framework specific */ - FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool - FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool - FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid - FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid - FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many - FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found - FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue - FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue - FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal - FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released - - /* Start of 2DG Driver specific */ - FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering - FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering - - /* Start of ETHER Driver specific */ - FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. - FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation - FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled - FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty - FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable - FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication - FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. - - /* Start of ETHER_PHY Driver specific */ - FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. - FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation - - /* Start of BYTEQ library specific */ - FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data - FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue - - /* Start of CTSU Driver specific */ - FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. - FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. - FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. - FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. - FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. - FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. - FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. - FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. - FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. - FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. - FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. - FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. - FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. - FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. - FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. - FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. - - /* Start of SDMMC specific */ - FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. - FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. - FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. - FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. - FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. - FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. - FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. - - /* Start of FX_IO specific */ - FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. - FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. - - /* Start of CAN specific */ - FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. - FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. - FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. - FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. - FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. - FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. - FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. - FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. - - /* Start of SF_WIFI Specific */ - FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. - FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. - FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed - FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode - FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. - FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. - FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point - FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error - FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter - FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value - FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result - FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured - FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure - FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure - FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error - - /* Start of SF_CELLULAR Specific */ - FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. - FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. - FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed - FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is upto2025-08-12 - FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed - FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. - FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. - FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed - - /* Start of SF_BLE specific */ - FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed - FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed - FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed - FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled - FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled - - /* Start of SF_BLE_ABS specific */ - FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. - FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. - - /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ - FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function - FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy - FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty - FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index - FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry - FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed - FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened - FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized - FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred - FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter - FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented - FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified - FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred - FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid - FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state - FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened - FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. - FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher - FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input 2025-08-12 is illegal. - FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. - - /* Start of Crypto RSIP specific (0x10100) */ - FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy - FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return - FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error - FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal - FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed - - /* Start of SF_CRYPTO specific */ - FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened - FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error - FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key - FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold - FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. - FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. - FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. - - /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. - * Refer to sf_cryoto_err.h for Crypto error codes. - */ - - /* Start of Sensor specific */ - FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. - FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. - FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. - - /* Start of COMMS specific */ - FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. -} fsp_err_t; - -/** @} */ - -/*********************************************************************************************************************** - * Function prototypes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_features.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_features.h deleted file mode 100644 index dd54197d7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_features.h +++ /dev/null @@ -1,297 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_FEATURES_H -#define FSP_FEATURES_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include - -/* Different compiler support. */ -#include "fsp_common_api.h" -#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Available modules. */ -typedef enum e_fsp_ip -{ - FSP_IP_CFLASH = 0, ///< Code Flash - FSP_IP_DFLASH = 1, ///< Data Flash - FSP_IP_RAM = 2, ///< RAM - FSP_IP_LVD = 3, ///< Low Voltage Detection - FSP_IP_CGC = 3, ///< Clock Generation Circuit - FSP_IP_LPM = 3, ///< Low Power Modes - FSP_IP_FCU = 4, ///< Flash Control Unit - FSP_IP_ICU = 6, ///< Interrupt Control Unit - FSP_IP_DMAC = 7, ///< DMA Controller - FSP_IP_DTC = 8, ///< Data Transfer Controller - FSP_IP_IOPORT = 9, ///< I/O Ports - FSP_IP_PFS = 10, ///< Pin Function Select - FSP_IP_ELC = 11, ///< Event Link Controller - FSP_IP_MPU = 13, ///< Memory Protection Unit - FSP_IP_MSTP = 14, ///< Module Stop - FSP_IP_MMF = 15, ///< Memory Mirror Function - FSP_IP_KEY = 16, ///< Key Interrupt Function - FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit - FSP_IP_DOC = 18, ///< Data Operation Circuit - FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator - FSP_IP_SCI = 20, ///< Serial Communications Interface - FSP_IP_IIC = 21, ///< I2C Bus Interface - FSP_IP_SPI = 22, ///< Serial Peripheral Interface - FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit - FSP_IP_SCE = 24, ///< Secure Cryptographic Engine - FSP_IP_SLCDC = 25, ///< Segment LCD Controller - FSP_IP_AES = 26, ///< Advanced Encryption Standard - FSP_IP_TRNG = 27, ///< True Random Number Generator - FSP_IP_FCACHE = 30, ///< Flash Cache - FSP_IP_SRAM = 31, ///< SRAM - FSP_IP_ADC = 32, ///< A/D Converter - FSP_IP_DAC = 33, ///< 12-Bit D/A Converter - FSP_IP_TSN = 34, ///< Temperature Sensor - FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit - FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator - FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator - FSP_IP_OPAMP = 38, ///< Operational Amplifier - FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter - FSP_IP_RTC = 40, ///< Real Time Clock - FSP_IP_WDT = 41, ///< Watch Dog Timer - FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer - FSP_IP_GPT = 43, ///< General PWM Timer - FSP_IP_POEG = 44, ///< Port Output Enable for GPT - FSP_IP_OPS = 45, ///< Output Phase Switch - FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer - FSP_IP_CAN = 48, ///< Controller Area Network - FSP_IP_IRDA = 49, ///< Infrared Data Association - FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface - FSP_IP_USBFS = 51, ///< USB Full Speed - FSP_IP_SDHI = 52, ///< SD/MMC Host Interface - FSP_IP_SRC = 53, ///< Sampling Rate Converter - FSP_IP_SSI = 54, ///< Serial Sound Interface - FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface - FSP_IP_ETHER = 64, ///< Ethernet MAC Controller - FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller - FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller - FSP_IP_PDC = 66, ///< Parallel Data Capture Unit - FSP_IP_GLCDC = 67, ///< Graphics LCD Controller - FSP_IP_DRW = 68, ///< 2D Drawing Engine - FSP_IP_JPEG = 69, ///< JPEG - FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter - FSP_IP_USBHS = 71, ///< USB High Speed - FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface - FSP_IP_CEC = 73, ///< HDMI CEC - FSP_IP_TFU = 74, ///< Trigonometric Function Unit - FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator - FSP_IP_CANFD = 76, ///< CAN-FD - FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT - FSP_IP_SAU = 78, ///< Serial Array Unit - FSP_IP_IICA = 79, ///< Serial Interface IICA - FSP_IP_UARTA = 80, ///< Serial Interface UARTA - FSP_IP_TAU = 81, ///< Timer Array Unit - FSP_IP_TML = 82, ///< 32-bit Interval Timer - FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator - FSP_IP_USBCC = 84, ///< USB Type-C Controller -} fsp_ip_t; - -/** Signals that can be mapped to an interrupt. */ -typedef enum e_fsp_signal -{ - FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH - FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH - FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END - FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B - FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A - FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B - FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ - FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ - FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A - FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B - FSP_SIGNAL_AGT_INT, ///< AGT INT - FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR - FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END - FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW - FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR - FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX - FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX - FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX - FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX - FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP - FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST - FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 - FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 - FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD - FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT - FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT - FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT - FSP_SIGNAL_CTSU_END = 0, ///< CTSU END - FSP_SIGNAL_CTSU_READ, ///< CTSU READ - FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE - FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI - FSP_SIGNAL_DALI_CLI, ///< DALI CLI - FSP_SIGNAL_DALI_SDI, ///< DALI SDI - FSP_SIGNAL_DALI_BPI, ///< DALI BPI - FSP_SIGNAL_DALI_FEI, ///< DALI FEI - FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI - FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT - FSP_SIGNAL_DOC_INT = 0, ///< DOC INT - FSP_SIGNAL_DRW_INT = 0, ///< DRW INT - FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE - FSP_SIGNAL_DTC_END, ///< DTC END - FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT - FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 - FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 - FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS - FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT - FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT - FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL - FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE - FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL - FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE - FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL - FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE - FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL - FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE - FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL - FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE - FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL - FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE - FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR - FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI - FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT - FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 - FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 - FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A - FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B - FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C - FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D - FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E - FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F - FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW - FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW - FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A - FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B - FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE - FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 - FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 - FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 - FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 - FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 - FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 - FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 - FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 - FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 - FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 - FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 - FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 - FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 - FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 - FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 - FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 - FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL - FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI - FSP_SIGNAL_IIC_RXI, ///< IIC RXI - FSP_SIGNAL_IIC_TEI, ///< IIC TEI - FSP_SIGNAL_IIC_TXI, ///< IIC TXI - FSP_SIGNAL_IIC_WUI, ///< IIC WUI - FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 - FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 - FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 - FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 - FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B - FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C - FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D - FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E - FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW - FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI - FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI - FSP_SIGNAL_KEY_INT = 0, ///< KEY INT - FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END - FSP_SIGNAL_PDC_INT, ///< PDC INT - FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY - FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT - FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT - FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM - FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD - FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY - FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY - FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY - FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG - FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY - FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 - FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 - FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK - FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY - FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 - FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 - FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 - FSP_SIGNAL_SCI_AM = 0, ///< SCI AM - FSP_SIGNAL_SCI_ERI, ///< SCI ERI - FSP_SIGNAL_SCI_RXI, ///< SCI RXI - FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI - FSP_SIGNAL_SCI_TEI, ///< SCI TEI - FSP_SIGNAL_SCI_TXI, ///< SCI TXI - FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI - FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND - FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND - FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS - FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD - FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ - FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO - FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI - FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE - FSP_SIGNAL_SPI_RXI, ///< SPI RXI - FSP_SIGNAL_SPI_TEI, ///< SPI TEI - FSP_SIGNAL_SPI_TXI, ///< SPI TXI - FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END - FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY - FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL - FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW - FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW - FSP_SIGNAL_SSI_INT = 0, ///< SSI INT - FSP_SIGNAL_SSI_RXI, ///< SSI RXI - FSP_SIGNAL_SSI_TXI, ///< SSI TXI - FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI - FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ - FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 - FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 - FSP_SIGNAL_USB_INT, ///< USB INT - FSP_SIGNAL_USB_RESUME, ///< USB RESUME - FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW - FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A - FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B - FSP_SIGNAL_ULPT_INT, ///< ULPT INT -} fsp_signal_t; - -typedef void (* fsp_vector_t)(void); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_version.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_version.h deleted file mode 100644 index 54b5c25ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/fsp_version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_VERSION_H - #define FSP_VERSION_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ - #include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup RENESAS_COMMON - * @{ - **********************************************************************************************************************/ - - #ifdef __cplusplus -extern "C" { - #endif - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** FSP pack major version. */ - #define FSP_VERSION_MAJOR (5U) - -/** FSP pack minor version. */ - #define FSP_VERSION_MINOR (8U) - -/** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) - -/** FSP pack version build number (currently unused). */ - #define FSP_VERSION_BUILD (0U) - -/** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.8.0") - -/** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.8.0") - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** FSP Pack version structure */ -typedef union st_fsp_pack_version -{ - /** Version id */ - uint32_t version_id; - - /** - * Code version parameters, little endian order. - */ - struct version_id_b_s - { - uint8_t build; ///< Build version of FSP Pack - uint8_t patch; ///< Patch version of FSP Pack - uint8_t minor; ///< Minor version of FSP Pack - uint8_t major; ///< Major version of FSP Pack - } version_id_b; -} fsp_pack_version_t; - -/** @} */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/instance/r_ioport.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/instance/r_ioport.h deleted file mode 100644 index 14abb229e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/instance/r_ioport.h +++ /dev/null @@ -1,522 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup IOPORT - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_H -#define R_IOPORT_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "r_ioport_api.h" -#if __has_include("r_ioport_cfg.h") - #include "r_ioport_cfg.h" -#endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ -typedef struct st_ioport_instance_ctrl -{ - uint32_t open; - void const * p_context; -} ioport_instance_ctrl_t; - -/* This typedef is here temporarily. See SWFLEX-144 for details. */ -/** Superset list of all possible IO port pins. */ -typedef enum e_ioport_port_pin_t -{ - IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 -} ioport_port_pin_t; - -#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #endif - - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an UARTA peripheral pin */ - IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; -#endif - -#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; -#endif - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const ioport_api_t g_ioport_on_ioport; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ - -fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); -fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); -fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); -fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); -fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); -fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); -fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t direction_values, - ioport_size_t mask); -fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); -fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t event_data, - ioport_size_t mask_value); -fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); -fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_IOPORT_H diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/periph/bsp_peripheral.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/periph/bsp_peripheral.h deleted file mode 100644 index bcaaf823c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/periph/bsp_peripheral.h +++ /dev/null @@ -1,211 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_PERIPHERAL_H -#define BSP_PERIPHERAL_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -// *UNCRUSTIFY-OFF* - -#define BSP_PERIPHERAL_ACMP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_PRESENT (1) -#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ADC_B_PRESENT (0) -#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_D_PRESENT (0) -#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AGT_PRESENT (1) -#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) -#define BSP_PERIPHERAL_AGTW_PRESENT (0) -#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AMI_PRESENT (0) -#define BSP_PERIPHERAL_ANALOG_PRESENT (1) -#define BSP_PERIPHERAL_BUS_PRESENT (1) -#define BSP_PERIPHERAL_CAC_PRESENT (1) -#define BSP_PERIPHERAL_CACHE_PRESENT (1) -#define BSP_PERIPHERAL_CAN_PRESENT (0) -#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_CANFD_PRESENT (1) -#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_CEC_PRESENT (1) -#define BSP_PERIPHERAL_CEU_PRESENT (0) -#define BSP_PERIPHERAL_CGC_PRESENT (1) -#define BSP_PERIPHERAL_CPSCU_PRESENT (1) -#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) -#define BSP_PERIPHERAL_CRC_PRESENT (1) -#define BSP_PERIPHERAL_CTSU_PRESENT (1) -#define BSP_PERIPHERAL_DAC_PRESENT (1) -#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DAC_B_PRESENT (0) -#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC8_PRESENT (0) -#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC12_PRESENT (1) -#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DEBUG_PRESENT (1) -#define BSP_PERIPHERAL_DMA_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) -#define BSP_PERIPHERAL_DOC_PRESENT (1) -#define BSP_PERIPHERAL_DOC_B_PRESENT (0) -#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) -#define BSP_PERIPHERAL_DRW_PRESENT (0) -#define BSP_PERIPHERAL_DSILINK_PRESENT (0) -#define BSP_PERIPHERAL_DTC_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ECCMB_PRESENT (1) -#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ELC_PRESENT (1) -#define BSP_PERIPHERAL_ELC_B_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_FACI_PRESENT (1) -#define BSP_PERIPHERAL_FCACHE_PRESENT (1) -#define BSP_PERIPHERAL_FLAD_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) -#define BSP_PERIPHERAL_GLCDC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_PRESENT (1) -#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) -#define BSP_PERIPHERAL_I3C_PRESENT (0) -#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ICU_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) -#define BSP_PERIPHERAL_IIC_PRESENT (1) -#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) -#define BSP_PERIPHERAL_IIC_B_PRESENT (0) -#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) -#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) -#define BSP_PERIPHERAL_IICA_PRESENT (0) -#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IPC_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_PRESENT (0) -#define BSP_PERIPHERAL_IRTC_PRESENT (0) -#define BSP_PERIPHERAL_IWDT_PRESENT (1) -#define BSP_PERIPHERAL_JPEG_PRESENT (0) -#define BSP_PERIPHERAL_KINT_PRESENT (0) -#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_MACL_PRESENT (0) -#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) -#define BSP_PERIPHERAL_MMF_PRESENT (0) -#define BSP_PERIPHERAL_MPU_PRESENT (1) -#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_MRMS_PRESENT (0) -#define BSP_PERIPHERAL_MRRGE_PRESENT (0) -#define BSP_PERIPHERAL_MSTP_PRESENT (1) -#define BSP_PERIPHERAL_OCD_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_OSPI_PRESENT (1) -#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) -#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) -#define BSP_PERIPHERAL_PDC_PRESENT (0) -#define BSP_PERIPHERAL_PFS_PRESENT (1) -#define BSP_PERIPHERAL_PFS_B_PRESENT (0) -#define BSP_PERIPHERAL_PMISC_PRESENT (0) -#define BSP_PERIPHERAL_PORGA_PRESENT (0) -#define BSP_PERIPHERAL_PORT_PRESENT (1) -#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) -#define BSP_PERIPHERAL_PSCU_PRESENT (1) -#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) -#define BSP_PERIPHERAL_QSPI_PRESENT (1) -#define BSP_PERIPHERAL_RADIO_PRESENT (0) -#define BSP_PERIPHERAL_RSIP_PRESENT (1) -#define BSP_PERIPHERAL_RTC_PRESENT (1) -#define BSP_PERIPHERAL_RTC_C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_PRESENT (0) -#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) -#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) -#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SCI_PRESENT (1) -#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_SCI_B_PRESENT (0) -#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDHI_PRESENT (1) -#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SLCDC_PRESENT (0) -#define BSP_PERIPHERAL_SPI_PRESENT (1) -#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_SPI_B_PRESENT (0) -#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SPMON_PRESENT (0) -#define BSP_PERIPHERAL_SRAM_PRESENT (1) -#define BSP_PERIPHERAL_SRC_PRESENT (0) -#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) -#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) -#define BSP_PERIPHERAL_TAU_PRESENT (0) -#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TFU_PRESENT (0) -#define BSP_PERIPHERAL_TML_PRESENT (0) -#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TRNG_PRESENT (0) -#define BSP_PERIPHERAL_TSD_PRESENT (1) -#define BSP_PERIPHERAL_TSN_PRESENT (1) -#define BSP_PERIPHERAL_TZF_PRESENT (1) -#define BSP_PERIPHERAL_UARTA_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ULPT_PRESENT (0) -#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_USB_PRESENT (1) -#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_USB_FS_PRESENT (1) -#define BSP_PERIPHERAL_USB_HS_PRESENT (1) -#define BSP_PERIPHERAL_USBCC_PRESENT (0) -#define BSP_PERIPHERAL_WDT_PRESENT (1) -#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_api.h deleted file mode 100644 index dcb104b06..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_SYSTEM_INTERFACES - * @defgroup IOPORT_API I/O Port Interface - * @brief Interface for accessing I/O ports and configuring I/O functionality. - * - * @section IOPORT_API_SUMMARY Summary - * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. - * Port and pin direction can be changed. - * - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_API_H -#define R_IOPORT_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common error codes and definitions. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -#ifndef BSP_OVERRIDE_IOPORT_SIZE_T - -/** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size -#endif - -/** Pin identifier and pin configuration value */ -typedef struct st_ioport_pin_cfg -{ - uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure - bsp_io_port_pin_t pin; ///< Pin identifier -} ioport_pin_cfg_t; - -/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ -typedef struct st_ioport_cfg -{ - uint16_t number_of_pins; ///< Number of pins for which there is configuration data - ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data - const void * p_extend; ///< Pointer to hardware extend configuration -} ioport_cfg_t; - -/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - */ -typedef void ioport_ctrl_t; - -/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ -typedef struct st_ioport_api -{ - /** Initialize internal driver data and initial pin configurations. Called during startup. Do - * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of - * multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Close the API. - * - * @param[in] p_ctrl Pointer to control structure. - **/ - fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); - - /** Configure multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Configure settings for an individual pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] cfg Configuration options for the pin. - */ - fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); - - /** Read the event input data of the specified pin and return the level. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_event Pointer to return the event data. - */ - fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); - - /** Write pin event data. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin event data is to be written to. - * @param[in] pin_value Level to be written to pin output event. - */ - fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); - - /** Read level of a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_value Pointer to return the pin level. - */ - fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); - - /** Write specified level to a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be written to. - * @param[in] level State to be written to the pin. - */ - fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); - - /** Set the direction of one or more pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port. - * @param[in] mask Mask controlling which pins on the port are to be configured. - */ - fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, - ioport_size_t mask); - - /** Read captured event data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_event_data Pointer to return the event data. - */ - fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); - - /** Write event output data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port event data will be written to. - * @param[in] event_data Data to be written as event data to specified port. - * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. - * being written to port. - */ - fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, - ioport_size_t mask_value); - - /** Read states of pins on the specified port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_port_value Pointer to return the port value. - */ - fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); - - /** Write to multiple pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be written to. - * @param[in] value Value to be written to the port. - * @param[in] mask Mask controlling which pins on the port are written to. - */ - fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); -} ioport_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_ioport_instance -{ - ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - ioport_api_t const * p_api; ///< Pointer to the API structure for this instance -} ioport_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT_API) - **********************************************************************************************************************/ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_cfg.h deleted file mode 100644 index d2688bf5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/r_ioport_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#ifdef __cplusplus -} -#endif -#endif /* R_IOPORT_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/renesas.h b/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/renesas.h deleted file mode 100644 index 41098a054..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/thirdparty/ra6m5bg/renesas.h +++ /dev/null @@ -1,154 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* Ensure Renesas MCU variation definitions are included to ensure MCU - * specific register variations are handled correctly. */ -#ifndef BSP_FEATURE_H - #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." -#endif - -/** @addtogroup Renesas - * @{ - */ - -/** @addtogroup RA - * @{ - */ - -#ifndef RA_H - #define RA_H - - #ifdef __cplusplus -extern "C" { - #endif - - #include "cmsis_compiler.h" - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - - #if BSP_MCU_GROUP_RA0E1 - #include "R7FA0E107.h" - #elif BSP_MCU_GROUP_RA2A1 - #include "R7FA2A1AB.h" - #elif BSP_MCU_GROUP_RA2A2 - #include "R7FA2A2AD.h" - #elif BSP_MCU_GROUP_RA2E1 - #include "R7FA2E1A9.h" - #elif BSP_MCU_GROUP_RA2E2 - #include "R7FA2E2A7.h" - #elif BSP_MCU_GROUP_RA2E3 - #include "R7FA2E307.h" - #elif BSP_MCU_GROUP_RA2L1 - #include "R7FA2L1AB.h" - #elif BSP_MCU_GROUP_RA4E1 - #include "R7FA4E10D.h" - #elif BSP_MCU_GROUP_RA4E2 - #include "R7FA4E2B9.h" - #elif BSP_MCU_GROUP_RA4M1 - #include "R7FA4M1AB.h" - #elif BSP_MCU_GROUP_RA4M2 - #include "R7FA4M2AD.h" - #elif BSP_MCU_GROUP_RA4M3 - #include "R7FA4M3AF.h" - #elif BSP_MCU_GROUP_RA4T1 - #include "R7FA4T1BB.h" - #elif BSP_MCU_GROUP_RA4W1 - #include "R7FA4W1AD.h" - #elif BSP_MCU_GROUP_RA4L1 - #include "R7FA4L1BD.h" - #elif BSP_MCU_GROUP_RA6E1 - #include "R7FA6E10F.h" - #elif BSP_MCU_GROUP_RA6E2 - #include "R7FA6E2BB.h" - #elif BSP_MCU_GROUP_RA6M1 - #include "R7FA6M1AD.h" - #elif BSP_MCU_GROUP_RA6M2 - #include "R7FA6M2AF.h" - #elif BSP_MCU_GROUP_RA6M3 - #include "R7FA6M3AH.h" - #elif BSP_MCU_GROUP_RA6M4 - #include "R7FA6M4AF.h" - #elif BSP_MCU_GROUP_RA6M5 - #include "R7FA6M5BH.h" - #elif BSP_MCU_GROUP_RA6T1 - #include "R7FA6T1AD.h" - #elif BSP_MCU_GROUP_RA6T2 - #include "R7FA6T2BD.h" - #elif BSP_MCU_GROUP_RA6T3 - #include "R7FA6T3BB.h" - #elif BSP_MCU_GROUP_RA8M1 - #include "R7FA8M1AH.h" - #elif BSP_MCU_GROUP_RA8D1 - #include "R7FA8D1BH.h" - #elif BSP_MCU_GROUP_RA8T1 - #include "R7FA8T1AH.h" - #elif BSP_MCU_GROUP_RA8E1 - #include "R7FA8E1AF.h" - #else - #if __has_include("renesas_internal.h") - #include "renesas_internal.h" - #else - #warning "Unsupported MCU" - #endif - #endif - -/* - * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB - * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 - * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: - * - * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | - * |-----------|------------|------------------------| - * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | - * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | - * - * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ - * - * IAR is currently the only toolchain producing the correct __ARM_ARCH value. - * - *- See https://github.com/ARM-software/CMSIS_6/issues/159 - */ - #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 - #undef __ARM_ARCH - #define __ARM_ARCH 801 - #endif - - #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M4 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) - #define RENESAS_CORTEX_M23 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M33 - #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M85 - #else - #warning Unsupported Architecture - #endif - - #ifdef __cplusplus -} - #endif - -#endif /* RA_H */ - -/** @} */ /* End of group RA */ - -/** @} */ /* End of group Renesas */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/R7FA6M5BH.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/R7FA6M5BH.h deleted file mode 100644 index 998c38712..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/R7FA6M5BH.h +++ /dev/null @@ -1,29959 +0,0 @@ -/* - * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause - * - * @file ./out/R7FA6M5BH.h - * @brief CMSIS HeaderFile - * @version 1.10.08 - */ - -/** @addtogroup Renesas Electronics Corporation - * @{ - */ - -/** @addtogroup R7FA6M5BH - * @{ - */ - -#ifndef R7FA6M5BH_H - #define R7FA6M5BH_H - - #ifdef __cplusplus -extern "C" { - #endif - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ - #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ - #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ - #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ - #define __MPU_PRESENT 1 /*!< MPU present */ - #define __FPU_PRESENT 1 /*!< FPU present */ - #define __FPU_DP 0 /*!< Double Precision FPU */ - #define __DSP_PRESENT 1 /*!< DSP extension present */ - #define __SAUREGION_PRESENT 0 /*!< SAU region present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - - #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ - #include "system.h" /*!< R7FA6M5BH System */ - - #ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I - #endif - #ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O - #endif - #ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO - #endif - -/* ======================================== Start of section using anonymous unions ======================================== */ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions - #elif defined(__ICCARM__) - #pragma language=extended - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning 586 - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #else - #warning Not supported compiler type - #endif - -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - -/** - * @brief R_BUS_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ - - struct - { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; - }; - - union - { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ - - struct - { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; - }; - __IM uint32_t RESERVED1; -} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_CSb [CSb] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ - - struct - { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; - }; - __IM uint16_t RESERVED1[3]; - - union - { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ - - struct - { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; - }; - __IM uint16_t RESERVED2[2]; -} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ - - struct - { - __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint8_t : 3; - __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ - uint8_t : 2; - } SDCCR_b; - }; - - union - { - __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ - - struct - { - __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ - uint8_t : 7; - } SDCMOD_b; - }; - - union - { - __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ - - struct - { - __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ - uint8_t : 7; - } SDAMOD_b; - }; - __IM uint8_t RESERVED; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ - - struct - { - __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ - uint8_t : 7; - } SDSELF_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ - - struct - { - __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ - __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count - * Setting. ( REFW+1 Cycles ) */ - } SDRFCR_b; - }; - - union - { - __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ - - struct - { - __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ - uint8_t : 7; - } SDRFEN_b; - }; - __IM uint8_t RESERVED4; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ - - struct - { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ - - struct - { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; - - union - { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ - - struct - { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ - - struct - { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; - }; - - union - { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ - - struct - { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ - uint16_t : 1; - } SDMOD_b; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; - - union - { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ - - struct - { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; - }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ - -/** - * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ - } ADD_b; - }; - - union - { - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ - } STAT_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ - - struct - { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ - - struct - { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ - - struct - { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) - */ -typedef struct -{ - union - { - __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ - - struct - { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ - __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ - uint8_t : 2; - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ - - struct - { - __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when - * a bus error occurs */ - uint32_t : 31; - } IRQEN_b; - }; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ - - struct - { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ - __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ - uint8_t : 2; - } CLR_b; - }; - }; - __IM uint32_t RESERVED3; -} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[36]; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ - - struct - { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } STAT_b; - }; - __IM uint8_t RESERVED1[7]; - - union - { - __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ - - struct - { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } CLR_b; - }; -} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ - -/** - * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) - */ -typedef struct -{ - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } MRE0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } FLBI_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S0BI_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S1BI_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S2BI_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } S3BI_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } STBYSBI_b; - }; - __IM uint32_t RESERVED7; - - union - { - union - { - __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } ECBI_b; - }; - - union - { - __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI0BI_b; - }; - }; - __IM uint32_t RESERVED8; - - union - { - union - { - __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } EOBI_b; - }; - - union - { - __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } SPI1BI_b; - }; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PBBI_b; - }; - __IM uint32_t RESERVED10; - - union - { - union - { - __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PABI_b; - }; - - union - { - __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } CPU0SAHBI_b; - }; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PIBI_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ - uint32_t : 31; - } PSBI_b; - }; -} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ - -/** - * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } FHBI_b; - }; - - union - { - __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } MRC0BI_b; - }; - }; - __IM uint32_t RESERVED[5]; - - union - { - __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S0BI_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - - struct - { - __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ - uint32_t : 30; - } S1BI_b; - }; -} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ - -/** - * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) - */ -typedef struct -{ - union - { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ - - struct - { - __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ - } ADD_b; - }; - - union - { - __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read - * Write. */ - - struct - { - __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write - * Status. */ - uint8_t : 7; - } RW_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - - struct - { - __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ - __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ - __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ - uint16_t : 13; - } BUSOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } BUSOADPT_b; - }; - __IM uint16_t RESERVED1[5]; - - union - { - __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection - * Register. */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ - } MSAOAD_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Key code */ - } MSAPT_b; - }; -} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ - -/** - * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) - */ -typedef struct -{ - union - { - __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ - - struct - { - __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ - __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ - __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ - __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ - __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ - __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ - __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ - __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ - __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ - __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ - __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ - __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ - __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ - __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ - __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ - __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ - __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ - __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ - __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ - __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ - __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ - __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ - __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ - __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ - __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ - __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ - __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ - __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ - __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ - __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ - __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ - __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ - } STAT_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ - - struct - { - __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ - __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ - __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ - __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ - __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ - __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ - __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ - __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ - __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ - __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ - __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ - __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ - __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ - __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ - __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ - __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ - __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ - __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ - __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ - __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ - __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ - __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ - __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ - __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ - __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ - __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ - __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ - __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ - __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ - __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ - __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ - __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ - } CLR_b; - }; -} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ - -/** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ - union - { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - - struct - { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ - uint16_t : 2; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ - uint16_t : 10; - } CNT_b; - }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) - */ -typedef struct -{ - union - { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ - - struct - { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; - }; - - union - { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ - - struct - { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; - }; - - union - { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ - - struct - { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; - }; - - union - { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ - - struct - { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; - }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ - - struct - { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; - }; - - union - { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ - - struct - { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ - - struct - { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; - }; - - union - { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ - - struct - { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; - }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ - union - { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ - - struct - { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; - }; - - union - { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct - { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - - struct - { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - - struct - { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct - { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ - - struct - { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - - struct - { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - - struct - { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ - - struct - { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; - - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ - - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ - -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ - union - { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - - struct - { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; - }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ - union - { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ - - struct - { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; - }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ - union - { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) - */ -typedef struct -{ - union - { - __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ - uint16_t : 12; - } AC_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ - - struct - { - __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. - * NOTE: Some low-order bits are fixed to 0. */ - } S_b; - }; - - union - { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ - - struct - { - __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination. NOTE: Some low-order - * bits are fixed to 1. */ - } E_b; - }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } EN_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } ENPT_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_b; - }; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } RPT_SEC_b; - }; - __IM uint16_t RESERVED3; - __IM uint32_t RESERVED4[60]; - __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ - __IM uint32_t RESERVED5[32]; -} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; - - union - { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ - - struct - { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; - }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ - union - { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ - - struct - { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; - }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_RTC_CP [CP] (Capture registers) - */ -typedef struct -{ - __IM uint8_t RESERVED[2]; - - union - { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; - - union - { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union - { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; - - union - { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; - }; - __IM uint8_t RESERVED3[3]; - - union - { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; - - union - { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; - }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; - }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ - union - { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; - }; - - union - { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ - - struct - { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; - }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ - union - { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ - - struct - { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; - }; - - union - { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ - - struct - { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; - }; - - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; - - union - { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct - { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; - - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ - - struct - { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; - - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ - - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; - - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; - }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ - -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ - - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct - { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - - struct - { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ - - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; - - union - { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct - { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; - - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ - - struct - { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED23[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ - - struct - { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; - }; - - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; - - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ - - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ - __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ - uint32_t : 3; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ - uint32_t : 2; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ - uint32_t : 27; - } MSSAR_b; - }; - - union - { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - - union - { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ - - struct - { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; - }; - - union - { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; - }; - - union - { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ - - struct - { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; - }; - - union - { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ - - struct - { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; - }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ - - union - { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - - union - { - __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ - }; - __IM uint32_t RESERVED4[58]; - - union - { - union - { - __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ - - struct - { - __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ - uint32_t : 31; - } BUSMABT_b; - }; - __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - }; - __IM uint32_t RESERVED5[46]; - - union - { - __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ - __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ - }; - __IM uint32_t RESERVED6[33]; - - union - { - __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ - - struct - { - __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ - uint32_t : 2; - __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ - uint32_t : 12; - __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ - uint32_t : 15; - } BUSDIVBYP_b; - }; - __IM uint32_t RESERVED7[63]; - - union - { - __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ - - struct - { - __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ - uint16_t : 15; - } BUSTHRPUT_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[255]; - __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED10[16]; - - union - { - __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address - * and Read/Write Status registers. */ - }; - __IM uint32_t RESERVED11[28]; - - union - { - __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ - __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ - }; - __IM uint32_t RESERVED12[16]; - __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ - __IM uint32_t RESERVED13[5]; - __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ -} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ - union - { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; - }; - - union - { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct - { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; - }; - - union - { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - - struct - { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; - - union - { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - - struct - { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; - }; - - union - { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ - - struct - { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - - union - { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ - - struct - { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; - }; - - union - { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ - - struct - { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; - }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; - }; - - union - { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ - - struct - { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; - }; - - union - { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ - - struct - { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; - }; - - union - { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ - - struct - { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; - }; - - union - { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ - - struct - { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; - }; - __IM uint32_t RESERVED1[3]; - - union - { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ - - struct - { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; - }; - - union - { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ - - struct - { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; - }; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; - }; - - union - { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ - - struct - { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; - }; - - union - { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; - }; - - union - { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ - - struct - { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; - }; - __IM uint32_t RESERVED3[18]; - - union - { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ - - struct - { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; - }; - __IM uint32_t RESERVED4[18]; - - union - { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ - - struct - { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; - }; - __IM uint32_t RESERVED5[18]; - - union - { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; - }; - __IM uint32_t RESERVED6[18]; - - union - { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct - { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; - }; - - union - { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; - }; - - union - { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ - - struct - { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; - }; - - union - { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; - }; - - union - { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; - }; - - union - { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; - }; - - union - { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ - - struct - { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; - }; - - union - { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ - - struct - { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; - }; - - union - { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ - - struct - { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; - }; - __IM uint32_t RESERVED7[2]; - - union - { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ - - struct - { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; - }; - __IM uint32_t RESERVED8[288]; - - union - { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ - - struct - { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; - }; - __IM uint32_t RESERVED9[288]; - - union - { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ - - struct - { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; - }; - __IM uint32_t RESERVED10[36]; - - union - { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ - - struct - { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; - }; - __IM uint32_t RESERVED11[36]; - - union - { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ - - struct - { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; - }; - __IM uint32_t RESERVED12[36]; - - union - { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ - - struct - { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; - }; - __IM uint32_t RESERVED13[36]; - - union - { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ - - struct - { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; - }; - __IM uint32_t RESERVED14[40]; - - union - { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; - }; - __IM uint32_t RESERVED15[6]; - - union - { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; - }; - __IM uint32_t RESERVED16[6]; - - union - { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; - }; - __IM uint32_t RESERVED17[6]; - - union - { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; - }; - __IM uint32_t RESERVED18[6]; - - union - { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; - }; - __IM uint32_t RESERVED19[6]; - - union - { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; - }; - __IM uint32_t RESERVED20[6]; - - union - { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; - }; - __IM uint32_t RESERVED21[6]; - - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; - - union - { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; - }; - __IM uint32_t RESERVED23[6]; - - union - { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ - - struct - { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; - }; - __IM uint32_t RESERVED24[6]; - - union - { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ - - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; - }; - __IM uint32_t RESERVED25[6]; - - union - { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - - struct - { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; - }; - __IM uint32_t RESERVED26[6]; - - union - { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - - struct - { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; - }; - - union - { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ - - struct - { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; - }; - __IM uint32_t RESERVED27; - - union - { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; - }; - - union - { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ - - struct - { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; - }; - - union - { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ - - struct - { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; - }; - __IM uint32_t RESERVED28[24]; - - union - { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ - - struct - { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; - }; - __IM uint32_t RESERVED29[6]; - - union - { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ - - struct - { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; - }; - __IM uint32_t RESERVED30[6]; - - union - { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ - - struct - { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; - }; - __IM uint32_t RESERVED31[46]; - - union - { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ - - struct - { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; - }; - __IM uint32_t RESERVED32; - - union - { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ - - struct - { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; - }; - - union - { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ - - struct - { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; - }; - __IM uint32_t RESERVED33; - - union - { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ - - struct - { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; - }; - __IM uint32_t RESERVED34; - - union - { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ - - struct - { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; - }; - - union - { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ - - struct - { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ - - struct - { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; - }; - - union - { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ - - struct - { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; - - union - { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ - - struct - { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; - }; - - union - { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ - - struct - { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; - }; - __IM uint32_t RESERVED36[2]; - - union - { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ - - struct - { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; - }; - - union - { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ - - struct - { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; - }; - __IM uint32_t RESERVED37[2]; - - union - { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; - }; - __IM uint32_t RESERVED38[10]; - - union - { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ - - struct - { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; - }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; - - union - { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ - - struct - { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; - }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ - -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; - - union - { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - - struct - { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; - }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ - -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ - union - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ - - struct - { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; - }; - - union - { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - - struct - { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; - }; - - union - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ - - struct - { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; - }; - - union - { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ - - struct - { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; - }; - - union - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ - - struct - { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; - }; - - union - { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ - - struct - { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; - }; - - union - { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; - }; - - union - { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ - - struct - { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; - }; - - union - { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ - - struct - { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; - }; - - union - { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ - - struct - { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; - }; - - union - { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; - }; - - union - { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ - - struct - { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; - }; - - union - { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ - - struct - { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; - }; - - union - { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ - - struct - { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; - }; - - union - { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ - - struct - { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; - }; - - union - { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ - - struct - { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; - }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ - -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ - union - { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ - - struct - { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; - }; - - union - { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; - }; - - union - { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; - }; - - union - { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; - }; - - union - { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ - - struct - { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; - }; - - union - { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; - }; - - union - { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ - - struct - { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; - }; - __IM uint16_t RESERVED[9]; - - union - { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; - - union - { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ - - struct - { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ - union - { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct - { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct - { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 12; - __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ - __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; - __IM uint32_t RESERVED1[123]; - - union - { - __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ - - struct - { - __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ - __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ - uint32_t : 6; - __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ - uint32_t : 21; - } FSBLSTAT_b; - }; -} R_DEBUG_Type; /*!< Size = 516 (0x204) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ - -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ - union - { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ - - struct - { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ - - struct - { - __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ - uint8_t : 3; - __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ - uint8_t : 3; - } DMCTL_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[11]; - - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ - - struct - { - __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ - uint32_t : 4; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; - }; - __IM uint32_t RESERVED6[15]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ - -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ - union - { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ - - struct - { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; - }; - - union - { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ - - struct - { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; - }; - - union - { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; - }; - - union - { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ - - struct - { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; - }; - - union - { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ - - struct - { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ - - struct - { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; - }; - - union - { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ - - struct - { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Up2025-07-29 Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Up2025-07-29 Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Up2025-07-29 Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Up2025-07-29 Mode */ - } DMAMD_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ - - struct - { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address up2025-07-29 mode for transfer source or destination. */ - } DMOFR_b; - }; - - union - { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ - - struct - { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - - union - { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ - - struct - { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; - }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ - - union - { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ - - struct - { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; - }; - - union - { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ - - struct - { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; - }; - - union - { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ - - struct - { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ - -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ - union - { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ - - struct - { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ - - struct - { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; - }; - - union - { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ - - struct - { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; - }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ - -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ - union - { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_b; - }; - - union - { - __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ - - struct - { - __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ - uint8_t : 7; - } DTCADMOD_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ - - struct - { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ - - struct - { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; - }; - - union - { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ - - struct - { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_SEC_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - - union - { - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - - struct - { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ - } DTCVBR_SEC_b; - }; - - union - { - __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ - - struct - { - __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ - } DTCDISP_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ - - struct - { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; - }; - - union - { - __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ - } DTCIBR_b; - }; - - union - { - __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ - - struct - { - __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ - uint8_t : 7; - } DTCOR_b; - }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ - - struct - { - __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ - uint16_t : 7; - __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ - } DTCSQE_b; - }; - __IM uint16_t RESERVED10; -} R_DTC_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ - union - { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; - }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; - - union - { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ - - struct - { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ - - struct - { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ - -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ -{ - union - { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ - - struct - { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ - - struct - { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ - - struct - { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ - - struct - { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ - - struct - { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ - - struct - { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; - }; - __IM uint32_t RESERVED5[5]; - - union - { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ - - struct - { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; - }; - __IM uint32_t RESERVED6[3]; - - union - { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ - - struct - { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; - }; - - union - { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ - - struct - { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; - }; - - union - { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ - - struct - { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ - - struct - { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; - }; - - union - { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ - - struct - { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; - }; - __IM uint32_t RESERVED8[20]; - - union - { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ - - struct - { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ - - struct - { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ - - struct - { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ - - union - { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ - - struct - { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; - }; - - union - { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ - - struct - { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; - }; - __IM uint32_t RESERVED11; - - union - { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ - - struct - { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; - }; - - union - { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ - - struct - { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; - }; - - union - { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; - }; - - union - { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ - - struct - { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; - }; - - union - { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ - - struct - { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; - }; - - union - { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ - - struct - { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; - }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ - -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ -{ - union - { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ - - struct - { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ - - struct - { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ - - struct - { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ - - struct - { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; - }; - __IM uint32_t RESERVED4; - - union - { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ - - struct - { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ - - struct - { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ - - struct - { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; - }; - __IM uint32_t RESERVED10; - - union - { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ - - struct - { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; - }; - __IM uint32_t RESERVED11[2]; - - union - { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ - - struct - { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; - }; - - union - { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ - - struct - { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; - }; - - union - { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ - - struct - { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; - }; - - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ - - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; - - union - { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ - - struct - { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; - }; - - union - { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ - - struct - { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; - }; - __IM uint32_t RESERVED13[18]; - - union - { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ - - struct - { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; - }; - - union - { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; - }; - __IM uint32_t RESERVED14; - - union - { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ - - struct - { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; - }; - - union - { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ - - struct - { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; - }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ - union - { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ - -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ - - struct - { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; - - union - { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ - - struct - { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; - }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; - - union - { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ - - struct - { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; - }; - - union - { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ - - struct - { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; - }; - __IM uint32_t RESERVED8[3]; - - union - { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ - - struct - { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ - - struct - { - __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ - uint8_t : 5; - } FCNTSELR_b; - }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; - - union - { - __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR0_b; - }; - - union - { - __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ - - struct - { - __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ - } FCNTDATAR1_b; - }; - __IM uint32_t RESERVED12[9]; - - union - { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ - - struct - { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; - }; - __IM uint16_t RESERVED13; - - union - { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ - - struct - { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; - }; - __IM uint16_t RESERVED14; - - union - { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ - - struct - { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; - }; - - union - { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ - - struct - { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; - }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16; - - union - { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ - - struct - { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; - }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[4]; - - union - { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ - - struct - { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; - }; - __IM uint16_t RESERVED19; - __IM uint32_t RESERVED20[11]; - - union - { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ - - struct - { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; - - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ - - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED23; - __IM uint16_t RESERVED24; - - union - { - union - { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ - - struct - { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; - }; - - union - { - __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ - - struct - { - __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address - * or the last blank checked address which is found in 'Blank - * Check' command execution. */ - uint32_t : 8; - } FBCADDR_b; - }; - }; - - union - { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ - - struct - { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; - }; - - union - { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ - - struct - { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ - - struct - { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ - - struct - { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; - }; - __IM uint16_t RESERVED27; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; - - union - { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ - - struct - { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invali2025-07-29 Register */ - - struct - { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invali2025-07-29 Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; - - union - { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ - - struct - { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; - - union - { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ - - struct - { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ - uint16_t : 6; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ - __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ - uint16_t : 4; - __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ - } FSAR_b; - }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief General PWM Timer (R_GPT0) - */ - -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ - union - { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ - - struct - { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; - }; - - union - { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ - - struct - { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; - }; - - union - { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ - - struct - { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; - }; - - union - { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ - - struct - { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; - }; - - union - { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ - - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; - }; - - union - { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ - - struct - { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; - }; - - union - { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ - - struct - { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; - - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ - - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; - - union - { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ - - struct - { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ - uint32_t : 7; - } GTICASR_b; - }; - - union - { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ - - struct - { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ - uint32_t : 7; - } GTICBSR_b; - }; - - union - { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ - - struct - { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 3; - __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ - __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ - uint32_t : 2; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; - }; - - union - { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ - - struct - { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection - * timing setting */ - uint32_t : 3; - } GTUDDTYC_b; - }; - - union - { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ - - struct - { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invali2025-07-29.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invali2025-07-29.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; - }; - - union - { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ - - struct - { - __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt - * Enable */ - __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; - }; - - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ - - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; - }; - - union - { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ - - struct - { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; - }; - - union - { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ - - struct - { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; - }; - - union - { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ - - struct - { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; - }; - - union - { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ - - struct - { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; - }; - - union - { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ - - struct - { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; - }; - - union - { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ - - struct - { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; - - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; - - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; - - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ - - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; - - union - { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; - }; - - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ - - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; - - union - { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ - - struct - { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; - }; - - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ - - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; - }; - - union - { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ - - struct - { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; - }; - - union - { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ - - struct - { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; - }; - - union - { - __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Control Register */ - - struct - { - __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter - * 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 - * Skipping Count Setting */ - __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping - * Counter 1 Initial Value */ - __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping - * Counter 1 */ - __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Count Source Select */ - uint32_t : 2; - __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping - * 2 Skipping Count Setting */ - __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping - * Counter 2 Initial Value */ - __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping - * Counter 2 */ - } GTADCMSC_b; - }; - - union - { - __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request - * Compare Match Skipping Setting Register */ - - struct - { - __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare - * Match Skipping Function Select */ - uint32_t : 9; - __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion - * Start Request Compare Match Skipping Function Select */ - uint32_t : 9; - } GTADCMSS_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ - - struct - { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; - }; - - union - { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ - - struct - { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; - }; - __IM uint32_t RESERVED1[2]; - - union - { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ - - struct - { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; - }; - - union - { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ - - struct - { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; - }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ - -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ - union - { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ - - struct - { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; - }; - __IM uint32_t RESERVED[15]; - - union - { - __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection - * Register */ - - struct - { - __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ - uint16_t : 7; - __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ - } GTONCWP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling - * Register */ - - struct - { - __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ - uint16_t : 3; - __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ - __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ - uint16_t : 7; - } GTONCCR_b; - }; - __IM uint16_t RESERVED2; -} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ - -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ - union - { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ - - struct - { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 1; - __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; - }; - __IM uint32_t RESERVED[60]; - - union - { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - - struct - { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - - union - { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ - - struct - { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; - }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; - - union - { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ - - struct - { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; - }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; - - union - { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ - - struct - { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; - }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; - - union - { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - - struct - { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - - union - { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ - - struct - { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; - }; - - union - { - __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ - - struct - { - __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return - * Enable */ - __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode - * Return Enable */ - __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze - * Mode */ - uint32_t : 27; - } WUPEN2_b; - }; - __IM uint32_t RESERVED10[5]; - - union - { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ - - struct - { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; - }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; - - union - { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ - - struct - { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; - }; - __IM uint32_t RESERVED16[24]; - - union - { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ - - struct - { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; - }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ - union - { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ - - struct - { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; - }; - - union - { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ - - struct - { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; - }; - - union - { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ - - struct - { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; - }; - - union - { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ - - struct - { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; - }; - - union - { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ - - struct - { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; - }; - - union - { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ - - struct - { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; - }; - - union - { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ - - struct - { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; - }; - - union - { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ - - struct - { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; - }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ - - union - { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ - - struct - { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; - }; - - union - { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ - - struct - { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; - }; - - union - { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ - - struct - { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; - }; - - union - { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ - - struct - { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ - - struct - { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; - }; - - union - { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ - - struct - { - __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; - }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; - }; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; - - union - { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ - -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ - union - { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ - - struct - { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ - - struct - { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; - }; - - union - { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ - - struct - { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; - }; - - union - { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ - - struct - { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ - - struct - { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 2; - __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ - __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ - __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ - __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ - uint32_t : 3; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; - }; - - union - { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; - }; - - union - { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; - }; - - union - { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ - - struct - { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; - }; - - union - { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ - - struct - { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; - }; - __IM uint32_t RESERVED3; - - union - { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ - - struct - { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; - }; - __IM uint32_t RESERVED4[4]; - - union - { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ - - struct - { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ - - struct - { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; - }; - - union - { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ - - struct - { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ - uint32_t : 13; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; - }; - - union - { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ - - struct - { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; - }; - - union - { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ - - struct - { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; - }; - - union - { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ - - struct - { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; - }; - - union - { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ - - struct - { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; - }; - - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ - - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; - - union - { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ - - struct - { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; - }; - - union - { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ - - struct - { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; - }; - - union - { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ - - struct - { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; - }; - __IM uint32_t RESERVED7; - - union - { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ - - struct - { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; - }; - __IM uint32_t RESERVED8; - - union - { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ - - struct - { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; - }; - - union - { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ - - struct - { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; - }; - __IM uint32_t RESERVED9[2]; - - union - { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ - - struct - { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; - }; - __IM uint32_t RESERVED10[3]; - - union - { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ - - struct - { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; - }; - __IM uint32_t RESERVED11[23]; - - union - { - __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ - - struct - { - __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ - uint32_t : 31; - } STCTL_b; - }; - - union - { - __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ - - struct - { - __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ - __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ - __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ - uint32_t : 5; - __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ - uint32_t : 16; - } ATCTL_b; - }; - - union - { - __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ - - struct - { - __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ - uint32_t : 31; - } ATTRG_b; - }; - - union - { - __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ - - struct - { - __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, - * SC2. */ - uint32_t : 31; - } ATCCNTE_b; - }; - __IM uint32_t RESERVED12[4]; - - union - { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ - - struct - { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; - }; - __IM uint32_t RESERVED13[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED14[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - - union - { - __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ - - struct - { - __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ - } HCMDQP_b; - }; - - union - { - __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ - - struct - { - __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ - } HRSPQP_b; - }; - - union - { - __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ - - struct - { - __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ - } HTDTBP_b; - }; - - union - { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; - }; - - union - { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; - }; - __IM uint32_t RESERVED15[10]; - - union - { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ - - struct - { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; - }; - - union - { - __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ - - struct - { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ - uint32_t : 16; - } HQTHCTL_b; - }; - - union - { - __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold - * Control Register */ - - struct - { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ - uint32_t : 5; - } HTBTHCTL_b; - }; - __IM uint32_t RESERVED16; - - union - { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ - - struct - { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 3; - __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ - uint32_t : 7; - } BST_b; - }; - - union - { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ - - struct - { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ - uint32_t : 7; - } BSTE_b; - }; - - union - { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ - - struct - { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ - uint32_t : 7; - } BIE_b; - }; - - union - { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ - - struct - { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 3; - __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ - uint32_t : 7; - } BSTFC_b; - }; - - union - { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; - }; - - union - { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; - }; - - union - { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; - }; - - union - { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; - }; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ - - struct - { - __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ - __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ - uint32_t : 1; - __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ - uint32_t : 22; - } HTST_b; - }; - - union - { - __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ - - struct - { - __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ - __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ - uint32_t : 22; - } HTSTE_b; - }; - - union - { - __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ - - struct - { - __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ - __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ - uint32_t : 22; - } HTIE_b; - }; - - union - { - __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ - - struct - { - __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ - __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ - uint32_t : 1; - __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ - uint32_t : 22; - } HTSTFC_b; - }; - - union - { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ - - struct - { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; - }; - - union - { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - - struct - { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ - uint32_t : 13; - } SVST_b; - }; - - union - { - __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ - - struct - { - __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; - }; - - union - { - __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ - - struct - { - __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ - } MRCCPT_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; - }; - __IM uint32_t RESERVED19; - - union - { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; - }; - __IM uint32_t RESERVED20; - - union - { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; - }; - __IM uint32_t RESERVED21; - - union - { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; - }; - __IM uint32_t RESERVED22; - - union - { - __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS4_b; - }; - __IM uint32_t RESERVED23; - - union - { - __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS5_b; - }; - __IM uint32_t RESERVED24; - - union - { - __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS6_b; - }; - __IM uint32_t RESERVED25; - - union - { - __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ - - struct - { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS7_b; - }; - __IM uint32_t RESERVED26[16]; - - union - { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - - struct - { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; - }; - __IM uint32_t RESERVED27[3]; - - union - { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; - }; - - union - { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; - }; - - union - { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ - - struct - { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; - }; - __IM uint32_t RESERVED28[5]; - - union - { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; - }; - - union - { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; - }; - - union - { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; - }; - - union - { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; - }; - - union - { - __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT4_b; - }; - - union - { - __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT5_b; - }; - - union - { - __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT6_b; - }; - - union - { - __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ - - struct - { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT7_b; - }; - __IM uint32_t RESERVED29[12]; - - union - { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - - struct - { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ - __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; - }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED30; - - union - { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; - }; - - union - { - __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD1_b; - }; - - union - { - __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ - - struct - { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD2_b; - }; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ - - struct - { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; - }; - - union - { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - - struct - { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; - }; - - union - { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ - - struct - { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; - }; - - union - { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ - - struct - { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; - }; - - union - { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - - struct - { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; - }; - - union - { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ - - struct - { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; - }; - - union - { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ - - struct - { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; - }; - - union - { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ - - struct - { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; - }; - - union - { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ - - struct - { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; - }; - - union - { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ - - struct - { - __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ - __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ - __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ - uint32_t : 5; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; - }; - - union - { - __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) - * Register */ - - struct - { - __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ - __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ - uint32_t : 4; - __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ - uint32_t : 24; - } CETSS_b; - }; - - union - { - __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ - - struct - { - __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ - __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ - __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ - uint32_t : 29; - } CGHDRCAP_b; - }; - - union - { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ - - struct - { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; - }; - __IM uint32_t RESERVED32[4]; - - union - { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; - }; - - union - { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; - }; - __IM uint32_t RESERVED33[9]; - - union - { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ - - struct - { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; - }; - - union - { - __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ - - struct - { - __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ - uint32_t : 16; - } HQSTLV_b; - }; - - union - { - __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ - - struct - { - __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ - uint32_t : 16; - } HDBSTLV_b; - }; - - union - { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - - struct - { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; - }; - - union - { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ - - struct - { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; - __IM uint32_t RESERVED34[3]; - - union - { - __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ - - struct - { - __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ - uint32_t : 16; - } SC1CPT_b; - }; - - union - { - __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ - - struct - { - __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ - uint32_t : 16; - } SC2CPT_b; - }; -} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OADPT_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[62]; - __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ - __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ - - struct - { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; - }; - - union - { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ - - struct - { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; - }; - - union - { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ - - struct - { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; - }; - - union - { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; - }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ - -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ - union - { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; - - struct - { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; - }; - - union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; - }; - - union - { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; - - struct - { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; - - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ - - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; - }; - - union - { - union - { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ - - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; - - struct - { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; - - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; - }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-PFS (R_PFS) - */ - -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ - union - { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ - }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports-MISC (R_PMISC) - */ - -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ - union - { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; - }; - __IM uint8_t RESERVED[2]; - - union - { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - - struct - { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; - }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ - union - { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct - { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; - - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - - struct - { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; - - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; - - union - { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct - { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - - struct - { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; - - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ - - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; - }; - - union - { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct - { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct - { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ - __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using - * time error adjustment function inlow-consumption clock - * mode. */ - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; - }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; - - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; - - union - { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; - - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; - }; - __IM uint8_t RESERVED9; - - union - { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; - - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; - }; - __IM uint8_t RESERVED10; - - union - { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; - - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; - }; - __IM uint8_t RESERVED11; - - union - { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; - - union - { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; - }; - __IM uint8_t RESERVED12; - - union - { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; - - union - { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; - }; - - union - { - union - { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; - - union - { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; - - union - { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ - - struct - { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; - }; - - union - { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - - struct - { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; - }; - - union - { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ - - struct - { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; - }; - __IM uint8_t RESERVED19; - - union - { - __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ - - struct - { - uint16_t : 5; - __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ - } RADJ2_b; - }; - __IM uint16_t RESERVED20[7]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ - -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ - union - { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; - - union - { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; - - union - { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; - - union - { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct - { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; - - union - { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF - * = 0, and MMR.MANEN = 1) */ - - struct - { - __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_MANC_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - union - { - __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ - __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ - uint16_t : 2; - __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ - uint16_t : 3; - } TDRHL_MAN_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - union - { - __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN - * = 1) */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ - uint16_t : 2; - __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ - uint16_t : 3; - } RDRHL_MAN_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ - - struct - { - __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ - __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ - __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ - uint8_t : 1; - __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ - __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ - __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ - __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ - } MMR_b; - }; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; - }; - - union - { - __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ - __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ - uint8_t : 2; - } TMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ - - struct - { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; - }; - - union - { - __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ - - struct - { - __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ - __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ - uint8_t : 2; - } RMPR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ - - struct - { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; - }; - - union - { - __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ - - struct - { - __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ - __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ - uint8_t : 5; - } MESR_b; - }; - }; - - union - { - union - { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ - - struct - { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; - }; - - union - { - __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ - - struct - { - __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ - __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ - __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ - uint8_t : 5; - } MECR_b; - }; - }; - - union - { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ - - struct - { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; - }; - - union - { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ - - struct - { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; - - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct - { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ - - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ - - struct - { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ - - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ - - struct - { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ - - struct - { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; - - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct - { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ - __IM uint16_t RESERVED1[4]; - - union - { - __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ - - struct - { - __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ - uint8_t : 7; - } SCIMSKEN_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_SCI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ - -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ - union - { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ - - struct - { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; - }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ - - struct - { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; - }; - - union - { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - - struct - { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; - }; - - union - { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - - struct - { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; - }; - - union - { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - - struct - { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; - }; - - union - { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - - struct - { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; - }; - - union - { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - - struct - { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; - }; - - union - { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ - - struct - { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; - }; - - union - { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - - struct - { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; - }; - - union - { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ - - struct - { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; - }; - - union - { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - - struct - { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; - }; - - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ - - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; - - union - { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - - struct - { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; - }; - - union - { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; - }; - - union - { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ - - struct - { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; - }; - - union - { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; - }; - - union - { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct - { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; - }; - - union - { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct - { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; - }; - - union - { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ - - struct - { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; - }; - - union - { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - - struct - { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; - }; - __IM uint32_t RESERVED1; - - union - { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ - - struct - { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; - }; - - union - { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - - struct - { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; - }; - - union - { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ - - struct - { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - - struct - { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ - - struct - { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; - }; - - union - { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ - - struct - { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; - }; - __IM uint32_t RESERVED3[79]; - - union - { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ - - struct - { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; - }; - __IM uint32_t RESERVED4[3]; - - union - { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ - - struct - { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; - }; - __IM uint32_t RESERVED6[4]; - - union - { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ - - struct - { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; - }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ - - struct - { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; - }; - - union - { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - - struct - { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; - }; - - union - { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ - - struct - { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; - }; - - union - { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - - struct - { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ - }; - - union - { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ - - struct - { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; - }; - - union - { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - - struct - { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; - }; - - union - { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ - - struct - { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; - }; - - union - { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ - - struct - { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; - }; - - union - { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ - - struct - { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; - }; - - union - { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ - - struct - { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; - }; - - union - { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ - - struct - { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; - }; - - union - { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ - - struct - { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; - }; - - union - { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ - - struct - { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; - }; - - union - { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ - - struct - { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; - }; - - union - { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ - - struct - { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; - }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ - -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ - union - { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ - - struct - { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; - }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; - - union - { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ - - struct - { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; - }; - __IM uint8_t RESERVED3[179]; - - union - { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ - - struct - { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; - }; - - union - { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; - }; - - union - { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Up2025-07-29 Enable Register */ - - struct - { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Up2025-07-29 Enable */ - uint8_t : 7; - } ECC1STSEN_b; - }; - - union - { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ - - struct - { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; - }; - - union - { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; - }; - __IM uint8_t RESERVED4[11]; - - union - { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; - }; - __IM uint8_t RESERVED5[3]; - - union - { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ - - struct - { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; - }; - __IM uint8_t RESERVED6[3]; - - union - { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ - - struct - { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; - }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ -{ - union - { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ - - struct - { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; - }; - - union - { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ - - struct - { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; - }; - __IM uint32_t RESERVED[2]; - - union - { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ - - struct - { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 3; - __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ - uint32_t : 4; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; - }; - - union - { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ - - struct - { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; - }; - - union - { - union - { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - - struct - { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; - }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - - union - { - union - { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - - struct - { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; - }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - }; - - union - { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ - - struct - { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; - }; - - union - { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ - - struct - { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; - }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System Pins (R_SYSTEM) - */ - -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; - - union - { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ - - struct - { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; - }; - - union - { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ - - struct - { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; - }; - - union - { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; - }; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ - - struct - { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ - - struct - { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; - }; - - union - { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ - - struct - { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; - }; - - union - { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ - - struct - { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; - }; - __IM uint32_t RESERVED5; - - union - { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ - - struct - { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; - }; - - union - { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ - - struct - { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; - }; - - union - { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; - }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; - - union - { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; - }; - - union - { - __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register - * 2 */ - - struct - { - __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ - uint8_t : 1; - __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ - uint8_t : 2; - } HOCOCR2_b; - }; - - union - { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; - }; - - union - { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ - - struct - { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; - }; - - union - { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ - - struct - { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; - }; - - union - { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ - - struct - { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ - uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ - uint8_t : 1; - } OSCSF_b; - }; - __IM uint8_t RESERVED8; - - union - { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ - - struct - { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; - }; - - union - { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ - - struct - { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; - }; - - union - { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ - - struct - { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; - }; - - union - { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ - - struct - { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; - }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; - - union - { - __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ - - struct - { - __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ - uint16_t : 2; - } PLL2CCR_b; - }; - - union - { - __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ - - struct - { - __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ - uint8_t : 7; - } PLL2CR_b; - }; - __IM uint8_t RESERVED11; - - union - { - __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ - - struct - { - __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock - * (valid only when LPOPTEN = 1) */ - __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ - __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W - * clock (valid only when LPOPT.LPOPTEN = 1) */ - uint8_t : 3; - __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ - } LPOPT_b; - }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; - - union - { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ - - struct - { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; - }; - __IM uint8_t RESERVED14; - - union - { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ - - struct - { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; - }; - - union - { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ - - struct - { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; - }; - __IM uint32_t RESERVED15[3]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO - * trimming bits */ - } MOCOUTCR_b; - }; - - union - { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; - }; - __IM uint8_t RESERVED17; - __IM uint32_t RESERVED18[2]; - - union - { - __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ - - struct - { - __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ - uint8_t : 5; - } USBCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ - uint8_t : 5; - } OCTACKDIVCR_b; - }; - - union - { - __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ - - struct - { - __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ - uint8_t : 5; - } SCISPICKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ - - struct - { - __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ - uint8_t : 5; - } CANFDCKDIVCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - - struct - { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; - }; - - union - { - __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ - - struct - { - __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ - uint8_t : 5; - } USB60CKDIVCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - - struct - { - __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ - uint8_t : 5; - } CECCKDIVCR_b; - }; - - union - { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ - - struct - { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ - - struct - { - __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ - uint8_t : 5; - } I3CCKDIVCR_b; - }; - __IM uint16_t RESERVED19; - - union - { - __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ - __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ - } USBCKCR_b; - }; - - union - { - union - { - __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ - - struct - { - __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ - uint8_t : 3; - __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ - __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ - } OCTACKCR_b; - }; - - union - { - __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ - - struct - { - __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ - uint8_t : 3; - __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ - __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ - } SCISPICKCR_b; - }; - }; - - union - { - __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ - - struct - { - __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ - __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ - } CANFDCKCR_b; - }; - - union - { - union - { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - - struct - { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; - }; - - union - { - __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ - - struct - { - __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ - uint8_t : 2; - __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ - __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ - } USB60CKCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ - - struct - { - __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ - __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ - } CECCKCR_b; - }; - - union - { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ - - struct - { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; - }; - }; - - union - { - __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ - - struct - { - __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ - uint8_t : 3; - __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ - __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ - } I3CCKCR_b; - }; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ - uint32_t : 29; - } SNZREQCR1_b; - }; - __IM uint32_t RESERVED22; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ - - struct - { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; - }; - __IM uint8_t RESERVED24; - - union - { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ - - struct - { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; - }; - - union - { - __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ - - struct - { - __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ - uint8_t : 7; - } SNZEDCR1_b; - }; - __IM uint16_t RESERVED25; - - union - { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ - - struct - { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; - }; - __IM uint16_t RESERVED26; - - union - { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ - - struct - { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; - }; - - union - { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ - - struct - { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; - }; - - union - { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ - - struct - { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; - }; - __IM uint8_t RESERVED27; - - union - { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ - - struct - { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; - }; - __IM uint8_t RESERVED28[2]; - - union - { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ - - struct - { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; - }; - __IM uint16_t RESERVED29[2]; - - union - { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ - - struct - { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; - }; - __IM uint8_t RESERVED30; - __IM uint32_t RESERVED31[5]; - - union - { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ - - struct - { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ - uint16_t : 1; - __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ - } RSTSR1_b; - }; - __IM uint16_t RESERVED32; - __IM uint32_t RESERVED33[3]; - - union - { - __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ - - struct - { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_ALT_b; - }; - - union - { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ - - struct - { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; - }; - __IM uint16_t RESERVED34; - __IM uint32_t RESERVED35[3]; - - union - { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; - }; - - union - { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; - }; - - union - { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ - - struct - { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; - }; - - union - { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ - - struct - { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; - }; - __IM uint32_t RESERVED36[183]; - - union - { - __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute - * Register */ - - struct - { - __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ - __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ - __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ - __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ - __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ - __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ - __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ - __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ - __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ - __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ - __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ - __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ - __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ - __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ - __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ - __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ - __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ - } CGFSAR_b; - }; - __IM uint32_t RESERVED37; - - union - { - __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - uint32_t : 1; - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 1; - __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ - uint32_t : 3; - __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ - __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ - uint32_t : 22; - } LPMSAR_b; - }; - - union - { - union - { - __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - uint32_t : 30; - } LVDSAR_b; - }; - - union - { - __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 29; - } RSTSAR_b; - }; - }; - - union - { - __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ - - struct - { - __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ - __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ - __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ - uint32_t : 13; - __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ - __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ - __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ - __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ - __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ - __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ - __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ - __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ - uint32_t : 8; - } BBFSAR_b; - }; - __IM uint32_t RESERVED38[3]; - - union - { - __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution - * Register */ - - struct - { - __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit - * 0 */ - __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit - * 1 */ - __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit - * 2 */ - __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit - * 3 */ - __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit - * 4 */ - __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit - * 5 */ - __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit - * 6 */ - __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit - * 7 */ - __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit - * 8 */ - __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit - * 9 */ - __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit - * 10 */ - __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit - * 11 */ - __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit - * 12 */ - __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit - * 13 */ - __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit - * 14 */ - __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit - * 15 */ - __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit - * 16 */ - __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit - * 17 */ - __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit - * 18 */ - __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit - * 19 */ - __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit - * 20 */ - uint32_t : 3; - __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit - * 24 */ - uint32_t : 1; - __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit - * 26 */ - __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit - * 27 */ - uint32_t : 4; - } DPFSAR_b; - }; - __IM uint32_t RESERVED39[6]; - __IM uint16_t RESERVED40; - - union - { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ - - struct - { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ - uint16_t : 3; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; - }; - - union - { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ - - struct - { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; - }; - - union - { - __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ - - struct - { - __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ - uint8_t : 2; - } DPSWCR_b; - }; - - union - { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ - - struct - { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; - }; - - union - { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ - - struct - { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; - }; - - union - { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ - - struct - { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; - }; - - union - { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 4; - } DPSIER3_b; - }; - - union - { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ - - struct - { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; - }; - - union - { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ - - struct - { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; - }; - - union - { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ - - struct - { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; - }; - - union - { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ - - struct - { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ - uint8_t : 4; - } DPSIFR3_b; - }; - - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; - }; - - union - { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ - - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; - }; - - union - { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ - - struct - { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; - }; - __IM uint8_t RESERVED41; - - union - { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ - - struct - { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; - }; - - union - { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ - - struct - { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; - }; - - union - { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ - - struct - { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; - }; - - union - { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ - - struct - { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; - }; - __IM uint8_t RESERVED42; - - union - { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; - }; - __IM uint16_t RESERVED43; - - union - { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ - - struct - { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; - }; - - union - { - union - { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - - struct - { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; - }; - - union - { - __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 2; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ - } LVD1CMPCR_b; - }; - }; - - union - { - union - { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - - struct - { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; - }; - - union - { - __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ - - struct - { - __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during - * drop in voltage) */ - uint8_t : 4; - __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ - } LVD2CMPCR_b; - }; - }; - __IM uint8_t RESERVED44; - - union - { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; - }; - - union - { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ - - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; - }; - __IM uint8_t RESERVED45; - - union - { - __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select - * Register */ - - struct - { - __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ - uint8_t : 7; - } VBATTMNSELR_b; - }; - - union - { - __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ - - struct - { - __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ - uint8_t : 7; - } VBATTMONR_b; - }; - - union - { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ - - struct - { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; - }; - __IM uint32_t RESERVED46[8]; - - union - { - union - { - __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ - - struct - { - __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ - __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ - uint8_t : 2; - __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ - __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ - __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ - __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ - } DCDCCTL_b; - }; - - union - { - __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ - - struct - { - __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ - __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ - uint8_t : 6; - } LDOSCR_b; - }; - }; - - union - { - __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ - - struct - { - __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ - uint8_t : 6; - } VCCSEL_b; - }; - __IM uint16_t RESERVED47; - - union - { - __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ - - struct - { - __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ - uint8_t : 7; - } PL2LDOSCR_b; - }; - __IM uint8_t RESERVED48; - __IM uint16_t RESERVED49; - __IM uint32_t RESERVED50[14]; - - union - { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ - - struct - { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; - }; - - union - { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ - - struct - { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; - }; - - union - { - __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ - - struct - { - __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ - uint8_t : 6; - } SOMRG_b; - }; - __IM uint8_t RESERVED51; - __IM uint32_t RESERVED52[3]; - - union - { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ - - struct - { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; - }; - __IM uint8_t RESERVED53; - - union - { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ - - struct - { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; - }; - __IM uint8_t RESERVED54; - __IM uint32_t RESERVED55[7]; - - union - { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ - - struct - { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; - }; - - union - { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ - - struct - { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; - }; - - union - { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ - - struct - { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; - }; - __IM uint8_t RESERVED56; - - union - { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ - - struct - { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; - }; - __IM uint8_t RESERVED57; - - union - { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ - - struct - { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; - }; - __IM uint8_t RESERVED58; - - union - { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; - }; - - union - { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ - - struct - { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; - }; - - union - { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ - - struct - { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; - }; - - union - { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ - - struct - { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; - }; - - union - { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ - - struct - { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; - }; - - union - { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ - - struct - { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; - }; - - union - { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ - - struct - { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; - }; - - union - { - __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ - - struct - { - uint8_t : 3; - __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ - uint8_t : 4; - } VBTBER_b; - }; - __IM uint8_t RESERVED59; - __IM uint16_t RESERVED60; - __IM uint32_t RESERVED61[15]; - - union - { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ - - struct - { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; - }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ - -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ - union - { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ - - struct - { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; - }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ - -typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ -{ - union - { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; - }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ - -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ - - struct - { - uint16_t : 15; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } DVCHGR_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ - uint16_t : 4; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - - union - { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - - struct - { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; - }; - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; - - union - { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ - - struct - { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; - }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; - - union - { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ - - struct - { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; - }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; - - union - { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ - - struct - { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; - }; - __IM uint16_t RESERVED20; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED21[3]; - - union - { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ - - struct - { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED23[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED24; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED25[5]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; - __IM uint32_t RESERVED26[165]; - - union - { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ - - struct - { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; - }; - - union - { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ - - struct - { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; - }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ - -typedef struct /*!< (@ 0x40083400) R_WDT Structure */ -{ - union - { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ - - struct - { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ - - struct - { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; - }; - - union - { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; - }; - - union - { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; - }; - __IM uint8_t RESERVED1; - - union - { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/** - * @brief TrustZone Filter (R_TZF) - */ - -typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ -{ - union - { - __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFOAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ - } TZFPT_b; - }; -} R_TZF_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief R_CACHE (R_CACHE) - */ - -typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ -{ - union - { - __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ - - struct - { - __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ - uint32_t : 31; - } CCACTL_b; - }; - - union - { - __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ - uint32_t : 31; - } CCAFCT_b; - }; - - union - { - __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ - uint32_t : 30; - } CCALCF_b; - }; - __IM uint32_t RESERVED[13]; - - union - { - __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ - - struct - { - __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ - uint32_t : 31; - } SCACTL_b; - }; - - union - { - __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ - - struct - { - __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ - uint32_t : 31; - } SCAFCT_b; - }; - - union - { - __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ - - struct - { - __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ - uint32_t : 30; - } SCALCF_b; - }; - __IM uint32_t RESERVED1[109]; - - union - { - __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection - * Register */ - - struct - { - __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint32_t : 31; - } CAPOAD_b; - }; - - union - { - __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ - - struct - { - __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ - __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ - uint32_t : 24; - } CAPRCR_b; - }; -} R_CACHE_Type; /*!< Size = 520 (0x208) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU System Security Control Unit (R_CPSCU) - */ - -typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ -{ - union - { - __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ - - struct - { - __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ - __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ - __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ - uint32_t : 29; - } CSAR_b; - }; - __IM uint32_t RESERVED[3]; - - union - { - __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ - - struct - { - __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ - __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection - * 2 */ - __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ - uint32_t : 29; - } SRAMSAR_b; - }; - - union - { - __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ - - struct - { - __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ - uint32_t : 28; - } STBRAMSAR_b; - }; - __IM uint32_t RESERVED1[6]; - - union - { - __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ - uint32_t : 31; - } DTCSAR_b; - }; - - union - { - __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ - - struct - { - __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ - uint32_t : 31; - } DMACSAR_b; - }; - __IM uint32_t RESERVED2[2]; - - union - { - __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ - - struct - { - __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ - uint32_t : 16; - } ICUSARA_b; - }; - - union - { - __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ - - struct - { - __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ - uint32_t : 31; - } ICUSARB_b; - }; - - union - { - __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ - - struct - { - __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ - uint32_t : 24; - } ICUSARC_b; - }; - - union - { - __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ - - struct - { - __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ - uint32_t : 31; - } ICUSARD_b; - }; - - union - { - __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ - - struct - { - uint32_t : 16; - __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ - uint32_t : 1; - __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ - __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ - __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ - uint32_t : 2; - __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ - __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ - __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ - uint32_t : 1; - __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ - __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ - __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ - __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ - __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ - } ICUSARE_b; - }; - - union - { - __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ - - struct - { - __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ - __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ - __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ - __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ - uint32_t : 3; - __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ - __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ - __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ - __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ - __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ - __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ - __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ - __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ - uint32_t : 17; - } ICUSARF_b; - }; - - union - { - __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ - - struct - { - __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ - __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ - __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ - __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ - __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ - __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ - __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ - uint32_t : 25; - } ICUSARM_b; - }; - __IM uint32_t RESERVED3[5]; - - union - { - __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ - } ICUSARG_b; - }; - - union - { - __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ - } ICUSARH_b; - }; - - union - { - __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ - - struct - { - __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ - } ICUSARI_b; - }; - __IM uint32_t RESERVED4[33]; - - union - { - __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ - - struct - { - __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ - uint32_t : 31; - } BUSSARA_b; - }; - - union - { - __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ - - struct - { - __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ - uint32_t : 31; - } BUSSARB_b; - }; - __IM uint32_t RESERVED5[2]; - - union - { - __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ - - struct - { - __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ - uint32_t : 31; - } BUSSARC_b; - }; - - union - { - __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ - - struct - { - __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ - uint32_t : 31; - } BUSPARC_b; - }; - __IM uint32_t RESERVED6[6]; - - union - { - __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution - * Register A */ - - struct - { - __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ - uint32_t : 24; - } MMPUSARA_b; - }; - - union - { - __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution - * Register B */ - - struct - { - __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ - uint32_t : 31; - } MMPUSARB_b; - }; - __IM uint32_t RESERVED7[18]; - - union - { - union - { - __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ - - struct - { - __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ - uint32_t : 31; - } TZFSAR_b; - }; - - union - { - __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ - - struct - { - __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ - uint32_t : 31; - } DEBUGSAR_b; - }; - }; - __IM uint32_t RESERVED8[7]; - - union - { - __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ - - struct - { - __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ - uint32_t : 24; - } DMACCHSAR_b; - }; - __IM uint32_t RESERVED9[3]; - - union - { - __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ - - struct - { - __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ - uint32_t : 31; - } CPUDSAR_b; - }; - __IM uint32_t RESERVED10[147]; - - union - { - __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register - * 0 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR0_b; - }; - - union - { - __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register - * 1 */ - - struct - { - uint32_t : 13; - __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start - * address of non-secure region). */ - uint32_t : 11; - } SRAMSABAR1_b; - }; - __IM uint32_t RESERVED11[126]; - - union - { - __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ - - struct - { - __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn - * and ELCSRn */ - uint32_t : 31; - } TEVTRCR_b; - }; -} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Consumer Electronics Control (R_CEC) - */ - -typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ -{ - union - { - __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ - - struct - { - __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ - __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device - * 1) */ - __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device - * 2) */ - __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ - __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ - __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ - __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ - __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ - __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ - __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device - * 3) */ - __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ - __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device - * 3) */ - __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ - __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ - __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ - uint16_t : 1; - } CADR_b; - }; - - union - { - __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ - - struct - { - __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ - __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing - * Select */ - __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ - __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ - __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ - __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ - } CECCTL1_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ - - struct - { - __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ - uint16_t : 7; - } STATB_b; - }; - - union - { - __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ - uint16_t : 7; - } STATL_b; - }; - - union - { - __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ - uint16_t : 7; - } LGC0L_b; - }; - - union - { - __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ - uint16_t : 7; - } LGC1L_b; - }; - - union - { - __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ - - struct - { - __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ - uint16_t : 7; - } DATB_b; - }; - - union - { - __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ - - struct - { - __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ - uint16_t : 7; - } NOMT_b; - }; - - union - { - __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ - uint16_t : 7; - } STATLL_b; - }; - - union - { - __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATLH_b; - }; - - union - { - __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ - uint16_t : 7; - } STATBL_b; - }; - - union - { - __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ - uint16_t : 7; - } STATBH_b; - }; - - union - { - __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LL_b; - }; - - union - { - __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ - uint16_t : 7; - } LGC0LH_b; - }; - - union - { - __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ - uint16_t : 7; - } LGC1LL_b; - }; - - union - { - __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting - * Register */ - - struct - { - __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ - uint16_t : 7; - } LGC1LH_b; - }; - - union - { - __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ - uint16_t : 7; - } DATBL_b; - }; - - union - { - __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting - * Register */ - - struct - { - __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ - uint16_t : 7; - } DATBH_b; - }; - - union - { - __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ - - struct - { - __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ - uint16_t : 7; - } NOMP_b; - }; - __IM uint16_t RESERVED1; - - union - { - __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ - - struct - { - uint8_t : 4; - __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ - __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ - uint8_t : 1; - __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ - } CECEXMD_b; - }; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ - - struct - { - __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ - __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ - uint8_t : 6; - } CECEXMON_b; - }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[10]; - __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ - __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ - - union - { - __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ - - struct - { - __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ - __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ - __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ - __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ - __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ - __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ - __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ - uint8_t : 1; - } CECES_b; - }; - - union - { - __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ - - struct - { - __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ - __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ - __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ - __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ - __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ - uint8_t : 2; - __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ - } CECS_b; - }; - - union - { - __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ - - struct - { - __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ - __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ - __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ - __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ - __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ - __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ - __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ - uint8_t : 1; - } CECFC_b; - }; - - union - { - __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ - - struct - { - __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ - __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ - __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ - __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ - __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ - __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ - } CECCTL0_b; - }; -} R_CEC_Type; /*!< Size = 70 (0x46) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Octa Serial Peripheral Interface (R_OSPI) - */ - -typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ -{ - union - { - __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ - - struct - { - __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ - __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ - uint32_t : 16; - } DCR_b; - }; - - union - { - __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ - - struct - { - __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ - __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ - __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ - __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ - } DAR_b; - }; - - union - { - __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ - - struct - { - __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ - __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ - uint32_t : 3; - __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ - __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ - __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ - __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ - __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ - __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ - __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ - uint32_t : 2; - } DCSR_b; - }; - - union - { - __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ - - struct - { - __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ - __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ - } DSR_b[2]; - }; - - union - { - __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ - - struct - { - __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ - __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ - __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ - __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ - __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ - uint32_t : 4; - } MDTR_b; - }; - - union - { - __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ - - struct - { - __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ - } ACTR_b; - }; - - union - { - __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ - - struct - { - __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ - } ACAR_b[2]; - }; - __IM uint32_t RESERVED[4]; - - union - { - __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ - __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ - __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ - __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ - __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DRCSTR_b; - }; - - union - { - __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting - * Register */ - - struct - { - __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ - __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ - __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ - __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ - __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting - * in PCLKH units */ - __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ - __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ - __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ - __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ - } DWCSTR_b; - }; - - union - { - __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ - - struct - { - uint32_t : 8; - __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ - __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ - __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ - uint32_t : 16; - } DCSTR_b; - }; - - union - { - __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ - - struct - { - __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ - __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ - __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ - __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ - uint32_t : 4; - __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device - * 0 */ - __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device - * 1 */ - __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ - uint32_t : 17; - __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ - } CDSR_b; - }; - - union - { - __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ - - struct - { - __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ - __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ - __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ - __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ - } MDLR_b; - }; - - union - { - __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ - - struct - { - __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ - __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ - __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ - __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ - } MRWCR_b[2]; - }; - - union - { - __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ - - struct - { - __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ - __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ - __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ - __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ - __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ - __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ - __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ - uint32_t : 1; - __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ - __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ - __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ - __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ - __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ - __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ - __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ - uint32_t : 1; - } MRWCSR_b; - }; - - union - { - __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ - - struct - { - __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ - __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ - uint32_t : 16; - } ESR_b; - }; - - union - { - __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ - - struct - { - __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ - } CWNDR_b; - }; - - union - { - __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ - - struct - { - __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ - __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ - __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ - __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ - } CWDR_b; - }; - - union - { - __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ - - struct - { - __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ - __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ - __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ - __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ - } CRR_b; - }; - - union - { - __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ - - struct - { - __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ - __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ - uint32_t : 26; - } ACSR_b; - }; - __IM uint32_t RESERVED1[5]; - - union - { - __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ - - struct - { - __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are - * Low in single continuous write of OctaRAM. */ - uint32_t : 7; - __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 - * are Low in single continuous read of OctaRAM. */ - uint32_t : 7; - } DCSMXR_b; - }; - - union - { - __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating - * size Register */ - - struct - { - __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single - * continuous write of device 0. */ - uint32_t : 5; - __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single - * continuous write of device 1. */ - uint32_t : 5; - } DWSCTSR_b; - }; -} R_OSPI_Type; /*!< Size = 132 (0x84) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 High-Speed Module (R_USB_HS0) - */ - -typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ -{ - union - { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ - - struct - { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ - uint16_t : 7; - } SYSCFG_b; - }; - - union - { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ - - struct - { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; - }; - - union - { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ - - struct - { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; - }; - - union - { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ - - struct - { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; - }; - - union - { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ - - struct - { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller - * Operation */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit - * when switching from device B to device A in OTGmode. If - * the HNPBTOA bit is 1, the internal function controlremains - * in the Suspend state until the HNP processing endseven - * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ - uint16_t : 4; - } DVSTCTR0_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ - - struct - { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; - }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - - union - { - union - { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } CFIFO_b; - }; - - struct - { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or - * write transmit data to the FIFO buffer by accessing these - * bits. */ - } D0FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - union - { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ - - struct - { - __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write - * transmit data to the FIFO buffer by accessing these bits. */ - } D1FIFO_b; - }; - - struct - { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; - }; - - union - { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; - }; - - union - { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; - }; - __IM uint32_t RESERVED6; - - union - { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; - }; - - union - { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; - }; - - union - { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ - - struct - { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; - }; - - union - { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ - - struct - { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can - * be accessed. */ - __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; - }; - - union - { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ - - struct - { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Up2025-07-29 Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; - }; - - union - { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ - - struct - { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ - } INTENB1_b; - }; - __IM uint16_t RESERVED7; - - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BRDYENB_b; - }; - - union - { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ - uint16_t : 6; - } NRDYENB_b; - }; - - union - { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - - struct - { - __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ - uint16_t : 6; - } BEMPENB_b; - }; - - union - { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ - - struct - { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be - * set only in the initial setting (before communications).The - * setting cannot be changed once communication starts. */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency - * can be improved by setting this bit to 1 if no low-speed - * device is connected directly or via FS-HUB to the USB port. */ - uint16_t : 7; - } SOFCFG_b; - }; - - union - { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ - - struct - { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; - }; - - union - { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ - - struct - { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; - }; - - union - { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ - - struct - { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ - } INTSTS1_b; - }; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } BRDYSTS_b; - }; - - union - { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ - uint16_t : 6; - } NRDYSTS_b; - }; - - union - { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ - - struct - { - __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ - uint16_t : 6; - } BEMPSTS_b; - }; - - union - { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ - - struct - { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; - }; - - union - { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ - - struct - { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; - }; - - union - { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ - - struct - { - uint16_t : 8; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; - }; - __IM uint16_t RESERVED9; - - union - { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ - - struct - { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected - * : read-only Host controller selected : read-write */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected - * : read-only Host controller selected : read-write */ - } USBREQ_b; - }; - - union - { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ - - struct - { - __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected - * : read-only Host controller selected : read-write */ - } USBVAL_b; - }; - - union - { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ - - struct - { - __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected - * : read-only Host controller selected : read-write */ - } USBINDX_b; - }; - - union - { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ - - struct - { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected - * : read-only Host controller selected : read-write */ - } USBLENG_b; - }; - - union - { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ - - struct - { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; - }; - - union - { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * destination function device for control transfer when the - * host controller function is selected. */ - } DCPMAXP_b; - }; - - union - { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; - }; - __IM uint16_t RESERVED10; - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ - __IM uint16_t RESERVED11; - - union - { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ - - struct - { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; - }; - - union - { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ - - struct - { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number - * of the selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - uint16_t : 1; - } PIPEBUF_b; - }; - - union - { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ - - struct - { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data - * payload (maximum packet size) for the selected pipe.A size - * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the - * peripheral device when the host controller function is - * selected. */ - } PIPEMAXP_b; - }; - - union - { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ - - struct - { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the - * transfer interval timing for the selected pipe as n-th - * power of 2 of the frame timing. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; - }; - - union - { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ - - struct - { - __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for - * the next transaction of the relevant pipe. */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe - * is being used for the USB bus */ - __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is set for DATA1 */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected - * value of the sequence toggle bit for the next transaction - * of the relevant pipe is cleared to DATA0 */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto - * buffer clear mode for the relevant pipe */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto - * response mode for the relevant pipe. */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO - * buffer status for the relevant pipe in the transmitting - * direction. */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status - * for the relevant pipe. */ - } PIPE_CTR_b[9]; - }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED14[11]; - - union - { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ - - struct - { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; - }; - __IM uint32_t RESERVED15[7]; - - union - { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ - - struct - { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; - }; - - union - { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ - - struct - { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; - }; - __IM uint32_t RESERVED16[15]; - - union - { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ - - struct - { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; - }; - __IM uint16_t RESERVED17; - - union - { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; - }; - - union - { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ - - struct - { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; - }; - - union - { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ - - struct - { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; - }; - - union - { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; - }; - __IM uint32_t RESERVED18; - - union - { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ - - struct - { - __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset - * value for adjusting the terminating resistance. */ - uint16_t : 1; - } PHYTRIM1_b; - }; - - union - { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ - - struct - { - __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ - uint16_t : 1; - } PHYTRIM2_b; - }; - __IM uint32_t RESERVED19[3]; - - union - { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ - - struct - { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; - }; - - union - { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; - }; - - union - { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ - - struct - { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; - }; - - union - { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ - - struct - { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; - }; -} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGTX0) - */ - -typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ -{ - union - { - __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ - __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ - }; -} R_AGTX0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CANFD ECC (R_ECCMB0) - */ - -typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ -{ - union - { - __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ - - struct - { - __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ - __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ - __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ - __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ - __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ - __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ - __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ - uint32_t : 2; - __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag - * Clear */ - __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ - __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ - uint32_t : 2; - __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ - __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ - __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ - uint32_t : 14; - } EC710CTL_b; - }; - - union - { - __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ - uint16_t : 5; - __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ - uint16_t : 6; - __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ - } EC710TMC_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1; - - union - { - __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ - - struct - { - __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ - } EC710TED_b; - }; - - union - { - __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ - - struct - { - __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ - uint32_t : 22; - } EC710EAD0_b; - }; -} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Flash (R_FLAD) - */ - -typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ -{ - __IM uint8_t RESERVED[64]; - - union - { - __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ - - struct - { - __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ - } FCKMHZ_b; - }; -} R_FLAD_Type; /*!< Size = 65 (0x41) */ - -/** @} */ /* End of group Device_Peripheral_peripherals */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ADC0_BASE 0x40170000UL - #define R_ADC1_BASE 0x40170200UL - #define R_PSCU_BASE 0x400E0000UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40083600UL - #define R_CANFD_BASE 0x400B0000UL - #define R_CRC_BASE 0x40108000UL - #define R_CTSU_BASE 0x400D0000UL - #define R_DAC_BASE 0x40171000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40109000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40082000UL - #define R_ETHERC0_BASE 0x40114100UL - #define R_ETHERC_EDMAC_BASE 0x40114000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GPT0_BASE 0x40169000UL - #define R_GPT1_BASE 0x40169100UL - #define R_GPT2_BASE 0x40169200UL - #define R_GPT3_BASE 0x40169300UL - #define R_GPT4_BASE 0x40169400UL - #define R_GPT5_BASE 0x40169500UL - #define R_GPT6_BASE 0x40169600UL - #define R_GPT7_BASE 0x40169700UL - #define R_GPT8_BASE 0x40169800UL - #define R_GPT9_BASE 0x40169900UL - #define R_GPT10_BASE 0x40169A00UL - #define R_GPT11_BASE 0x40169B00UL - #define R_GPT12_BASE 0x40169C00UL - #define R_GPT13_BASE 0x40169D00UL - #define R_GPT_OPS_BASE 0x40169A00UL - #define R_GPT_POEG0_BASE 0x4008A000UL - #define R_GPT_POEG1_BASE 0x4008A100UL - #define R_GPT_POEG2_BASE 0x4008A200UL - #define R_GPT_POEG3_BASE 0x4008A300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x4009F000UL - #define R_IIC1_BASE 0x4009F100UL - #define R_IIC2_BASE 0x4009F200UL - #define R_IWDT_BASE 0x40083200UL - #define R_I3C0_BASE 0x4011F000UL - #define R_I3C1_BASE 0x4011F400UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40084000UL - #define R_PORT0_BASE 0x40080000UL - #define R_PORT1_BASE 0x40080020UL - #define R_PORT2_BASE 0x40080040UL - #define R_PORT3_BASE 0x40080060UL - #define R_PORT4_BASE 0x40080080UL - #define R_PORT5_BASE 0x400800A0UL - #define R_PORT6_BASE 0x400800C0UL - #define R_PORT7_BASE 0x400800E0UL - #define R_PORT8_BASE 0x40080100UL - #define R_PORT9_BASE 0x40080120UL - #define R_PORT10_BASE 0x40080140UL - #define R_PORT11_BASE 0x40080160UL - #define R_PORT12_BASE 0x40080180UL - #define R_PORT13_BASE 0x400801A0UL - #define R_PORT14_BASE 0x400801C0UL - #define R_PFS_BASE 0x40080800UL - #define R_PMISC_BASE 0x40080D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40083000UL - #define R_SCI0_BASE 0x40118000UL - #define R_SCI1_BASE 0x40118100UL - #define R_SCI2_BASE 0x40118200UL - #define R_SCI3_BASE 0x40118300UL - #define R_SCI4_BASE 0x40118400UL - #define R_SCI5_BASE 0x40118500UL - #define R_SCI6_BASE 0x40118600UL - #define R_SCI7_BASE 0x40118700UL - #define R_SCI8_BASE 0x40118800UL - #define R_SCI9_BASE 0x40118900UL - #define R_SDHI0_BASE 0x40092000UL - #define R_SDHI1_BASE 0x40092400UL - #define R_SPI0_BASE 0x4011A000UL - #define R_SPI1_BASE 0x4011A100UL - #define R_SPI2_BASE 0x40072200UL - #define R_SRAM_BASE 0x40002000UL - #define R_SSI0_BASE 0x4009D000UL - #define R_SSI1_BASE 0x4009D100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x400F3000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_WDT_BASE 0x40083400UL - #define R_TZF_BASE 0x40000E00UL - #define R_CACHE_BASE 0x40007000UL - #define R_CPSCU_BASE 0x40008000UL - #define R_CEC_BASE 0x400AC000UL - #define R_OSPI_BASE 0x400A6000UL - #define R_USB_HS0_BASE 0x40111000UL - #define R_AGTX0_BASE 0x400E8000UL - #define R_AGTX1_BASE 0x400E8100UL - #define R_AGTX2_BASE 0x400E8200UL - #define R_AGTX3_BASE 0x400E8300UL - #define R_AGTX4_BASE 0x400E8400UL - #define R_AGTX5_BASE 0x400E8500UL - #define R_AGTX6_BASE 0x400E8600UL - #define R_AGTX7_BASE 0x400E8700UL - #define R_AGTX8_BASE 0x400E8800UL - #define R_AGTX9_BASE 0x400E8900UL - #define R_ECCMB0_BASE 0x4036F200UL - #define R_ECCMB1_BASE 0x4036F300UL - #define R_FLAD_BASE 0x407FC000UL - #define R_WDT1_BASE 0x40044300UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) - #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) - #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) - #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - #define R_TZF ((R_TZF_Type *) R_TZF_BASE) - #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) - #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) - #define R_CEC ((R_CEC_Type *) R_CEC_BASE) - #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) - #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) - #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) - #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) - #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) - #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) - #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) - #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) - #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) - #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) - #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) - #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) - #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) - #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - -/* ========================================= End of section using anonymous unions ========================================= */ - #if defined(__CC_ARM) - #pragma pop - #elif defined(__ICCARM__) - -/* leave anonymous unions enabled */ - #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - -/* anonymous unions are enabled by default */ - #elif defined(__TMS470__) - -/* anonymous unions are enabled by default */ - #elif defined(__TASKING__) - #pragma warning restore - #elif defined(__CSMC__) - -/* anonymous unions are enabled by default */ - #endif - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Cluster Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_clusters - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ SDRAM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SDCCR ========================================================= */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCMOD ========================================================= */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ - #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDAMOD ========================================================= */ - #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ - #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ -/* ======================================================== SDSELF ========================================================= */ - #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ - #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDRFCR ========================================================= */ - #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ - #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ -/* ======================================================== SDRFEN ========================================================= */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ - #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ -/* ========================================================= SDICR ========================================================= */ - #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ - #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SDIR ========================================================== */ - #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ - #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ - #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ - #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ - #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ -/* ========================================================= SDADR ========================================================= */ - #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ - #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ -/* ========================================================= SDTR ========================================================== */ - #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ - #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ - #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ - #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ - #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ - #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ - #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ - #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ -/* ========================================================= SDMOD ========================================================= */ - #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ - #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ -/* ========================================================= SDSR ========================================================== */ - #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ - #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ - #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ - #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ - #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSERRb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ - #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ - #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= IRQEN ========================================================= */ - #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ - #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ DMACDTCERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FLBI ========================================================== */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== MRE0BI ========================================================= */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S2BI ========================================================== */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= S3BI ========================================================== */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== STBYSBI ======================================================== */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= ECBI ========================================================== */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= EOBI ========================================================== */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI0BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================== SPI1BI ========================================================= */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PBBI ========================================================== */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PABI ========================================================== */ - #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PIBI ========================================================== */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ========================================================= PSBI ========================================================== */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= CPU0SAHBI ======================================================= */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSSABT1 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FHBI ========================================================== */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ======================================================== MRC0BI ========================================================= */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S0BI ========================================================== */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ========================================================= S1BI ========================================================== */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ BMSAERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ - #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RW =========================================================== */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ - #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ OAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BUSOAD ========================================================= */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ - #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ - #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ - #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSOADPT ======================================================== */ - #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== MSAOAD ========================================================= */ - #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= MSAPT ========================================================= */ - #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ MBWERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= STAT ========================================================== */ - #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ -/* ========================================================== CLR ========================================================== */ - #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ - #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ - #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CNT ========================================================== */ - #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ - #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ - #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ ELSEGR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== BY =========================================================== */ - #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ - #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ - #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ - #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ - #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ ELSR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== HA =========================================================== */ - #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ - #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ SAR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== L =========================================================== */ - #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ - #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ -/* =========================================================== U =========================================================== */ - #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ - #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ - #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ - #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ REGION ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AC =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ - #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ -/* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ - #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ GROUP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== EN =========================================================== */ - #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= ENPT ========================================================== */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== RPT ========================================================== */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ======================================================== RPT_SEC ======================================================== */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================== CTL ========================================================== */ - #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ - #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ -/* ========================================================== SA =========================================================== */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ - #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== EA =========================================================== */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ - #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ PIN ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= PmnPFS_BY ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ======================================================= PmnPFS_HA ======================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ -/* ======================================================== PmnPFS ========================================================= */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ - #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ - #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ - #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ - #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ - #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ - #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ - #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ - #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ - #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ - #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ - #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PORT ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ VLSEL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== VL1SEL ========================================================= */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ - #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ PMSAR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PMSAR ========================================================= */ - -/* =========================================================================================================================== */ -/* ================ RTCCR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RTCCR ========================================================= */ - #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ - #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ - #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ - #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ - #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ - #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= RSEC ========================================================== */ - #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ - #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMIN ========================================================== */ - #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ - #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ -/* ========================================================== RHR ========================================================== */ - #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ - #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RDAY ========================================================== */ - #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ - #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ -/* ========================================================= RMON ========================================================== */ - #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ PIPE_TR ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== E =========================================================== */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ - #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ - #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ -/* =========================================================== N =========================================================== */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ - #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= AGTCR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTMR1 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ -/* ======================================================== AGTMR2 ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ -/* ===================================================== AGTIOSEL_ALT ====================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ -/* ======================================================== AGTIOC ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTISR ========================================================= */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ -/* ======================================================== AGTCMSR ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ -/* ======================================================= AGTIOSEL ======================================================== */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ - #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ AGT16 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ AGT32 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== AGT ========================================================== */ - #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ - #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMA ========================================================= */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== AGTCMB ========================================================= */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ - #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ - -/** @} */ /* End of group PosMask_clusters */ - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup PosMask_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ADCSR ========================================================= */ - #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ - #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ - #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ - #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ - #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ - #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ - #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ - #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ - #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ - #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSA ========================================================= */ - #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ - #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADS ========================================================= */ - #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ - #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ -/* ========================================================= ADADC ========================================================= */ - #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ - #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ - #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ -/* ========================================================= ADCER ========================================================= */ - #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ - #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ - #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ - #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ - #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ - #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ - #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ - #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ - #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSTRGR ======================================================== */ - #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ - #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ - #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ - #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ -/* ======================================================== ADEXICR ======================================================== */ - #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ - #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ - #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ - #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ - #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ - #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ - #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ - #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ - #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANSB ========================================================= */ - #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ - #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADDBLDR ======================================================== */ - #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ - #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADTSDR ========================================================= */ - #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ - #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADOCDR ========================================================= */ - #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ - #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADRD_RIGHT ======================================================= */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ - #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ -/* ======================================================= ADRD_LEFT ======================================================= */ - #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ - #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ========================================================= ADDR ========================================================== */ - #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ - #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADSHCR ========================================================= */ - #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ - #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ - #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ - #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ - #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ -/* ======================================================== ADDISCR ======================================================== */ - #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ - #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ - #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADSHMSR ======================================================== */ - #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ - #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADACSR ========================================================= */ - #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ - #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ -/* ======================================================== ADGSPCR ======================================================== */ - #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ - #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ - #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ - #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ - #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ -/* ========================================================= ADICR ========================================================= */ - #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ - #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ -/* ======================================================= ADDBLDRA ======================================================== */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ - #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADDBLDRB ======================================================== */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ - #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ -/* ====================================================== ADHVREFCNT ======================================================= */ - #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ - #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ - #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= ADWINMON ======================================================== */ - #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ - #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ - #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ - #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPCR ======================================================== */ - #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ - #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ - #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ - #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ - #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ - #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ - #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCMPANSER ======================================================= */ - #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ - #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ - #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPLER ======================================================== */ - #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ - #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ - #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPANSR ======================================================= */ - #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ - #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCMPLR ======================================================== */ - #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ - #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPDR0 ======================================================== */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ - #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPDR1 ======================================================== */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ - #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADCMPSR ======================================================== */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ - #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPSER ======================================================== */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ - #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ - #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCMPBNSR ======================================================= */ - #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ - #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ - #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ -/* ======================================================= ADWINLLB ======================================================== */ - #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ - #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADWINULB ======================================================== */ - #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ - #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ -/* ======================================================= ADCMPBSR ======================================================== */ - #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ - #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSSTRL ======================================================== */ - #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRT ======================================================== */ - #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTRO ======================================================== */ - #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADSSTR ========================================================= */ - #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ - #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ -/* ======================================================== ADPGACR ======================================================== */ - #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ - #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ - #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ - #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ - #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ - #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ - #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ - #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ - #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ - #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ - #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ - #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ - #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ - #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ - #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ - #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ - #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADRD ========================================================== */ - #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ - #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ -/* ========================================================= ADRST ========================================================= */ - #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ - #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ -/* ====================================================== VREFAMPCNT ======================================================= */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ - #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ - #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ - #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ - #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ - #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCALEXE ======================================================== */ - #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ - #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ - #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ -/* ======================================================== ADANIM ========================================================= */ - #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ - #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGAGS0 ======================================================== */ - #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ - #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ - #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ - #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ - #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= ADPGADCR0 ======================================================= */ - #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ - #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ - #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ - #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ - #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ - #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ - #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ - #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ - #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ADREF ========================================================= */ - #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ - #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ - #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ -/* ======================================================== ADEXREF ======================================================== */ - #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ - #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADAMPOFF ======================================================== */ - #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ - #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ -/* ======================================================== ADTSTPR ======================================================== */ - #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ - #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ - #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================= ADDDACER ======================================================== */ - #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ - #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ - #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ - #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ - #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADEXTSTR ======================================================== */ - #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ - #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ - #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ - #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ - #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ - #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ - #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ -/* ======================================================== ADTSTRA ======================================================== */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ - #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ - #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ - #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ - #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ - #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ - #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ -/* ======================================================== ADTSTRB ======================================================== */ - #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ - #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ -/* ======================================================== ADTSTRC ======================================================== */ - #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ - #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ - #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ADTSTRD ======================================================== */ - #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ - #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR0 ======================================================= */ - #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ - #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ - #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ - #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ - #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ - #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ - #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR1 ======================================================= */ - #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ - #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ - #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ - #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ - #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ - #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ - #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ -/* ======================================================= ADSWTSTR2 ======================================================= */ - #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ - #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ - #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ - #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ - #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ - #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ - #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ - #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ - #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ - #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ - #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ -/* ======================================================== ADSWCR ========================================================= */ - #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ - #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ - #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ -/* ======================================================== ADGSCS ========================================================= */ - #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ - #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ - #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ - #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ -/* ========================================================= ADSER ========================================================= */ - #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ - #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ -/* ======================================================== ADBUF0 ========================================================= */ - #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF1 ========================================================= */ - #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF2 ========================================================= */ - #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF3 ========================================================= */ - #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF4 ========================================================= */ - #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF5 ========================================================= */ - #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF6 ========================================================= */ - #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF7 ========================================================= */ - #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF8 ========================================================= */ - #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF9 ========================================================= */ - #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF10 ======================================================== */ - #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF11 ======================================================== */ - #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF12 ======================================================== */ - #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF13 ======================================================== */ - #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF14 ======================================================== */ - #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUF15 ======================================================== */ - #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ - #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ -/* ======================================================== ADBUFEN ======================================================== */ - #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ - #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ -/* ======================================================= ADBUFPTR ======================================================== */ - #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ - #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ - #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ - #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS0 ======================================================= */ - #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADPGADBS1 ======================================================= */ - #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ - #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ -/* ======================================================= ADREFMON ======================================================== */ - #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ - #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ - #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ - #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PSARB ========================================================= */ - #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ - #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ - #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ - #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ - #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ - #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ - #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ - #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ - #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ - #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ - #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ - #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ - #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ - #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ - #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ - #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ - #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ - #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ - #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ - #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ - #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ - #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ - #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ - #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ - #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ - #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ - #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ - #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARC ========================================================= */ - #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ - #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ - #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ - #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ - #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ - #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ - #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ - #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ - #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ - #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ - #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARD ========================================================= */ - #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ - #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ - #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ - #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ - #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ - #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ - #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ - #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ - #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ - #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ - #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ - #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ - #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ - #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ - #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ - #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ - #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ - #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ - #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ -/* ========================================================= PSARE ========================================================= */ - #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ - #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ - #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ - #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ - #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ - #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ - #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ - #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ - #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ - #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ - #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ - #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ - #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ - #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ - #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ - #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ - #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ -/* ========================================================= MSSAR ========================================================= */ - #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ - #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ - #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ - #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ - #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ - #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ - #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFSAMONA ======================================================== */ - #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ - #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ -/* ======================================================= CFSAMONB ======================================================== */ - #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ - #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ -/* ======================================================== DFSAMON ======================================================== */ - #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ - #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ -/* ======================================================== SSAMONA ======================================================== */ - #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ - #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ -/* ======================================================== SSAMONB ======================================================== */ - #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ - #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DLMMON ========================================================= */ - #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ - #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSMABT ======================================================== */ - #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSDIVBYP ======================================================= */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ - #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ - #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ - #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ -/* ======================================================= BUSTHRPUT ======================================================= */ - #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ - #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CACR0 ========================================================= */ - #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ - #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR1 ========================================================= */ - #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ - #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ - #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ - #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ -/* ========================================================= CACR2 ========================================================= */ - #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ - #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ - #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ - #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ - #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ - #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ - #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ -/* ========================================================= CAICR ========================================================= */ - #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ - #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ - #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ - #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ - #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ - #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ - #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ - #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ -/* ========================================================= CASTR ========================================================= */ - #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ - #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ - #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ - #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ - #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ -/* ======================================================== CAULVR ========================================================= */ - #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ - #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CALLVR ========================================================= */ - #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ - #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ -/* ======================================================== CACNTBR ======================================================== */ - #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ - #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CRCCR0 ========================================================= */ - #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ - #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ - #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ - #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ -/* ======================================================== CRCCR1 ========================================================= */ - #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ - #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ - #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ - #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ -/* ======================================================== CRCDIR ========================================================= */ - #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ - #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDIR_BY ======================================================= */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ - #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCDOR ========================================================= */ - #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ - #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CRCDOR_HA ======================================================= */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ - #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ -/* ======================================================= CRCDOR_BY ======================================================= */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ - #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ -/* ======================================================== CRCSAR ========================================================= */ - #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ - #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTSUCR0 ======================================================== */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ - #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ - #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ - #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ - #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ - #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ - #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ -/* ======================================================== CTSUCR1 ======================================================== */ - #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ - #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ - #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ - #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ - #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ - #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ - #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUSDPRS ======================================================= */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ - #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ - #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ - #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSST ======================================================== */ - #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ - #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ -/* ======================================================= CTSUMCH0 ======================================================== */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ - #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUMCH1 ======================================================== */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ - #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ -/* ======================================================= CTSUCHAC ======================================================== */ - #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUCHTRC ======================================================= */ - #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUDCLKC ======================================================= */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ - #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ - #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== CTSUST ========================================================= */ - #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ - #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ - #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ - #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ - #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ - #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ -/* ======================================================== CTSUSSC ======================================================== */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ - #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ -/* ======================================================== CTSUSO0 ======================================================== */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ - #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ - #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ - #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ -/* ======================================================== CTSUSO1 ======================================================== */ - #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ - #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ - #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ - #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ -/* ======================================================== CTSUSC ========================================================= */ - #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ - #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ -/* ======================================================== CTSURC ========================================================= */ - #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ - #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ -/* ======================================================= CTSUERRS ======================================================== */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ - #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ - #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ - #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ - #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ - #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ - #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ -/* ======================================================= CTSUTRMR ======================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DACR ========================================================== */ - #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ - #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ - #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ - #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ -/* ========================================================= DADR ========================================================== */ - #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ - #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DADPR ========================================================= */ - #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ - #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADSCR ======================================================== */ - #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ - #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ -/* ======================================================= DAVREFCR ======================================================== */ - #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ - #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ -/* ========================================================= DAPC ========================================================== */ - #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ - #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== DAAMPCR ======================================================== */ - #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ - #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DAASWCR ======================================================== */ - #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ - #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ - #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ -/* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ - #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== DBGSTR ========================================================= */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ - #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ -/* ======================================================= DBGSTOPCR ======================================================= */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ - #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ -/* ======================================================= FSBLSTAT ======================================================== */ - #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ - #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ - #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ -/* ========================================================= DMCTL ========================================================= */ - #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ - #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ - #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ - #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ -/* ======================================================== DMECHR ========================================================= */ - #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ - #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ - #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ - #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ - #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ - #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ -/* ========================================================= DELSR ========================================================= */ - #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DMSAR ========================================================= */ - #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ - #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMDAR ========================================================= */ - #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ - #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCRA ========================================================= */ - #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ - #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ - #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ - #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMCRB ========================================================= */ - #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ - #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ - #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMTMD ========================================================= */ - #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ - #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ - #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ - #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ - #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ - #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ -/* ========================================================= DMINT ========================================================= */ - #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ - #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ - #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ - #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ - #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ - #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMAMD ========================================================= */ - #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ - #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ - #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ - #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ - #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ - #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ - #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ - #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ - #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ -/* ========================================================= DMOFR ========================================================= */ - #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ - #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMCNT ========================================================= */ - #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ - #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ -/* ========================================================= DMREQ ========================================================= */ - #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ - #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ - #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSTS ========================================================= */ - #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ - #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ - #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ - #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ - #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ -/* ========================================================= DMSRR ========================================================= */ -/* ========================================================= DMDRR ========================================================= */ -/* ========================================================= DMSBS ========================================================= */ - #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ - #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ - #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMDBS ========================================================= */ - #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ - #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ - #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ - #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ -/* ========================================================= DMBWR ========================================================= */ - #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ - #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DOCR ========================================================== */ - #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ - #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ - #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ - #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ - #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ - #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ -/* ========================================================= DODIR ========================================================= */ - #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ - #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ -/* ========================================================= DODSR ========================================================= */ - #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ - #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= DTCADMOD ======================================================== */ - #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ - #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ -/* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ -/* ======================================================= DTCCR_SEC ======================================================= */ - #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ -/* ====================================================== DTCVBR_SEC ======================================================= */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DTCDISP ======================================================== */ - #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ - #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DTEVR ========================================================= */ - #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ - #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ - #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ - #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ - #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ - #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCIBR ========================================================= */ - #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ - #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ -/* ========================================================= DTCOR ========================================================= */ - #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ - #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ -/* ======================================================== DTCSQE ========================================================= */ - #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ - #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ - #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARA ======================================================== */ - #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ - #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ - #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ - #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARB ======================================================== */ - #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ - #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ - #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ - #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ - #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ - #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ - #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ - #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ - #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ - #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ - #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ - #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ - #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ - #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ - #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ - #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ - #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ -/* ======================================================== ELCSARC ======================================================== */ - #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ - #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ - #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ - #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ - #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ECMR ========================================================== */ - #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ - #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ - #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ - #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ - #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ - #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ - #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ - #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ - #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ - #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ - #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ - #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ - #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ -/* ========================================================= RFLR ========================================================== */ - #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ - #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ - #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ - #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ - #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ - #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ - #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ -/* ======================================================== ECSIPR ========================================================= */ - #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ - #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ - #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ - #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ - #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ - #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ -/* ========================================================== PIR ========================================================== */ - #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ - #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ - #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ - #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ - #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ - #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ -/* ========================================================== PSR ========================================================== */ - #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ - #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ -/* ========================================================= RDMLR ========================================================= */ - #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ - #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ -/* ========================================================= IPGR ========================================================== */ - #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ - #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ -/* ========================================================== APR ========================================================== */ - #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ - #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ -/* ========================================================== MPR ========================================================== */ - #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ - #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFCF ========================================================== */ - #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ - #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ -/* ======================================================== TPAUSER ======================================================== */ - #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ - #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ -/* ======================================================= TPAUSECR ======================================================== */ -/* ========================================================= BCFRR ========================================================= */ - #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ - #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ -/* ========================================================= MAHR ========================================================== */ - #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ - #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MALR ========================================================== */ - #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ - #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ -/* ========================================================= TROCR ========================================================= */ - #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ - #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CDCR ========================================================== */ -/* ========================================================= LCCR ========================================================== */ - #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ - #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CNDCR ========================================================= */ - #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ - #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CEFCR ========================================================= */ - #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ - #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= FRECR ========================================================= */ - #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ - #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TSFRCR ========================================================= */ - #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ - #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== TLFRCR ========================================================= */ - #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ - #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RFCR ========================================================== */ - #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ - #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= MAFCR ========================================================= */ - #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ - #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= EDMR ========================================================== */ - #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ - #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ - #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ - #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDTRR ========================================================= */ - #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ - #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ -/* ========================================================= EDRRR ========================================================= */ - #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ - #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ -/* ========================================================= TDLAR ========================================================= */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDLAR ========================================================= */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= EESR ========================================================== */ - #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ - #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ - #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ - #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ - #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ - #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ - #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ - #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ - #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ - #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ - #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ - #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ - #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ - #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ - #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ - #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ - #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ - #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ - #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ - #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ - #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ - #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ - #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ -/* ======================================================== EESIPR ========================================================= */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ - #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ - #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ - #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ - #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ - #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ - #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ - #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ - #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ - #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ - #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ - #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ - #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ - #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ - #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ - #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ - #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ - #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ - #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ - #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ - #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ - #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ - #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ -/* ======================================================== TRSCER ========================================================= */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ - #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ - #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ -/* ========================================================= RMFCR ========================================================= */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ - #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= TFTR ========================================================== */ - #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ - #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ -/* ========================================================== FDR ========================================================== */ - #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ - #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ - #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ - #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ -/* ========================================================= RMCR ========================================================== */ - #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ - #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ -/* ========================================================= TFUCR ========================================================= */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ - #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ -/* ========================================================= RFOCR ========================================================= */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ - #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ -/* ========================================================= IOSR ========================================================== */ - #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ - #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ -/* ========================================================= FCFTR ========================================================= */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ - #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ - #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ -/* ======================================================== RPADIR ========================================================= */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ - #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ - #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ -/* ========================================================= TRIMD ========================================================= */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ - #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ - #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ -/* ========================================================= RBWAR ========================================================= */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ - #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= RDFAR ========================================================= */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TBRAR ========================================================= */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ - #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= TDFAR ========================================================= */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ - #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ - -/* ====================================================== FACI_CMD16 ======================================================= */ -/* ======================================================= FACI_CMD8 ======================================================= */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ -/* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ -/* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FMEPROT ======================================================== */ - #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ - #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT0 ======================================================== */ - #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ - #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== FBPROT1 ======================================================== */ - #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ - #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ - #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ - #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ - #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ - #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ -/* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ -/* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ -/* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ -/* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ -/* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ -/* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== FBCADDR ======================================================== */ - #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ - #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ -/* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ -/* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ -/* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ -/* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ -/* ======================================================= FCNTSELR ======================================================== */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ - #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ -/* ====================================================== FCNTDATAR0 ======================================================= */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FCNTDATAR1 ======================================================= */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ - #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ -/* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ -/* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ -/* ========================================================= FSAR ========================================================== */ - #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ - #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ - #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ - #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ - #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ - #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ - #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ - #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= GTWP ========================================================== */ - #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ - #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ - #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ - #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ - #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTR ========================================================= */ - #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ - #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSTP ========================================================= */ - #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ - #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCLR ========================================================= */ - #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ - #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTSSR ========================================================= */ - #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ - #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ - #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ - #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ - #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ - #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ - #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ - #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ - #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ - #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ - #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ - #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ - #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTPSR ========================================================= */ - #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ - #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ - #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ - #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ - #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ - #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ - #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ - #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ - #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ - #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ - #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ - #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ - #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCSR ========================================================= */ - #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ - #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ - #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ - #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ - #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ - #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ - #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ - #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ - #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ - #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ - #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ - #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ - #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ - #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ - #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTUPSR ========================================================= */ - #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ - #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ - #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ - #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ - #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ - #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ - #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ - #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ - #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ - #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ - #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ - #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ - #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTDNSR ========================================================= */ - #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ - #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ - #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ - #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ - #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ - #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ - #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ - #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ - #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ - #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ - #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ - #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ - #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICASR ======================================================== */ - #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ - #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ - #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ - #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ - #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ - #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ - #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ - #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ - #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ - #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ - #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ - #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ - #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTICBSR ======================================================== */ - #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ - #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ - #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ - #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ - #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ - #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ - #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ - #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ - #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ - #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ - #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ - #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ - #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ - #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ - #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ - #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ - #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ - #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ - #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ - #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ - #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ - #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ - #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ -/* ======================================================= GTUDDTYC ======================================================== */ - #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ - #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ - #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ - #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ - #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ - #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ - #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ - #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ - #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ - #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ -/* ========================================================= GTIOR ========================================================= */ - #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ - #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ - #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ - #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ - #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ - #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ - #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ - #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ - #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ - #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ - #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ - #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ - #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ - #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ - #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ - #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ - #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ - #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ - #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTINTAD ======================================================== */ - #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ - #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ - #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ - #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ - #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ - #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ - #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ - #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ - #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ - #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ - #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ - #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ -/* ========================================================= GTST ========================================================== */ - #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ - #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ - #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ - #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ - #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ - #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ - #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ - #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ - #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ - #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ - #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ - #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ - #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ - #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ - #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ - #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ - #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ - #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ - #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ - #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTBER ========================================================= */ - #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ - #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ - #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ - #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ - #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ - #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ - #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ - #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ - #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ - #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ - #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ - #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ - #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ - #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ -/* ========================================================= GTITC ========================================================= */ - #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ - #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ - #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ - #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ - #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ - #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ - #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ - #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ - #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ - #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ - #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ -/* ========================================================= GTCNT ========================================================= */ - #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ - #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTCCR ========================================================= */ - #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ - #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPR ========================================================== */ - #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ - #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTPBR ========================================================= */ - #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ - #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTPDBR ========================================================= */ - #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ - #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRA ======================================================== */ - #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ - #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTADTRB ======================================================== */ - #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ - #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRA ======================================================== */ - #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ - #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTBRB ======================================================== */ - #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ - #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRA ======================================================= */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ - #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= GTADTDBRB ======================================================= */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ - #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== GTDTCR ========================================================= */ - #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ - #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ - #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ - #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ - #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ -/* ========================================================= GTDVU ========================================================= */ - #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDVD ========================================================= */ - #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ - #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBU ========================================================= */ - #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ - #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTDBD ========================================================= */ - #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ - #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= GTSOS ========================================================= */ - #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ - #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ -/* ======================================================== GTSOTR ========================================================= */ - #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ - #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ -/* ======================================================== GTADSMR ======================================================== */ - #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ - #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ - #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ - #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ - #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTEITC ========================================================= */ - #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ - #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ - #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ - #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ - #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ - #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ - #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ - #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= GTEITLI1 ======================================================== */ - #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ - #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ - #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ - #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ - #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ - #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ - #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ - #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ - #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ -/* ======================================================= GTEITLI2 ======================================================== */ - #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ - #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ - #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ -/* ======================================================== GTEITLB ======================================================== */ - #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ - #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ - #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ - #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ - #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ - #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ - #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ - #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ -/* ======================================================== GTICLF ========================================================= */ - #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ - #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ - #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ - #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ - #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ - #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ -/* ========================================================= GTPC ========================================================== */ - #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ - #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ - #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ - #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ -/* ======================================================= GTADCMSC ======================================================== */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ - #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ - #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ - #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ - #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ - #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ -/* ======================================================= GTADCMSS ======================================================== */ - #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ - #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ - #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ - #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ - #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ -/* ======================================================== GTSECSR ======================================================== */ - #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ - #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ - #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ - #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ - #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ - #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ - #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ - #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ - #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ - #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ - #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ -/* ======================================================== GTSECR ========================================================= */ - #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ - #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ - #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ - #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ - #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ - #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ - #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ - #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ - #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ - #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ - #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ - #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ - #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ -/* ======================================================== GTBER2 ========================================================= */ - #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ - #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ - #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ - #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ - #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ - #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ - #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ - #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ - #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ - #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ - #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ - #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ - #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ - #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ - #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ - #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ - #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ - #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ - #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ - #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ - #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ -/* ======================================================== GTOLBR ========================================================= */ - #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ - #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ - #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ - #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ -/* ======================================================== GTICCR ========================================================= */ - #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ - #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ - #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ - #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ - #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ - #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ - #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ - #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ - #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ - #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ - #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ - #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ - #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ - #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ - #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ - #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ - #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ - #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ - #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ - #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ - #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ - #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ - #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= OPSCR ========================================================= */ - #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ - #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ - #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ - #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ - #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ - #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ - #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ - #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ - #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ - #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ - #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ - #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ - #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ - #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ - #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ - #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ - #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ - #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ -/* ======================================================== GTONCWP ======================================================== */ - #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ - #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== GTONCCR ======================================================== */ - #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ - #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ - #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ - #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ - #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= IRQCR ========================================================= */ - #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ - #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ - #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ - #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ - #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ - #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ -/* ========================================================= NMISR ========================================================= */ - #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ - #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ - #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ - #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ - #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ - #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ - #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ - #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ - #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ - #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ - #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ - #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ - #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ - #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ - #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ - #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ -/* ========================================================= NMIER ========================================================= */ - #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ - #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ - #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ - #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ - #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ - #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ - #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ - #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ - #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ - #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ - #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ - #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ - #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ - #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ - #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ -/* ======================================================== NMICLR ========================================================= */ - #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ - #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ - #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ - #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ - #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ - #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ - #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ - #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ - #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ - #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ - #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ - #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ - #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ - #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ - #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ -/* ========================================================= NMICR ========================================================= */ - #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ - #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ - #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ - #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ - #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ - #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ -/* ========================================================= IELSR ========================================================= */ - #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ - #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ - #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DELSR ========================================================= */ - #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ - #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ - #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ - #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ -/* ======================================================== SELSR0 ========================================================= */ - #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ - #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ -/* ========================================================= WUPEN ========================================================= */ - #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ - #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ - #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ - #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ - #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ - #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ - #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ - #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ - #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ - #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ - #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ - #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ - #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ - #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ - #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ - #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ - #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN1 ========================================================= */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ - #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ - #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ - #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ -/* ======================================================== WUPEN2 ========================================================= */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ - #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ - #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ - #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ - #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ - #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IELEN ========================================================= */ - #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ - #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ - #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ - #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ICCR1 ========================================================= */ - #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ - #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ - #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ - #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ - #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ - #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ - #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ - #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ - #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ -/* ========================================================= ICCR2 ========================================================= */ - #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ - #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ - #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ - #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ - #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ - #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ - #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR1 ========================================================= */ - #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ - #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ - #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ - #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ -/* ========================================================= ICMR2 ========================================================= */ - #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ - #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ - #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ - #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ - #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ - #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ - #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ -/* ========================================================= ICMR3 ========================================================= */ - #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ - #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ - #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ - #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ - #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ - #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ - #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ - #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ -/* ========================================================= ICFER ========================================================= */ - #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ - #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ - #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ - #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ - #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ - #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ - #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ - #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ - #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSER ========================================================= */ - #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ - #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ - #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ - #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ - #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ - #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ - #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ -/* ========================================================= ICIER ========================================================= */ - #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ - #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ - #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ - #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ - #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ - #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ - #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ - #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR1 ========================================================= */ - #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ - #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ - #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ - #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ - #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ - #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ - #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= ICSR2 ========================================================= */ - #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ - #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ - #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ - #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ - #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ - #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ - #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ -/* ========================================================= ICBRL ========================================================= */ - #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ - #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICBRH ========================================================= */ - #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ - #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ -/* ========================================================= ICDRT ========================================================= */ - #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ - #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ -/* ========================================================= ICDRR ========================================================= */ - #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ - #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ -/* ========================================================= ICWUR ========================================================= */ - #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ - #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ - #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ - #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ - #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ - #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICWUR2 ========================================================= */ - #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ - #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ - #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ - #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ - #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== IWDTRR ========================================================= */ - #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ - #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ -/* ======================================================== IWDTCR ========================================================= */ - #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ======================================================== IWDTSR ========================================================= */ - #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== IWDTRCR ======================================================== */ - #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= IWDTCSTPR ======================================================= */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PRTS ========================================================== */ - #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ - #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ -/* ========================================================= CECTL ========================================================= */ - #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ - #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ -/* ========================================================= BCTL ========================================================== */ - #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ - #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ - #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ - #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ - #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ - #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ - #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSDVAD ========================================================= */ - #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ - #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ - #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTCTL ========================================================= */ - #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ - #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ - #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ - #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ - #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ - #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ - #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ - #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ - #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ - #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ - #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ - #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ - #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ - #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ -/* ========================================================= PRSST ========================================================= */ - #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ - #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ - #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ - #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ -/* ========================================================= INST ========================================================== */ - #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ - #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ -/* ========================================================= INSTE ========================================================= */ - #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ - #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ -/* ========================================================= INIE ========================================================== */ - #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ - #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== INSTFC ========================================================= */ - #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ - #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= DVCT ========================================================== */ - #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ - #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ -/* ======================================================== IBINCTL ======================================================== */ - #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ - #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ - #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ - #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ -/* ========================================================= BFCTL ========================================================= */ - #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ - #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ - #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ - #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ - #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ - #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ - #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ - #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ -/* ========================================================= SVCTL ========================================================= */ - #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ - #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ - #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ - #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ - #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ - #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ -/* ======================================================= REFCKCTL ======================================================== */ - #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ - #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ -/* ========================================================= STDBR ========================================================= */ - #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ - #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ - #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ - #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ - #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ - #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ -/* ========================================================= EXTBR ========================================================= */ - #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ - #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ - #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ - #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ - #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ - #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ -/* ======================================================== BFRECDT ======================================================== */ - #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ - #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BAVLCDT ======================================================== */ - #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ - #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ -/* ======================================================== BIDLCDT ======================================================== */ - #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ - #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== OUTCTL ========================================================= */ - #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ - #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ - #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ - #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ - #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ - #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ - #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ - #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ - #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ -/* ========================================================= INCTL ========================================================= */ - #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ - #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ - #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ - #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ -/* ======================================================== TMOCTL ========================================================= */ - #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ - #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ - #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ - #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ - #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ - #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ - #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ -/* ========================================================= WUCTL ========================================================= */ - #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ - #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ - #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ - #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ - #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ -/* ======================================================== ACKCTL ========================================================= */ - #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ - #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ - #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ - #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ - #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTRCTL ======================================================== */ - #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ - #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ - #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ -/* ======================================================= SCSTLCTL ======================================================== */ - #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ - #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ - #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ - #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ - #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ - #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ - #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ - #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SVTDLG0 ======================================================== */ - #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ - #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= STCTL ========================================================= */ - #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ - #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ -/* ========================================================= ATCTL ========================================================= */ - #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ - #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ - #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ - #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ - #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ - #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ -/* ========================================================= ATTRG ========================================================= */ - #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ - #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== ATCCNTE ======================================================== */ - #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ - #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ -/* ======================================================== CNDCTL ========================================================= */ - #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ - #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ - #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ - #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ - #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ -/* ======================================================== NCMDQP ========================================================= */ -/* ======================================================== NRSPQP ========================================================= */ -/* ======================================================== NTDTBP0 ======================================================== */ -/* ======================================================== NIBIQP ========================================================= */ -/* ========================================================= NRSQP ========================================================= */ -/* ======================================================== HCMDQP ========================================================= */ - #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ - #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HRSPQP ========================================================= */ - #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ - #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== HTDTBP ========================================================= */ - #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ - #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== NQTHCTL ======================================================== */ - #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ - #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ - #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= NTBTHCTL0 ======================================================= */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ======================================================= NRQTHCTL ======================================================== */ - #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ - #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ -/* ======================================================== HQTHCTL ======================================================== */ - #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ - #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ - #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ -/* ======================================================= HTBTHCTL ======================================================== */ - #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ - #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ - #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ - #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ - #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ -/* ========================================================== BST ========================================================== */ - #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ - #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ - #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ - #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ - #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ - #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ - #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ - #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ - #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTE ========================================================== */ - #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ - #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ - #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ - #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ - #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ - #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ - #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ - #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ - #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ -/* ========================================================== BIE ========================================================== */ - #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ - #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ - #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ - #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ - #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ - #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ - #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ - #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ - #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= BSTFC ========================================================= */ - #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ - #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ - #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ - #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ - #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ - #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ - #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ - #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ - #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= NTST ========================================================== */ - #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ - #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ - #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ - #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ - #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ -/* ========================================================= NTSTE ========================================================= */ - #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ - #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ - #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ - #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ - #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ -/* ========================================================= NTIE ========================================================== */ - #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ - #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ - #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ - #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ - #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ -/* ======================================================== NTSTFC ========================================================= */ - #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ - #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ - #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ - #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ - #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ -/* ========================================================= HTST ========================================================== */ - #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ - #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ - #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ - #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ - #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ - #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ - #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ -/* ========================================================= HTSTE ========================================================= */ - #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ - #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ - #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ - #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ - #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ - #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ - #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ -/* ========================================================= HTIE ========================================================== */ - #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ - #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ - #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ - #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ - #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ - #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ - #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ -/* ======================================================== HTSTFC ========================================================= */ - #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ - #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ - #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ - #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ - #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ - #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ - #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ - #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ -/* ========================================================= BCST ========================================================== */ - #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ - #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ - #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ - #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ - #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ -/* ========================================================= SVST ========================================================== */ - #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ - #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ - #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ - #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ - #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ - #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ -/* ========================================================= WUST ========================================================== */ - #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ - #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ -/* ======================================================== MRCCPT ========================================================= */ - #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ - #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DATBAS0 ======================================================== */ - #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS1 ======================================================== */ - #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS2 ======================================================== */ - #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS3 ======================================================== */ - #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS4 ======================================================== */ - #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS5 ======================================================== */ - #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS6 ======================================================== */ - #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================== DATBAS7 ======================================================== */ - #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ - #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ - #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ - #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ - #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ - #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ - #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ - #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ - #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ - #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= EXDATBAS ======================================================== */ - #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ - #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ - #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ - #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ - #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ - #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ - #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ - #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ -/* ======================================================= SDATBAS0 ======================================================== */ - #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS1 ======================================================== */ - #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================= SDATBAS2 ======================================================== */ - #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ - #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ - #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ - #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ - #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ - #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ -/* ======================================================== MSDCT0 ========================================================= */ - #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT1 ========================================================= */ - #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT2 ========================================================= */ - #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT3 ========================================================= */ - #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT4 ========================================================= */ - #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT5 ========================================================= */ - #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT6 ========================================================= */ - #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================== MSDCT7 ========================================================= */ - #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ - #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ - #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ - #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ - #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ - #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ - #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ - #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ -/* ========================================================= SVDCT ========================================================= */ - #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ - #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ - #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ - #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ - #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ - #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ - #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ - #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ -/* ======================================================= SDCTPIDL ======================================================== */ -/* ======================================================= SDCTPIDH ======================================================== */ -/* ======================================================== SVDVAD0 ======================================================== */ - #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD1 ======================================================== */ - #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== SVDVAD2 ======================================================== */ - #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ - #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ - #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ - #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ - #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ - #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ - #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ -/* ======================================================== CSECMD ========================================================= */ - #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ - #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ - #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ - #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ -/* ======================================================== CEACTST ======================================================== */ - #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ - #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CMWLG ========================================================= */ - #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ - #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ -/* ========================================================= CMRLG ========================================================= */ - #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ - #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ - #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ - #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ -/* ======================================================== CETSTMD ======================================================== */ - #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ - #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ -/* ======================================================== CGDVST ========================================================= */ - #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ - #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ - #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ - #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ - #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ - #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ - #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ -/* ======================================================== CMDSPW ========================================================= */ - #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ - #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPR ========================================================= */ - #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ - #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ - #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ - #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ -/* ======================================================== CMDSPT ========================================================= */ - #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ - #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ - #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ - #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ -/* ========================================================= CETSM ========================================================= */ - #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ - #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ - #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ - #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ - #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ - #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ - #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ -/* ========================================================= CETSS ========================================================= */ - #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ - #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ - #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ - #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ - #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ - #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ -/* ======================================================= CGHDRCAP ======================================================== */ - #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ - #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ - #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ - #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ - #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== BITCNT ========================================================= */ - #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ - #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ - #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ - #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ -/* ======================================================== NQSTLV ========================================================= */ - #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ - #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ - #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ - #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================= NDBSTLV0 ======================================================== */ - #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================= NRSQSTLV ======================================================== */ - #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ - #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HQSTLV ========================================================= */ - #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ - #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ - #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ -/* ======================================================== HDBSTLV ======================================================== */ - #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ - #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ - #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ - #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ -/* ======================================================== PRSTDBG ======================================================== */ - #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ - #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ - #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ - #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ - #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ - #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ -/* ======================================================= MSERRCNT ======================================================== */ - #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ - #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ -/* ======================================================== SC1CPT ========================================================= */ - #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ - #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ -/* ======================================================== SC2CPT ========================================================= */ - #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ - #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== OAD ========================================================== */ - #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ========================================================= OADPT ========================================================= */ - #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== MSTPCRA ======================================================== */ - #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRB ======================================================== */ - #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ - #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRC ======================================================== */ - #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ - #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRD ======================================================== */ - #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ - #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRE ======================================================== */ - #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ - #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ -/* ======================================================= LSMRWDIS ======================================================== */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ - #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ - #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ - #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ - #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ - #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PCNTR1 ========================================================= */ - #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ - #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PODR ========================================================== */ - #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ - #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ -/* ========================================================== PDR ========================================================== */ - #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ - #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR2 ========================================================= */ - #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ - #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EIDR ========================================================== */ - #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ - #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ -/* ========================================================= PIDR ========================================================== */ - #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ - #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR3 ========================================================= */ - #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ - #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= PORR ========================================================== */ - #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ - #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ -/* ========================================================= POSR ========================================================== */ - #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ - #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ -/* ======================================================== PCNTR4 ========================================================= */ - #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ - #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ - #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= EORR ========================================================== */ - #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ - #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ -/* ========================================================= EOSR ========================================================== */ - #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ - #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PFENET ========================================================= */ - #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ - #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ - #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ - #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPR ========================================================== */ - #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ========================================================= PWPRS ========================================================= */ - #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ - #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ - #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ - #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ -/* ======================================================== PRWCNTR ======================================================== */ - #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ - #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SFMSMD ========================================================= */ - #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ - #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ - #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ - #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ - #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ - #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ - #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ - #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ - #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ - #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ - #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ -/* ======================================================== SFMSSC ========================================================= */ - #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ - #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ - #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ - #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSKC ========================================================= */ - #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ - #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ - #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMSST ========================================================= */ - #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ - #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ - #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ - #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ -/* ======================================================== SFMCOM ========================================================= */ - #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ - #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMCMD ========================================================= */ - #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ - #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCST ========================================================= */ - #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ - #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ - #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMSIC ========================================================= */ - #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ - #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ -/* ======================================================== SFMSAC ========================================================= */ - #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ - #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ - #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMSDC ========================================================= */ - #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ - #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ - #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ - #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ - #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ - #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ -/* ======================================================== SFMSPC ========================================================= */ - #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ - #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ - #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ - #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ -/* ======================================================== SFMPMD ========================================================= */ - #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ - #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ -/* ======================================================== SFMCNT1 ======================================================== */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ - #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== R64CNT ========================================================= */ - #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ - #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ - #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ - #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ -/* ========================================================= BCNT0 ========================================================= */ - #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ - #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECCNT ======================================================== */ - #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT1 ========================================================= */ - #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ - #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINCNT ======================================================== */ - #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT2 ========================================================= */ - #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ - #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ -/* ======================================================== RHRCNT ========================================================= */ - #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ========================================================= BCNT3 ========================================================= */ - #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ - #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ -/* ======================================================== RWKCNT ========================================================= */ - #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================== RDAYCNT ======================================================== */ - #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RMONCNT ======================================================== */ - #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== RYRCNT ========================================================= */ - #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT0AR ======================================================== */ - #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ - #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RSECAR ========================================================= */ - #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ - #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ - #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT1AR ======================================================== */ - #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ - #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ -/* ======================================================== RMINAR ========================================================= */ - #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ - #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ - #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ - #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT2AR ======================================================== */ - #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ - #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RHRAR ========================================================= */ - #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ - #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ - #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ - #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================== BCNT3AR ======================================================== */ - #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ - #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ -/* ========================================================= RWKAR ========================================================= */ - #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ - #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ -/* ======================================================= BCNT0AER ======================================================== */ - #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RDAYAR ========================================================= */ - #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ - #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ - #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ - #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT1AER ======================================================== */ - #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RMONAR ========================================================= */ - #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ - #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ - #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ - #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT2AER ======================================================== */ - #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ========================================================= RYRAR ========================================================= */ - #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ - #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ - #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ - #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= BCNT3AER ======================================================== */ - #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ - #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ -/* ======================================================== RYRAREN ======================================================== */ - #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ - #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR1 ========================================================== */ - #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ - #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ - #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ - #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ - #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ - #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ - #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR2 ========================================================== */ - #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ - #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ - #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ - #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ - #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ - #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ - #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ - #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ - #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ -/* ========================================================= RCR4 ========================================================== */ - #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ - #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ - #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ - #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRH ========================================================== */ - #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ - #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ -/* ========================================================= RFRL ========================================================== */ - #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ - #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ -/* ========================================================= RADJ ========================================================== */ - #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ - #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ - #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ - #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ -/* ========================================================= RADJ2 ========================================================= */ - #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ - #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SMR ========================================================== */ - #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ - #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ - #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ - #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ - #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ======================================================= SMR_SMCI ======================================================== */ - #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ - #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ - #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ - #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ - #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ - #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ - #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ - #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ -/* ========================================================== BRR ========================================================== */ - #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ - #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ -/* ========================================================== SCR ========================================================== */ - #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ======================================================= SCR_SMCI ======================================================== */ - #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ - #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ - #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ - #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ - #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ - #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ - #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ - #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ -/* ========================================================== TDR ========================================================== */ - #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ - #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ -/* ========================================================== SSR ========================================================== */ - #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_FIFO ======================================================== */ - #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ - #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ - #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_MANC ======================================================== */ - #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ - #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ -/* ======================================================= SSR_SMCI ======================================================== */ - #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ - #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ - #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ - #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ - #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ - #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ -/* ========================================================== RDR ========================================================== */ - #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ - #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ -/* ========================================================= SCMR ========================================================== */ - #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ - #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ - #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ - #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ - #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ - #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ -/* ========================================================= SEMR ========================================================== */ - #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ - #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ - #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ - #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ - #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ - #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ - #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ - #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ - #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ -/* ========================================================= SNFR ========================================================== */ - #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ - #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ -/* ========================================================= SIMR1 ========================================================= */ - #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ - #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ - #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ - #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR2 ========================================================= */ - #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ - #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ - #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ - #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ -/* ========================================================= SIMR3 ========================================================= */ - #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ - #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ - #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ - #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ - #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ - #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ - #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ - #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ - #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ -/* ========================================================= SISR ========================================================== */ - #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ - #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ -/* ========================================================= SPMR ========================================================== */ - #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ - #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ - #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ - #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ - #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ - #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ - #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ - #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ -/* ========================================================= TDRHL ========================================================= */ - #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ - #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FTDRHL ========================================================= */ - #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ -/* ========================================================= FTDRH ========================================================= */ - #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ - #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ - #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FTDRL ========================================================= */ - #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ - #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= RDRHL ========================================================= */ - #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ - #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ -/* ======================================================== FRDRHL ========================================================= */ - #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ - #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ - #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ - #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ - #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ - #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ -/* ======================================================= TDRHL_MAN ======================================================= */ - #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ - #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ - #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ - #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ -/* ======================================================= RDRHL_MAN ======================================================= */ - #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ - #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ - #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ - #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ - #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRH ========================================================= */ - #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ - #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ - #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ - #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ - #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ - #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ - #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ - #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ - #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ -/* ========================================================= FRDRL ========================================================= */ - #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ - #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ -/* ========================================================= MDDR ========================================================== */ - #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ - #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ -/* ========================================================= DCCR ========================================================== */ - #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ - #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ - #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ - #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ - #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ - #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ - #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ -/* ========================================================== FCR ========================================================== */ - #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ - #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ - #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ - #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ - #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ - #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ - #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ - #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ - #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ -/* ========================================================== FDR ========================================================== */ - #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ - #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ - #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ - #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ -/* ========================================================== LSR ========================================================== */ - #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ - #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ - #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ - #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ - #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ -/* ========================================================== CDR ========================================================== */ - #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ - #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ -/* ========================================================= SPTR ========================================================== */ - #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ - #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ - #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ - #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ - #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ - #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ - #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ - #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ -/* ========================================================= ACTR ========================================================== */ - #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ - #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ - #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ - #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ - #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ - #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ - #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ -/* ========================================================= ESMER ========================================================= */ - #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ - #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR0 ========================================================== */ - #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ - #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ - #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ - #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ -/* ========================================================== CR1 ========================================================== */ - #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ - #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ - #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ - #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ - #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ - #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ - #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ -/* ========================================================== CR2 ========================================================== */ - #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ - #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ - #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ - #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ - #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ - #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ -/* ========================================================== CR3 ========================================================== */ - #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ - #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ -/* ========================================================== PCR ========================================================== */ - #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ - #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ - #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ - #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ - #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ -/* ========================================================== ICR ========================================================== */ - #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ - #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ - #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ - #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ - #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ - #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ - #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ - #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ - #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ - #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ - #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ - #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ - #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ - #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ - #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ -/* ========================================================= STCR ========================================================== */ - #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ - #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ - #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ - #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ - #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ - #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ - #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ - #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0DR ========================================================= */ -/* ========================================================= CF0CR ========================================================= */ - #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ - #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ - #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ - #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ - #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ - #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ - #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ - #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ - #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF0RR ========================================================= */ -/* ======================================================== PCF1DR ========================================================= */ -/* ======================================================== SCF1DR ========================================================= */ -/* ========================================================= CF1CR ========================================================= */ - #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ - #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ - #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ - #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ - #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ - #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ - #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ - #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ - #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ - #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ -/* ========================================================= CF1RR ========================================================= */ -/* ========================================================== TCR ========================================================== */ - #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ - #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ -/* ========================================================== TMR ========================================================== */ - #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ - #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ - #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ - #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ - #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ - #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ -/* ========================================================= TPRE ========================================================== */ -/* ========================================================= TCNT ========================================================== */ -/* ======================================================= SCIMSKEN ======================================================== */ - #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ - #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== MMR ========================================================== */ - #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ - #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ - #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ - #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ - #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ - #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ - #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ - #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ - #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ -/* ========================================================= TMPR ========================================================== */ - #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ - #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ - #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= RMPR ========================================================== */ - #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ - #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ - #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ - #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ -/* ========================================================= MESR ========================================================== */ - #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ - #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ - #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ - #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ - #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ -/* ========================================================= MECR ========================================================== */ - #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ - #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ - #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ - #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ - #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SD_CMD ========================================================= */ - #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ - #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ - #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ - #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ - #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ - #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ - #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ - #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ - #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ -/* ======================================================== SD_ARG ========================================================= */ - #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ - #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_ARG1 ======================================================== */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ - #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== SD_STOP ======================================================== */ - #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ - #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ - #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_SECCNT ======================================================= */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ - #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SD_RSP10 ======================================================== */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ - #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP1 ======================================================== */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ - #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP32 ======================================================== */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ - #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP3 ======================================================== */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ - #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP54 ======================================================== */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ - #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SD_RSP5 ======================================================== */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ - #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= SD_RSP76 ======================================================== */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ - #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ -/* ======================================================== SD_RSP7 ======================================================== */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ - #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ -/* ======================================================= SD_INFO1 ======================================================== */ - #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ - #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ - #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ - #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ - #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ - #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ - #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ - #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ - #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ - #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_INFO2 ======================================================== */ - #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ - #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ - #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ - #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ - #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ - #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ - #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ - #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ - #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ - #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ - #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ - #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ - #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ - #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO1_MASK ===================================================== */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ - #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ - #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ - #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ - #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ -/* ===================================================== SD_INFO2_MASK ===================================================== */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ - #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ - #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ - #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ - #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ - #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ - #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ - #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ - #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ - #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ - #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_CLK_CTRL ====================================================== */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ - #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ - #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ - #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ -/* ======================================================== SD_SIZE ======================================================== */ - #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ - #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= SD_OPTION ======================================================= */ - #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ - #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ - #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ - #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ - #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ - #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ - #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ -/* ====================================================== SD_ERR_STS1 ====================================================== */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ - #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ - #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ - #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ - #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ - #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ - #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SD_ERR_STS2 ====================================================== */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ - #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ - #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ - #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ - #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ - #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SD_BUF0 ======================================================== */ - #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ - #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SDIO_MODE ======================================================= */ - #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ - #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ - #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ - #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ - #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SDIO_INFO1 ======================================================= */ - #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ -/* ==================================================== SDIO_INFO1_MASK ==================================================== */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ - #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ - #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ -/* ======================================================= SD_DMAEN ======================================================== */ - #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ - #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ -/* ======================================================= SOFT_RST ======================================================== */ - #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ - #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ -/* ======================================================= SDIF_MODE ======================================================= */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ - #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ -/* ======================================================= EXT_SWAP ======================================================== */ - #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ - #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ - #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SPCR ========================================================== */ - #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ - #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ - #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ - #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ - #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ - #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ - #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ - #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ - #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ -/* ========================================================= SSLP ========================================================== */ - #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ - #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ - #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ - #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ - #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ - #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ - #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ - #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ - #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ - #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPCR ========================================================= */ - #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ - #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ - #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ - #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ - #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSR ========================================================== */ - #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ - #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ - #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ - #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ - #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ - #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ - #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ - #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ - #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ -/* ========================================================= SPDR ========================================================== */ -/* ======================================================== SPDR_HA ======================================================== */ -/* ======================================================== SPDR_BY ======================================================== */ -/* ========================================================= SPSCR ========================================================= */ - #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ - #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ -/* ========================================================= SPBR ========================================================== */ - #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ - #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ -/* ========================================================= SPDCR ========================================================= */ - #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ - #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ - #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ - #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ - #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ - #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= SPCKD ========================================================= */ - #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ - #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SSLND ========================================================= */ - #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ - #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPND ========================================================== */ - #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ - #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR2 ========================================================= */ - #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ - #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ - #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ - #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ - #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ - #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ - #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCMD ========================================================= */ - #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ - #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ - #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ - #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ - #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ - #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ - #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ - #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ - #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ - #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ - #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ - #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ - #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ -/* ======================================================== SPDCR2 ========================================================= */ - #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ - #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ - #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ -/* ========================================================= SPSSR ========================================================= */ - #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ - #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ - #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ -/* ========================================================= SPCR3 ========================================================= */ - #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ - #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ - #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ - #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ -/* ========================================================= SPPR ========================================================== */ - #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ - #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ - #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ - #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ - #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ - #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PARIOAD ======================================================== */ - #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR ======================================================== */ - #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ - #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMWTSC ======================================================== */ -/* ======================================================== ECCMODE ======================================================== */ - #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ - #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== ECC2STS ======================================================== */ - #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ - #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECC1STSEN ======================================================= */ - #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ - #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ -/* ======================================================== ECC1STS ======================================================== */ - #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ - #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCPRCR ======================================================== */ - #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ - #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ -/* ======================================================= ECCPRCR2 ======================================================== */ - #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ - #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ - #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCETST ======================================================== */ - #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ - #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ -/* ======================================================== ECCOAD ========================================================= */ - #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMPRCR2 ======================================================= */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ - #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ - #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SSICR ========================================================= */ - #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ - #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ - #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ - #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ - #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ - #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ - #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ - #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ - #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ - #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ - #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ - #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ - #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ - #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ - #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ - #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ - #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ - #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ - #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ - #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ - #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ - #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ - #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ -/* ========================================================= SSISR ========================================================= */ - #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ - #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ - #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ - #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ - #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ - #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ - #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ - #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ - #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ - #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ - #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFCR ========================================================= */ - #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ - #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ - #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ - #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ - #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ - #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ - #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ - #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ - #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ - #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ - #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFSR ========================================================= */ - #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ - #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ - #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ - #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ - #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ - #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ -/* ======================================================== SSIFTDR ======================================================== */ - #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ - #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFTDR16 ======================================================= */ -/* ======================================================= SSIFTDR8 ======================================================== */ -/* ======================================================== SSIFRDR ======================================================== */ - #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ - #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SSIFRDR16 ======================================================= */ -/* ======================================================= SSIFRDR8 ======================================================== */ -/* ======================================================== SSIOFR ========================================================= */ - #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ - #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ - #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ - #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ - #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ -/* ======================================================== SSISCR ========================================================= */ - #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ - #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ - #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ - #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ - -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= SBYCR ========================================================= */ - #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ - #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ - #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ -/* ======================================================== MSTPCRA ======================================================== */ - #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ - #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ -/* ======================================================= SCKDIVCR ======================================================== */ - #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ - #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ - #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ - #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ - #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ - #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ - #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ - #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ -/* ======================================================= SCKDIVCR2 ======================================================= */ - #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ - #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ -/* ======================================================== SCKSCR ========================================================= */ - #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ - #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== PLLCCR ========================================================= */ - #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ - #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ - #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ - #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ -/* ========================================================= PLLCR ========================================================= */ - #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ - #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== PLLCCR2 ======================================================== */ - #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ - #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ - #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ -/* ========================================================= BCKCR ========================================================= */ - #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ - #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ -/* ======================================================== MEMWAIT ======================================================== */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ - #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ -/* ======================================================== MOSCCR ========================================================= */ - #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ - #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR ========================================================= */ - #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ - #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== HOCOCR2 ======================================================== */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ - #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ - #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ -/* ======================================================== MOCOCR ========================================================= */ - #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ - #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR1 ========================================================= */ - #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ - #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLLCR2 ========================================================= */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ - #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ -/* ========================================================= OSCSF ========================================================= */ - #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ - #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ - #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ - #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ - #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ -/* ========================================================= CKOCR ========================================================= */ - #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ - #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ - #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ - #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== TRCKCR ========================================================= */ - #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ - #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ - #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ -/* ======================================================== OSTDCR ========================================================= */ - #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ - #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ - #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ -/* ======================================================== OSTDSR ========================================================= */ - #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ - #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ -/* ========================================================= LPOPT ========================================================= */ - #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ - #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ - #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ - #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ - #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ -/* ======================================================= SLCDSCKCR ======================================================= */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ - #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ -/* ======================================================== EBCKOCR ======================================================== */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ - #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SDCKOCR ======================================================== */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ - #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ -/* ======================================================= MOCOUTCR ======================================================== */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ - #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================= HOCOUTCR ======================================================== */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ - #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ -/* ========================================================= SNZCR ========================================================= */ - #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ - #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ - #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ - #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== SNZEDCR ======================================================== */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ - #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ - #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ - #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ - #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ - #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ - #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ - #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR ======================================================== */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ - #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== FLSTOP ========================================================= */ - #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ - #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ - #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ -/* ========================================================= PSMCR ========================================================= */ - #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ - #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ -/* ========================================================= OPCCR ========================================================= */ - #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ - #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ - #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ -/* ======================================================== SOPCCR ========================================================= */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ - #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ - #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ -/* ======================================================= MOSCWTCR ======================================================== */ - #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ - #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ -/* ======================================================= HOCOWTCR ======================================================== */ - #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ - #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ -/* ======================================================== RSTSR1 ========================================================= */ - #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ - #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ - #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ - #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ - #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ - #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ - #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ - #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ - #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ - #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ - #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ -/* ======================================================== STCONR ========================================================= */ - #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ - #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD1CR1 ======================================================== */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LVD2CR1 ======================================================== */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ - #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ - #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ====================================================== USBCKCR_ALT ====================================================== */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= SDADCCKCR ======================================================= */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ - #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1SR ========================================================= */ - #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2SR ========================================================= */ - #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ - #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ - #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ -/* ========================================================= PRCR ========================================================== */ - #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ - #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ - #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ - #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ - #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ - #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ - #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER0 ======================================================== */ - #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER1 ======================================================== */ - #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ - #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER2 ======================================================== */ - #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ - #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ - #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ - #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ - #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ - #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIER3 ======================================================== */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ - #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ - #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ - #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ - #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR0 ======================================================== */ - #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR1 ======================================================== */ - #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ - #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR2 ======================================================== */ - #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ - #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ - #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ - #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ - #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ - #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSIFR3 ======================================================== */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ - #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ - #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ - #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ - #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR0 ======================================================== */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR1 ======================================================== */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ -/* ======================================================= DPSIEGR2 ======================================================== */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ - #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ - #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ - #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSBYCR ======================================================== */ - #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ - #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ - #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ - #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ -/* ======================================================== SYOCDCR ======================================================== */ - #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ - #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ - #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ -/* ========================================================= MOMCR ========================================================= */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ - #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ - #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ - #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ - #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR0 ========================================================= */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ - #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ - #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ - #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ - #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ - #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSR2 ========================================================= */ - #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ - #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ -/* ======================================================== LVCMPCR ======================================================== */ - #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ - #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ - #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ -/* ======================================================= LVD1CMPCR ======================================================= */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDLVLR ======================================================== */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ - #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ - #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ -/* ======================================================= LVD2CMPCR ======================================================= */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ - #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ - #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD1CR0 ======================================================== */ - #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== LVD2CR0 ======================================================== */ - #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ - #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ - #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ - #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ - #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ - #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ - #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTCR1 ========================================================= */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ - #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== DCDCCTL ======================================================== */ - #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ - #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ - #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ - #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ - #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ - #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ - #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ -/* ======================================================== VCCSEL ========================================================= */ - #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ - #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== LDOSCR ========================================================= */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ - #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ - #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ -/* ======================================================= PL2LDOSCR ======================================================= */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ - #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ -/* ======================================================== SOSCCR ========================================================= */ - #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ - #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ -/* ========================================================= SOMCR ========================================================= */ - #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ - #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ -/* ========================================================= SOMRG ========================================================= */ - #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ - #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ -/* ======================================================== LOCOCR ========================================================= */ - #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ - #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ -/* ======================================================= LOCOUTCR ======================================================== */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ - #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ -/* ======================================================== VBTCR2 ========================================================= */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ - #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ - #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VBTSR ========================================================= */ - #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ - #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ - #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ - #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTCMPCR ======================================================== */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ - #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTLVDICR ======================================================= */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ - #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTWCTLR ======================================================== */ - #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ - #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH0OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH1OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ -/* ====================================================== VBTWCH2OTSR ====================================================== */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ - #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTICTLR ======================================================== */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ - #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ - #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ - #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ -/* ======================================================= VBTOCTLR ======================================================== */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ - #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ - #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ - #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ - #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ - #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ - #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWTER ======================================================== */ - #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ - #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ - #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ - #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ - #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ - #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ - #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWEGR ======================================================== */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ - #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ - #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ - #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTWFR ========================================================= */ - #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ - #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ - #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ - #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ - #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ - #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ - #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBKR ========================================================= */ - #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ - #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ -/* ======================================================== FWEPROR ======================================================== */ - #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ - #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ -/* ======================================================== PLL2CCR ======================================================== */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ - #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ - #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ - #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ -/* ======================================================== PLL2CR ========================================================= */ - #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ - #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ -/* ====================================================== USBCKDIVCR ======================================================= */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ - #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== OCTACKDIVCR ====================================================== */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ - #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== SCISPICKDIVCR ===================================================== */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ - #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== CANFDCKDIVCR ====================================================== */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ - #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== GPTCKDIVCR ======================================================= */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ - #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ -/* ===================================================== USB60CKDIVCR ====================================================== */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ - #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== CECCKDIVCR ======================================================= */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ - #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== I3CCKDIVCR ======================================================= */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ - #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ -/* ====================================================== IICCKDIVCR ======================================================= */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ - #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ - #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ - #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= OCTACKCR ======================================================== */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ - #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ - #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ - #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ -/* ====================================================== SCISPICKCR ======================================================= */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ - #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= CANFDCKCR ======================================================= */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ - #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== GPTCKCR ======================================================== */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ - #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ - #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ - #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= USB60CKCR ======================================================= */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ - #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ - #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ - #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCKCR ======================================================== */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ - #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ - #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ - #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== IICCKCR ======================================================== */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ - #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ - #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ - #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== I3CCKCR ======================================================== */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ - #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ - #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ - #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZREQCR1 ======================================================= */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ - #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================= SNZEDCR1 ======================================================== */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ - #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ -/* ======================================================== CGFSAR ========================================================= */ - #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ - #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ -/* ======================================================== LPMSAR ========================================================= */ - #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ - #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ - #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ - #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ -/* ======================================================== LVDSAR ========================================================= */ - #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ -/* ======================================================== RSTSAR ========================================================= */ - #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ -/* ======================================================== BBFSAR ========================================================= */ - #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ - #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ - #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ - #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ - #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ - #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ - #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ - #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ - #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ - #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ - #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ - #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPFSAR ========================================================= */ - #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ - #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ - #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ - #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ - #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ - #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ - #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ - #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ - #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ - #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ - #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ - #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ - #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ - #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ - #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ - #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ - #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ - #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ - #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ - #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ - #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ - #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ - #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ - #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ - #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ -/* ======================================================== DPSWCR ========================================================= */ - #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ - #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ -/* ====================================================== VBATTMNSELR ====================================================== */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ - #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= VBATTMONR ======================================================= */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ - #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ -/* ======================================================== VBTBER ========================================================= */ - #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ - #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCDR ========================================================= */ - #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ - #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TSCR ========================================================== */ - #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ - #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ - #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ - #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ - #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ - #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ========================================================= CFIFO ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== DVCHGR ========================================================= */ - #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ - #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ - #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ - #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ====================================================== USBBCCTRL0 ======================================================= */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ - #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ - #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ - #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ - #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ - #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ - #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ - #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ - #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ - #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ -/* ======================================================== UCKSEL ========================================================= */ - #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ - #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ -/* ========================================================= USBMC ========================================================= */ - #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ - #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ - #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSLEW ======================================================== */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ - #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ - #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ - #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ - #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR0R_FS ======================================================= */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ - #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ - #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ - #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ - #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ - #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ - #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ - #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ - #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ -/* ====================================================== DPUSR1R_FS ======================================================= */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ - #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ - #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ - #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ - #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ - #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ - #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ - #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= WDTRR ========================================================= */ - #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ - #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ -/* ========================================================= WDTCR ========================================================= */ - #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ - #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ - #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ - #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ - #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ - #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ - #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ -/* ========================================================= WDTSR ========================================================= */ - #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ - #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ - #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ - #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ - #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ -/* ======================================================== WDTRCR ========================================================= */ - #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ - #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ -/* ======================================================= WDTCSTPR ======================================================== */ - #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ - #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_TZF ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFOAD ========================================================= */ - #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ========================================================= TZFPT ========================================================= */ - #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ R_CACHE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CCACTL ========================================================= */ - #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ - #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCAFCT ========================================================= */ - #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ - #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ -/* ======================================================== CCALCF ========================================================= */ - #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ - #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ -/* ======================================================== SCACTL ========================================================= */ - #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ - #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCAFCT ========================================================= */ - #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ - #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ -/* ======================================================== SCALCF ========================================================= */ - #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ - #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ -/* ======================================================== CAPOAD ========================================================= */ - #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ -/* ======================================================== CAPRCR ========================================================= */ - #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ - #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ - #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ - #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ - -/* =========================================================================================================================== */ -/* ================ R_CPSCU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CSAR ========================================================== */ - #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ - #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ - #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ - #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ - #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ -/* ======================================================== SRAMSAR ======================================================== */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ - #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ - #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ - #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ -/* ======================================================= STBRAMSAR ======================================================= */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ - #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ -/* ======================================================== DTCSAR ========================================================= */ - #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ - #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACSAR ======================================================== */ - #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ - #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARA ======================================================== */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ - #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ -/* ======================================================== ICUSARB ======================================================== */ - #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ - #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARC ======================================================== */ - #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ - #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ -/* ======================================================== ICUSARD ======================================================== */ - #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ - #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARE ======================================================== */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ - #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ - #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ - #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ - #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ - #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ - #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ - #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ - #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ - #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ - #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ - #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ - #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARF ======================================================== */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ - #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ - #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ - #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ - #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ - #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ - #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ - #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ - #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ - #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ - #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ - #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ - #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== ICUSARG ======================================================== */ - #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARH ======================================================== */ - #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARI ======================================================== */ - #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ - #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== ICUSARM ======================================================== */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ - #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ - #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ - #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ - #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ - #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ - #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ - #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARA ======================================================== */ - #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ - #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARB ======================================================== */ - #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ - #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSSARC ======================================================== */ - #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ - #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSPARC ======================================================== */ - #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ - #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MMPUSARA ======================================================== */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ - #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ -/* ======================================================= MMPUSARB ======================================================== */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ - #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== TZFSAR ========================================================= */ - #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ - #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGSAR ======================================================== */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ - #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ -/* ======================================================= DMACCHSAR ======================================================= */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ - #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ -/* ======================================================== CPUDSAR ======================================================== */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ - #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ -/* ====================================================== SRAMSABAR0 ======================================================= */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ====================================================== SRAMSABAR1 ======================================================= */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ - #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ -/* ======================================================== TEVTRCR ======================================================== */ - #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ - #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CEC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CADR ========================================================== */ - #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ - #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ - #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ - #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ - #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ - #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ - #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ - #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ - #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ - #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ - #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ - #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ - #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ - #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ - #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ - #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ - #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL1 ======================================================== */ - #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ - #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ - #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ - #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ - #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ - #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ - #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ - #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ -/* ========================================================= STATB ========================================================= */ - #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ - #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= STATL ========================================================= */ - #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ - #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC0L ========================================================= */ - #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ - #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= LGC1L ========================================================= */ - #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ - #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATB ========================================================== */ - #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ - #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMT ========================================================== */ - #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ - #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLL ========================================================= */ - #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ - #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATLH ========================================================= */ - #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ - #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBL ========================================================= */ - #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ - #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== STATBH ========================================================= */ - #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ - #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LL ========================================================= */ - #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ - #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC0LH ========================================================= */ - #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ - #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LL ========================================================= */ - #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ - #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ -/* ======================================================== LGC1LH ========================================================= */ - #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ - #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBL ========================================================= */ - #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ - #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ -/* ========================================================= DATBH ========================================================= */ - #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ - #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ -/* ========================================================= NOMP ========================================================== */ - #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ - #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CECEXMD ======================================================== */ - #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ - #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ - #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ - #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ -/* ======================================================= CECEXMON ======================================================== */ - #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ - #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ - #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ - #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ -/* ========================================================= CTXD ========================================================== */ -/* ========================================================= CRXD ========================================================== */ -/* ========================================================= CECES ========================================================= */ - #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ - #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ - #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ - #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ - #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ - #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ - #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ - #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ -/* ========================================================= CECS ========================================================== */ - #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ - #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ - #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ - #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ - #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ - #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ - #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ - #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ -/* ========================================================= CECFC ========================================================= */ - #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ - #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ - #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ - #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ - #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ - #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ - #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ - #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ -/* ======================================================== CECCTL0 ======================================================== */ - #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ - #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ - #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ - #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ - #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ - #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ - #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ - #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ - #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_OSPI ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DCR ========================================================== */ - #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ - #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ - #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ -/* ========================================================== DAR ========================================================== */ - #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ - #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ - #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ - #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ - #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= DCSR ========================================================== */ - #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ - #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ - #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ - #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ - #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ - #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ - #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ - #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ - #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ - #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ - #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ - #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ -/* ========================================================== DSR ========================================================== */ - #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ - #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ - #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ - #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ -/* ========================================================= MDTR ========================================================== */ - #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ - #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ - #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ - #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ - #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ - #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ - #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ -/* ========================================================= ACTR ========================================================== */ - #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ - #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ACAR ========================================================== */ - #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ - #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== DRCSTR ========================================================= */ - #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ - #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ - #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ - #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ - #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ - #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ - #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ - #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ - #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ - #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ - #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ -/* ======================================================== DWCSTR ========================================================= */ - #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ - #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ - #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ - #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ - #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ - #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ - #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ - #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ - #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ - #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ - #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ - #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ - #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ -/* ========================================================= DCSTR ========================================================= */ - #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ - #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ - #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ - #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ - #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ -/* ========================================================= CDSR ========================================================== */ - #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ - #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ - #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ - #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ - #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ - #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ - #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ - #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ - #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ - #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ -/* ========================================================= MDLR ========================================================== */ - #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ - #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ - #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ - #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ - #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ - #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ -/* ========================================================= MRWCR ========================================================= */ - #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ - #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ - #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ - #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ - #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ -/* ======================================================== MRWCSR ========================================================= */ - #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ - #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ - #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ - #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ - #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ - #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ - #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ - #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ - #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ - #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ - #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ - #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ - #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ - #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ - #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ - #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ - #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ -/* ========================================================== ESR ========================================================== */ - #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ - #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ - #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ - #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ -/* ========================================================= CWNDR ========================================================= */ - #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ - #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CWDR ========================================================== */ - #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ - #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ - #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ - #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ - #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ -/* ========================================================== CRR ========================================================== */ - #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ - #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ - #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ - #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ - #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ - #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ -/* ========================================================= ACSR ========================================================== */ - #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ - #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ - #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ - #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ -/* ======================================================== DCSMXR ========================================================= */ - #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ - #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ - #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ - #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== DWSCTSR ======================================================== */ - #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ - #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ - #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ - #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SYSCFG ========================================================= */ - #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ - #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ - #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ - #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ - #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ - #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ - #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ -/* ======================================================== BUSWAIT ======================================================== */ - #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ - #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ -/* ======================================================== SYSSTS0 ======================================================== */ - #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ - #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ - #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ - #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ - #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ - #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ -/* ======================================================== PLLSTA ========================================================= */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ - #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ -/* ======================================================= DVSTCTR0 ======================================================== */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ - #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ - #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ - #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ - #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ - #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ - #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ - #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ - #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ - #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ -/* ======================================================= TESTMODE ======================================================== */ - #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ - #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ -/* ========================================================= CFIFO ========================================================= */ - #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFIFOL ========================================================= */ -/* ======================================================== CFIFOH ========================================================= */ -/* ======================================================== CFIFOLL ======================================================== */ -/* ======================================================== CFIFOHH ======================================================== */ -/* ======================================================== D0FIFO ========================================================= */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D0FIFOL ======================================================== */ -/* ======================================================== D0FIFOH ======================================================== */ -/* ======================================================= D0FIFOLL ======================================================== */ -/* ======================================================= D0FIFOHH ======================================================== */ -/* ======================================================== D1FIFO ========================================================= */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ - #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== D1FIFOL ======================================================== */ -/* ======================================================== D1FIFOH ======================================================== */ -/* ======================================================= D1FIFOLL ======================================================== */ -/* ======================================================= D1FIFOHH ======================================================== */ -/* ======================================================= CFIFOSEL ======================================================== */ - #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ - #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFIFOCTR ======================================================== */ - #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D0FIFOSEL ======================================================= */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D0FIFOCTR ======================================================= */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================= D1FIFOSEL ======================================================= */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ - #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ - #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ - #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ - #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ - #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ - #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ - #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ -/* ======================================================= D1FIFOCTR ======================================================= */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ - #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ - #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ - #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ - #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ -/* ======================================================== INTENB0 ======================================================== */ - #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ - #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ - #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ - #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ - #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ - #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ - #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ - #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ - #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTENB1 ======================================================== */ - #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ - #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ - #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ - #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ - #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ - #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ - #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ - #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ - #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ - #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ - #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYENB ======================================================== */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ - #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYENB ======================================================== */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ - #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPENB ======================================================== */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ - #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ -/* ======================================================== SOFCFG ========================================================= */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ - #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ - #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ - #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ - #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ -/* ======================================================== PHYSET ========================================================= */ - #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ - #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ - #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ - #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ - #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ - #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ - #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ - #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTS0 ======================================================== */ - #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ - #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ - #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ - #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ - #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ - #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ - #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ - #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ - #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ - #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ - #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ - #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ -/* ======================================================== INTSTS1 ======================================================== */ - #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ - #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ - #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ - #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ - #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ - #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ - #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ - #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ - #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ - #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ - #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ -/* ======================================================== BRDYSTS ======================================================== */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ - #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== NRDYSTS ======================================================== */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ - #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ -/* ======================================================== BEMPSTS ======================================================== */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ - #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FRMNUM ========================================================= */ - #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ - #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ - #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ - #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ -/* ======================================================== UFRMNUM ======================================================== */ - #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ - #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ - #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ -/* ======================================================== USBADDR ======================================================== */ - #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ - #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ -/* ======================================================== USBREQ ========================================================= */ - #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ - #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ - #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ -/* ======================================================== USBVAL ========================================================= */ - #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ - #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBINDX ======================================================== */ - #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ - #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ -/* ======================================================== USBLENG ======================================================== */ - #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ - #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ -/* ======================================================== DCPCFG ========================================================= */ - #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ -/* ======================================================== DCPMAXP ======================================================== */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ -/* ======================================================== DCPCTR ========================================================= */ - #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ - #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ - #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ - #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ - #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== PIPESEL ======================================================== */ -/* ======================================================== PIPECFG ======================================================== */ - #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ - #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ - #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ - #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ - #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ - #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ - #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ - #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ -/* ======================================================== PIPEBUF ======================================================== */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ - #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ - #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ -/* ======================================================= PIPEMAXP ======================================================== */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ - #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ - #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ -/* ======================================================= PIPEPERI ======================================================== */ - #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ - #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ - #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ -/* ======================================================= PIPE_CTR ======================================================== */ - #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ - #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ - #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ - #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ - #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ - #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ - #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ - #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ - #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ - #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ - #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ - #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ -/* ======================================================== DEVADD ========================================================= */ - #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ - #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ - #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ - #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ -/* ======================================================== LPCTRL ========================================================= */ - #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ - #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ -/* ========================================================= LPSTS ========================================================= */ - #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ - #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ -/* ======================================================== BCCTRL ========================================================= */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ - #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ - #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ - #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ - #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ - #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ - #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ - #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ - #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL1 ======================================================== */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ - #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ - #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ - #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ - #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ - #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ - #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= PL1CTRL2 ======================================================== */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ - #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ - #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ -/* ======================================================= HL1CTRL1 ======================================================== */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ - #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ - #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ -/* ======================================================= HL1CTRL2 ======================================================== */ - #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ - #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ - #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ - #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ - #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ -/* ======================================================= PHYTRIM1 ======================================================== */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ - #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ - #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ - #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ - #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ - #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ -/* ======================================================= PHYTRIM2 ======================================================== */ - #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ - #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ - #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ - #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ - #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ - #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ -/* ======================================================== DPUSR0R ======================================================== */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ - #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ - #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ - #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR1R ======================================================== */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ - #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ - #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ - #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ - #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ - #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ - #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSR2R ======================================================== */ - #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ - #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ - #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ - #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ - #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ - #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ - #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ -/* ======================================================== DPUSRCR ======================================================== */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ - #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ - #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_AGTX0 ================ */ -/* =========================================================================================================================== */ - -/* =========================================================================================================================== */ -/* ================ R_ECCMB0 ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= EC710CTL ======================================================== */ - #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ - #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ - #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ - #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ - #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ - #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ - #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ - #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ - #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ - #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ - #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ - #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ - #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ - #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ -/* ======================================================= EC710TMC ======================================================== */ - #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ - #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ - #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ - #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ - #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ -/* ======================================================= EC710TED ======================================================== */ - #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ - #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= EC710EAD0 ======================================================= */ - #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ - #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ - -/* =========================================================================================================================== */ -/* ================ R_FLAD ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FCKMHZ ========================================================= */ - #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ - #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ - -/** @} */ /* End of group PosMask_peripherals */ - - #ifdef __cplusplus -} - #endif - -#endif /* R7FA6M5BH_H */ - -/** @} */ /* End of group R7FA6M5BH */ - -/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_cfg.h deleted file mode 100644 index 825f8cd32..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BOARD_CFG_H_ -#define BOARD_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - void bsp_init(void * p_args); - - #ifdef __cplusplus - } - #endif -#endif /* BOARD_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_sdram.h deleted file mode 100644 index 2d5eb7405..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/board_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BOARD_SDRAM_H -#define BOARD_SDRAM_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0. - * It is only present if the new support has not been enabled. */ -#if 1 != BSP_CFG_SDRAM_ENABLED - #define bsp_sdram_init() R_BSP_SdramInit(true) -#endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_api.h deleted file mode 100644 index d912bc0ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_api.h +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_API_H -#define BSP_API_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* FSP Common Includes. */ -#include "fsp_common_api.h" - -/* Gets MCU configuration information. */ -#include "bsp_cfg.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic push - -/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. - * We are not modifying these files so we will ignore these warnings temporarily. */ - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" -#endif - -/* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_exceptions.h" -#include "vector_data.h" - -/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ -#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" -#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) - -/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ - #pragma GCC diagnostic pop -#endif - -#if defined(BSP_API_OVERRIDE) - #include BSP_API_OVERRIDE -#else - -/* BSP Common Includes. */ - #include "../../src/bsp/mcu/all/bsp_common.h" - -/* BSP MCU Specific Includes. */ - #include "../../src/bsp/mcu/all/bsp_register_protection.h" - #include "../../src/bsp/mcu/all/bsp_irq.h" - #include "../../src/bsp/mcu/all/bsp_io.h" - #include "../../src/bsp/mcu/all/bsp_group_irq.h" - #include "../../src/bsp/mcu/all/bsp_clocks.h" - #include "../../src/bsp/mcu/all/bsp_module_stop.h" - #include "../../src/bsp/mcu/all/bsp_security.h" - -/* Factory MCU information. */ - #include "../../inc/fsp_features.h" - -/* BSP Common Includes (Other than bsp_common.h) */ - #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" - - #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") - #include "../../src/bsp/mcu/all/internal/bsp_internal.h" - #endif - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_cfg.h deleted file mode 100644 index 8074418ad..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_cfg.h +++ /dev/null @@ -1,61 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - - #include "bsp_clock_cfg.h" - #include "bsp_mcu_family_cfg.h" - #include "board_cfg.h" - #define RA_NOT_DEFINED 0 - #ifndef BSP_CFG_RTOS - #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else - #define BSP_CFG_RTOS (0) - #endif - #endif - #ifndef BSP_CFG_RTC_USED - #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) - #endif - #undef RA_NOT_DEFINED - #if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif - #define BSP_CFG_MCU_VCC_MV (3300) - #define BSP_CFG_STACK_MAIN_BYTES (0x400) - #define BSP_CFG_HEAP_BYTES (0) - #define BSP_CFG_PARAM_CHECKING_ENABLE (0) - #define BSP_CFG_ASSERT (0) - - #define BSP_CFG_PFS_PROTECT ((1)) - - #define BSP_CFG_C_RUNTIME_INIT ((1)) - #define BSP_CFG_EARLY_INIT ((0)) - - #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED - #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - #endif - - #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE - #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE - #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) - #endif - #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS - #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - #endif - - #ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_clocks.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_clocks.h deleted file mode 100644 index b496e8ff5..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_clocks.h +++ /dev/null @@ -1,1727 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_CLOCKS_H -#define BSP_CLOCKS_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_clock_cfg.h" -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match SCKCR.CKSEL values. */ -#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. -#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. - #endif - #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. - #endif - #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. - #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. - #endif -#else - -/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ -/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ - #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. - #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. - #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. - -/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ - #define BSP_PRV_OSTC_OFFSET (0x7FU) - -#endif - -/* PLLs are not supported in the following scenarios: - * - When using low voltage mode - * - When using an MCU that does not have a PLL - * - When the PLL only accepts the main oscillator as a source and XTAL is not used - */ -#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ - !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) - #define BSP_PRV_PLL_SUPPORTED (1) - #if BSP_FEATURE_CGC_HAS_PLL2 - #define BSP_PRV_PLL2_SUPPORTED (1) - #else - #define BSP_PRV_PLL2_SUPPORTED (0) - #endif -#else - #define BSP_PRV_PLL_SUPPORTED (0) - #define BSP_PRV_PLL2_SUPPORTED (0) -#endif - -/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency - * calculated here is also used to initialize the g_clock_freq array. */ -#if BSP_PRV_PLL_SUPPORTED - #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ - (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif -#if BSP_PRV_PLL2_SUPPORTED - #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #else - #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #endif -#endif - -#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) - -/* Frequencies of clocks with fixed freqencies. */ -#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz -#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz - -#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) -#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE - #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) - #endif - #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ - (BSP_CFG_PLL_DIV + 1U)) - #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) - #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ - (BSP_CFG_PLL_DIV)) - #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) - #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) - #endif -#endif - -/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ -#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) -#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) - -#if !BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) -#else - #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) -#endif - -#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) -#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) -#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) -#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) -#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) -#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) -#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) -#define BSP_PRV_EXTRACLK3_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_EXTRACLK3_DIV) - -/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have - * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ -#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) -#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) -#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) -#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) -#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) -#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) -#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) -#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) -#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) -#define BSP_STARTUP_EXTRACLK3_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_EXTRACLK3_DIV_VALUE) - -/* System clock divider options. */ -#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. -#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. -#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. -#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. -#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. -#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. -#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. -#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). -#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. -#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. -#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. -#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. - -/* USB clock divider options. */ -#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 -#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 -#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 -#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 -#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 -#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 -#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 -#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 -#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 -#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 - -/* USB60 clock divider options. */ -#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 -#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 -#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 -#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 -#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 -#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 -#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 -#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 -#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 -#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 - -/* GLCD clock divider options. */ -#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 -#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 -#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 -#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 -#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 -#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 -#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 -#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 -#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 -#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 - -/* OCTA clock divider options. */ -#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 -#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 - -/* CANFD clock divider options. */ -#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 -#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 - -/* SCI clock divider options. */ -#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 -#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 -#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 -#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 -#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 -#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 -#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 -#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 -#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 -#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 - -/* SPI clock divider options. */ -#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 -#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 -#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 -#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 -#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 -#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 -#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 -#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 -#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 -#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 - -/* SCISPI clock divider options. */ -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 -#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 - -/* GPT clock divider options. */ -#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 -#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 -#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 -#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 -#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 -#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 -#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 -#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 -#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 -#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 - -/* IIC clock divider options. */ -#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 -#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 -#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 -#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 -#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 - -/* CEC clock divider options. */ -#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 -#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 - -/* I3C clock divider options. */ -#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 -#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 -#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 -#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 -#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 -#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 -#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 -#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 -#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 -#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 - -/* ADC clock divider options. */ -#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 -#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 -#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 -#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 -#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 -#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 -#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 -#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 -#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 -#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 - -/* SAU clock divider options. */ -#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 -#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 -#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 -#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 -#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 -#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 -#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 -#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 -#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 -#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 -#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 - -/* Extra peripheral 0 clock divider options. */ -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 -#define BSP_CLOCKS_EXTRA_PERIPHERAL0_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 - -/* PLL divider options. */ -#define BSP_CLOCKS_PLL_DIV_1 (0) -#define BSP_CLOCKS_PLL_DIV_2 (1) -#define BSP_CLOCKS_PLL_DIV_3 (2) -#define BSP_CLOCKS_PLL_DIV_4 (3) -#define BSP_CLOCKS_PLL_DIV_5 (4) -#define BSP_CLOCKS_PLL_DIV_6 (5) -#define BSP_CLOCKS_PLL_DIV_8 (7) -#define BSP_CLOCKS_PLL_DIV_9 (8) -#define BSP_CLOCKS_PLL_DIV_1_5 (9) -#define BSP_CLOCKS_PLL_DIV_16 (15) - -/* PLL multiplier options. */ -#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) - -/* Offset from decimal multiplier to register value for PLLCCR type 4. */ - #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) - -#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) - -#else - - #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) - #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) - -/** - * X=Integer portion of the multiplier. - * Y=Fractional portion of the multiplier. - */ - #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U))) - -#endif - -/* Configuration option used to disable clock output. */ -#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) - -/* HOCO cycles per microsecond. */ -#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) - -/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ -#if BSP_HOCO_HZ < 48000000U - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) -#else - #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) -#endif - -/* Create a mask of valid bits in SCKDIVCR. */ -#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#if BSP_FEATURE_CGC_HAS_PCLKD - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) -#else - #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKC - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) -#else - #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKB - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) -#else - #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKA - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) -#else - #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB - #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) -#else - #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_PCLKE - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) -#else - #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) -#endif -#if BSP_FEATURE_CGC_HAS_FCLK - #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) -#else - #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) -#endif -#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ - BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ - BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ - BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) - -/* FLL is only used when enabled, present and the subclock is populated. */ -#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED - #define BSP_PRV_HOCO_USE_FLL (1) - #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US - #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) - #endif -#else - #define BSP_PRV_HOCO_USE_FLL (0) - #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) -#endif - -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR - #define BSP_PRV_RTC_RESET_DELAY_US (200) -#endif - -/* Operating power control modes. */ -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed -#else - #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed - #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed - #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage - #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed -#endif -#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -typedef struct -{ - uint32_t pll_freq; -} bsp_clock_up2025-07-29_callback_args_t; - - #if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_up2025-07-29_callback_t)(bsp_clock_up2025-07-29_callback_args_t * - p_callback_args); - #elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_up2025-07-29_callback_t)(bsp_clock_up2025-07-29_callback_args_t * - p_callback_args); - #endif - -#endif - -/** PLL multiplier values */ -typedef enum e_cgc_pll_mul -{ - CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 - CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 - CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 - CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 - CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 - CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 - CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 - CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 - CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 - CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 - CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 - CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 - CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 - CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 - CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 - CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 - CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 - CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 - CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 - CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 - CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 - CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 - CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 - CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 - CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 - CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 - CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 - CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 - CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 - CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 - CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 - CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 - CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 - CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 - CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 - CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 - CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 - CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 - CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 - CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 - CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 - CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 - CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 - CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 - CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 - CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 - CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 - CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 - CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 - CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 - CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 - CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 - CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 - CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 - CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 - CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 - CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 - CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 - CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 - CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 - CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 - CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 - CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 - CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 - CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 - CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 - CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 - CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 - CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 - CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 - CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 - CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 - CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 - CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 - CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 - CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 - CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 - CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 - CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 - CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 - CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 - CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 - CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 - CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 - CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 - CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 - CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 - CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 - CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 - CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 - CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 - CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 - CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 - CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 - CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 - CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 - CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 - CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 - CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 - CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 - CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 - CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 - CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 - CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 - CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 - CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 - CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 - CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 - CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 - CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 - CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 - CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 - CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 - CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 - CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 - CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 - CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 - CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 - CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 - CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 - CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 - CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 - CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 - CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 - CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 - CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 - CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 - CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 - CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 - CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 - CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 - CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 - CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 - CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 - CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 - CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 - CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 - CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 - CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 - CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 - CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 - CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 - CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 - CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 - CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 - CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 - CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 - CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 - CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 - CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 - CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 - CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 - CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 - CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 - CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 - CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 - CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 - CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 - CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 - CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 - CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 - CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 - CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 - CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 - CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 - CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 - CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 - CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 - CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 - CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 - CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 - CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 - CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 - CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 - CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 - CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 - CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 - CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 - CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 - CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 - CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 - CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 - CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 - CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 - CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 - CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 - CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 - CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 - CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 - CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 - CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 - CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 - CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 - CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 - CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 - CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 - CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 - CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 - CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 - CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 - CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 - CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 - CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 - CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 - CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 - CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 - CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 - CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 - CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 - CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 - CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 - CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 - CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 - CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 - CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 - CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 - CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 - CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 - CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 - CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 - CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 - CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 - CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 - CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 - CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 - CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 - CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 - CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 - CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 - CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 - CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 - CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 - CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 - CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 - CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 - CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 - CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 - CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 - CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 - CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 - CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 - CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 - CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 - CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 - CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 - CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 - CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 - CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 - CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 - CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 - CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 - CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 - CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 - CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 - CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 - CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 - CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 - CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 - CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 - CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 - CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 - CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 - CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 - CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 - CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 - CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 - CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 - CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 - CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 - CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 - CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 - CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 - CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 - CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 - CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 - CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 - CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 - CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 - CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 - CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 - CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 - CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 - CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 - CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 - CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 - CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 - CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 - CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 - CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 - CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 - CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 - CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 - CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 - CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 - CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 - CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 - CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 - CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 - CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 - CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 - CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 - CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 - CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 - CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 - CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 - CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 - CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 - CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 - CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 - CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 - CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 - CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 - CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 - CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 - CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 - CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 - CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 - CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 - CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 - CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 - CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 - CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 - CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 - CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 - CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 - CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 - CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 - CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 - CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 - CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 - CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 - CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 - CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 - CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 - CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 - CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 - CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 - CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 - CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 - CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 - CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 - CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 - CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 - CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 - CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 - CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 - CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 - CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 - CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 - CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 - CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 - CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 - CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 - CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 - CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 - CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 - CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 - CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 - CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 - CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 - CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 - CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 - CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 - CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 - CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 - CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 - CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 - CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 - CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 - CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 - CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 - CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 - CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 - CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 - CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 - CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 - CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 - CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 - CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 - CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 - CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 - CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 - CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 - CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 - CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 - CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 - CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 - CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 - CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 - CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 - CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 - CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 - CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 - CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 - CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 - CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 - CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 - CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 - CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 - CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 - CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 - CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 - CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 - CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 - CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 - CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 - CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 - CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 - CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 - CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 - CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 - CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 - CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 - CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 - CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 - CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 - CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 - CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 - CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 - CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 - CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 - CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 - CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 - CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 - CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 - CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 - CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 - CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 - CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 - CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 - CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 - CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 - CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 - CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 - CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 - CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 - CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 - CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 - CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 - CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 - CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 - CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 - CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 - CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 - CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 - CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 - CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 - CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 - CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 - CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 - CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 - CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 - CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 - CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 - CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 - CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 - CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 - CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 - CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 - CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 - CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 - CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 - CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 - CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 - CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 - CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 - CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 - CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 - CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 - CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 - CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 - CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 - CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 - CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 - CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 - CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 - CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 - CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 - CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 - CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 - CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 - CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 - CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 - CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 - CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 - CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 - CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 - CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 - CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 - CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 - CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 - CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 - CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 - CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 - CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 - CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 - CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 - CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 - CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 - CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 - CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 - CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 - CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 - CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 - CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 - CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 - CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 - CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 - CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 - CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 - CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 - CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 - CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 - CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 - CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 - CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 - CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 - CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 - CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 - CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 - CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 - CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 - CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 - CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 - CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 - CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 - CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 - CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 - CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 - CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 - CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 - CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 - CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 - CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 - CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 - CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 - CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 - CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 - CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 - CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 - CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 - CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 - CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 - CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 - CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 - CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 - CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 - CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 - CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 - CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 - CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 - CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 - CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 - CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 - CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 - CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 - CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 - CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 - CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 - CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 - CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 - CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 - CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 - CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 - CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 - CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 - CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 - CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 - CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 - CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 - CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 - CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 - CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 - CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 - CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 - CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 - CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 - CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 - CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 - CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 - CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 - CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 - CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 - CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 - CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 - CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 - CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 - CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 - CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 - CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 - CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 - CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 - CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 - CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 - CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 - CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 - CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 - CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 - CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 - CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 - CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 - CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 - CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 - CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 - CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 - CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 - CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 - CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 - CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 - CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 - CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 - CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 - CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 - CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 - CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 - CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 - CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 - CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 - CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 - CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 - CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 - CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 - CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 - CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 - CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 - CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 - CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 - CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 - CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 - CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 - CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 - CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 - CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 - CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 - CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 - CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 - CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 - CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 - CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 - CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 - CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 - CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 - CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 - CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 - CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 - CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 - CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 - CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 - CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 - CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 - CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 - CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 - CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 - CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 - CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 - CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 - CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 - CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 - CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 - CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 - CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 - CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 - CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 - CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 - CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 - CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 - CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 - CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 - CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 - CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 - CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 - CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 - CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 - CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 - CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 - CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 - CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 - CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 - CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 - CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 - CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 - CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 - CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 - CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 - CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 - CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 - CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 - CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 - CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 - CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 - CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 - CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 - CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 - CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 - CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 - CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 - CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 - CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 - CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 - CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 - CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 - CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 - CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 - CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 - CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 - CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 - CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 - CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 - CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 - CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 - CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 - CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 - CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 - CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 - CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 - CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 - CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 - CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 - CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 - CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 - CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 - CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 - CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 - CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 - CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 - CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 - CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 - CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 - CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 - CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 - CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 - CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 - CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 - CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 - CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 - CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 - CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 - CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 - CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 - CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 - CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 - CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 - CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 - CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 - CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 - CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 - CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 - CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 - CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 - CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 - CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 - CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 - CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 - CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 - CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 - CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 - CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 - CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 - CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 - CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 - CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 - CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 - CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 - CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 - CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 - CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 - CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 - CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 - CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 - CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 - CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 - CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 - CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 - CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 - CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 - CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 - CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 - CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 - CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 - CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 - CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 - CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 - CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 - CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 - CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 - CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 - CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 - CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 - CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 - CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 - CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 - CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 - CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 - CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 - CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 - CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 - CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 - CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 - CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 - CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 - CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 - CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 - CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 - CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 - CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 - CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 - CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 - CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 - CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 - CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 - CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 - CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 - CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 - CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 - CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 - CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 - CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 - CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 - CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 - CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 - CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 - CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 - CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 - CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 - CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 - CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 - CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 - CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 - CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 - CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 - CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 - CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 - CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 - CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 - CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 - CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 - CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 - CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 - CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 - CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 - CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 - CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 - CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 - CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 - CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 - CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 - CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 - CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 - CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 - CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 - CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 - CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 - CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 - CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 - CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 - CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 - CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 - CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 - CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 - CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 - CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 - CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 - CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 - CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 - CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 - CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 - CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 - CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 - CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 - CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 - CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 - CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 - CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 - CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 - CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 - CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 - CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 - CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 - CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 - CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 - CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 - CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 - CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 - CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 - CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 - CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 - CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 - CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 - CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 - CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 - CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 - CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 - CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 - CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 - CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 - CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 - CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 - CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 - CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 - CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 - CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 - CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 - CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 - CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 - CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 - CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 - CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 - CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 - CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 - CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 - CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 - CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 - CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 - CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 - CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 - CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 - CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 - CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 - CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 - CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 - CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 - CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 - CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 - CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 - CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 - CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 - CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 - CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 - CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 - CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 - CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 - CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 - CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 - CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 - CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 - CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 - CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 - CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 - CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 - CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 - CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 - CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 - CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 - CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 - CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 - CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 - CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 - CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 - CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 - CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 - CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 - CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 - CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 - CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 - CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 - CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 - CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 - CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 - CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 - CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 - CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 - CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 - CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 - CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 - CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 - CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 - CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 - CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 - CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 - CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 - CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 - CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 - CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 - CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 - CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 - CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 - CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 - CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 - CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 - CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 - CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 - CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 - CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 - CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 - CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 - CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 - CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 - CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 - CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 - CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 - CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 - CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 - CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 - CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 - CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 - CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 - CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 - CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 - CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 - CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 - CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 - CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 - CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 - CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 - CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 - CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 - CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 - CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 - CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 - CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 - CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 - CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 - CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 - CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 - CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 - CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 - CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 - CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 - CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 - CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 - CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 - CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 - CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 - CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 - CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 - CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 - CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 - CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 - CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 - CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 - CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 - CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 - CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 - CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 - CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 - CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 - CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 - CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 - CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 - CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 - CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 - CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 - CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 - CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 - CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 - CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 - CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 - CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 - CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 - CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 - CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 - CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 - CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 - CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 - CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 - CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 - CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 - CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 - CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 - CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 - CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 - CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 - CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 - CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 - CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 - CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 - CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 - CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 - CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 - CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 - CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 - CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 - CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 - CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 - CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 - CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 - CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 - CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 - CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 - CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 - CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 - CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 - CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 - CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 - CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 - CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 - CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 - CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 - CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 - CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 - CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 - CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 - CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 - CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 - CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 - CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 - CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 - CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 - CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 - CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 - CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 - CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 - CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 - CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 - CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 - CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 - CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 - CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 - CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 - CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 - CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 - CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 - CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 - CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 - CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 - CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 - CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 - CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 - CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 - CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 - CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 - CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 - CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 - CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 - CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 - CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 - CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 - CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 - CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 - CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 - CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 - CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 - CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 - CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 - CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 - CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 - CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 - CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 - CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 - CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 - CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 - CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 - CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 - CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 - CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 - CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 -} cgc_pll_mul_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_clock_init(void); // Used internally by BSP - -#if BSP_TZ_NONSECURE_BUILD || BSP_ALT_BUILD -void bsp_clock_freq_var_init(void); // Used internally by BSP - -#endif - -#if BSP_TZ_SECURE_BUILD -void r_bsp_clock_up2025-07-29_callback_set(bsp_clock_up2025-07-29_callback_t p_callback, - bsp_clock_up2025-07-29_callback_args_t * p_callback_memory); - -#endif - -/* Used internally by CGC */ - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE -void bsp_prv_operating_mode_set(uint8_t operating_mode); - -#endif - -#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED -uint32_t bsp_prv_power_change_mstp_set(void); -void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); - -#endif - -void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); - -#if !BSP_FEATURE_CGC_REGISTER_SET_B -void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); - -#else -void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); -uint32_t bsp_prv_clock_source_get(void); - -#endif - -/* RTC Initialization */ -#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR -void R_BSP_Init_RTC(void); - -#endif - -#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE -bool bsp_prv_rtc_register_clock_set(bool enable); - -#endif - -#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE -bool bsp_prv_clock_prepare_pre_sleep(void); -void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); - -#endif - -/* The public function is used to get state or initialize the sub-clock. */ -#if BSP_FEATURE_RTC_IS_IRTC -fsp_err_t R_BSP_SubclockStatusGet(); -fsp_err_t R_BSP_SubclockInitialize(); - -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_common.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_common.h deleted file mode 100644 index c8afd5da6..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_common.h +++ /dev/null @@ -1,623 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_COMMON_H -#define BSP_COMMON_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include -#include - -/* Different compiler support. */ -#include "../../inc/api/fsp_common_api.h" -#include "bsp_compiler_support.h" - -/* BSP TFU Includes. */ -#include "../../src/bsp/mcu/all/bsp_tfu.h" - -#include "../../src/bsp/mcu/all/bsp_sdram.h" - -/* BSP MMF Includes. */ -#include "../../src/bsp/mcu/all/bsp_mmf.h" - -#include "bsp_cfg.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** Used to signify that an ELC event is not able to be used as an interrupt. */ -#define BSP_IRQ_DISABLED (0xFFU) - -/* Version of this module's code and API. */ - -#if 1 == BSP_CFG_RTOS /* ThreadX */ - #include "tx_user.h" - #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) - #include "tx_port.h" - #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); - #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); - #else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE - #endif -#else - #define FSP_CONTEXT_SAVE - #define FSP_CONTEXT_RESTORE -#endif - -/** Macro that can be defined in order to enable logging in FSP modules. */ -#ifndef FSP_LOG_PRINT - #define FSP_LOG_PRINT(X) -#endif - -/** Macro to log and return error without an assertion. */ -#ifndef FSP_RETURN - - #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ - return err; -#endif - -/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in - * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ -#if (1 == BSP_CFG_ASSERT) - - #ifndef FSP_ERROR_LOG - #define FSP_ERROR_LOG(err) \ - fsp_error_log((err), __FILE__, __LINE__); - #endif -#else - - #define FSP_ERROR_LOG(err) -#endif - -/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP - * functions. */ -#if (3 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) -#elif (2 == BSP_CFG_ASSERT) - #define FSP_ASSERT(a) {assert(a);} -#else - #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) -#endif // ifndef FSP_ASSERT - -/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used - * to identify runtime errors in FSP functions. */ - -#define FSP_ERROR_RETURN(a, err) \ - { \ - if ((a)) \ - { \ - (void) 0; /* Do nothing */ \ - } \ - else \ - { \ - FSP_ERROR_LOG(err); \ - return err; \ - } \ - } - -/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register up2025-07-29s. - * This macro can be redefined to add a timeout if necessary. */ -#ifndef FSP_HARDWARE_REGISTER_WAIT - #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} -#endif - -#ifndef FSP_REGISTER_READ - -/* Read a register and discard the result. */ - #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); -#endif - -/**************************************************************** - * - * This check is performed to select suitable ASM API with respect to core - * - * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so - * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ - -#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) - #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) - #endif -#else - #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION - #endif - #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) -#endif - -/* This macro defines a variable for saving previous mask value */ -#ifndef FSP_CRITICAL_SECTION_DEFINE - - #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U -#endif - -/* These macros abstract methods to save and restore the interrupt state for different architectures. */ -#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK - #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) -#else - #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI - #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI - #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ - (8U - __NVIC_PRIO_BITS))) -#endif - -/** This macro temporarily saves the current interrupt state and disables interrupts. */ -#ifndef FSP_CRITICAL_SECTION_ENTER - #define FSP_CRITICAL_SECTION_ENTER \ - old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ - FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) -#endif - -/** This macro restores the previously saved interrupt state, reenabling interrupts. */ -#ifndef FSP_CRITICAL_SECTION_EXIT - #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) -#endif - -/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ -#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) - -/** Used to signify that the requested IRQ vector is not defined in this system. */ -#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) - -/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ -#if (BSP_CFG_MCU_PART_SERIES == 8) - #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) -#else - #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) -#endif - -/* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE - #define FSP_PRIV_TZ_USE_SECURE_REGS (1) -#else - #define FSP_PRIV_TZ_USE_SECURE_REGS (0) -#endif - -/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ -#if BSP_CFG_EARLY_INIT - #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) -#else - #define BSP_SECTION_EARLY_INIT -#endif - -#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 -BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); -BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); - -#endif - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/* - * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register - * from the secure application using the provided non-secure callable functions. - */ - #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) - #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) - #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) -#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 - -/*******************************************************************************************************************//** - * Read a non-secure 8-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) -{ - p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 16-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) -{ - p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/*******************************************************************************************************************//** - * Read a non-secure 32-bit STYPE3 register in the secure state. - * - * @param[in] p_reg The address of the non-secure register. - * - * @return Value read from the register. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) -{ - p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); - - return *p_reg; -} - -/* - * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register - * using the non-secure aliased address. - */ - #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) - #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) - #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) -#else - #define FSP_STYPE3_REG8_READ(X, S) (X) - #define FSP_STYPE3_REG16_READ(X, S) (X) - #define FSP_STYPE3_REG32_READ(X, S) (X) -#endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Different warm start entry locations in the BSP. */ -typedef enum e_bsp_warm_start_event -{ - BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. - BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. - BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up -} bsp_warm_start_event_t; - -/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ -typedef enum e_fsp_priv_clock -{ - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_PCLKE = 20, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, - FSP_PRIV_CLOCK_CPUCLK = 32, -} fsp_priv_clock_t; - -/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ -typedef enum e_fsp_priv_source_clock -{ - FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator - FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator - FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator - FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator - FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator - FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output - FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output - FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output - FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output - FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output - FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output - FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output - FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output -} fsp_priv_source_clock_t; - -typedef struct st_bsp_unique_id -{ - union - { - uint32_t unique_id_words[4]; - uint8_t unique_id_bytes[16]; - }; -} bsp_unique_id_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); - -/*********************************************************************************************************************** - * Global variables (defined in other files) - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Return active interrupt vector number value - * - * @return Active interrupt vector number value - **********************************************************************************************************************/ -__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) -{ - xPSR_Type xpsr_value; - xpsr_value.w = __get_xPSR(); - - return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); -} - -/*******************************************************************************************************************//** - * Gets the frequency of a system clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) -{ -#if !BSP_FEATURE_CGC_REGISTER_SET_B - uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; - - #if BSP_FEATURE_CGC_HAS_CPUCLK - if (FSP_PRIV_CLOCK_CPUCLK == clock) - { - return SystemCoreClock; - } - - /* Get CPUCLK divisor */ - uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; - - /* Determine if either divisor is a multiple of 3 */ - if ((cpuclk_div | clock_div) & 8U) - { - /* Convert divisor settings to their actual values */ - cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); - clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); - - /* Calculate clock with multiplication and division instead of shifting */ - return (SystemCoreClock * cpuclk_div) / clock_div; - } - else - { - return (SystemCoreClock << cpuclk_div) >> clock_div; - } - - #else - uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; - - return (SystemCoreClock << iclk_div) >> clock_div; - #endif -#else - FSP_PARAMETER_NOT_USED(clock); - - return SystemCoreClock; -#endif -} - -/*******************************************************************************************************************//** - * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). - * - * @return Clock Divider - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) -{ - if (2U >= ckdivcr) - { - - /* clock_div: - * - Clock Divided by 1: 0 - * - Clock Divided by 2: 1 - * - Clock Divided by 4: 2 - */ - return 1U << ckdivcr; - } - else if (3U == ckdivcr) - { - - /* Clock Divided by 6 */ - return 6U; - } - else if (4U == ckdivcr) - { - - /* Clock Divided by 8 */ - return 8U; - } - else if (5U == ckdivcr) - { - - /* Clock Divided by 3 */ - return 3U; - } - else if (6U == ckdivcr) - { - - /* Clock Divided by 5 */ - return 5; - } - else if (7U == ckdivcr) - { - - /* Clock Divided by 10 */ - return 10; - } - else - { - /* The remaining case is ckdivcr = 8 which divides the clock by 16. */ - } - - /* Clock Divided by 16 */ - return 16U; -} - -#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI/SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) -{ - uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; - uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; - - return R_BSP_SourceClockHzGet(scispicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SPI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SPI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) -{ - uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = - (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> - R_SYSTEM_SPICKCR_CKSEL_Pos); - - return R_BSP_SourceClockHzGet(spicksel) / clock_div; -} - -#endif -#if BSP_FEATURE_BSP_HAS_SCI_CLOCK - -/*******************************************************************************************************************//** - * Gets the frequency of a SCI clock. - * - * @return Frequency of requested clock in Hertz. - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) -{ - uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); - uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = - (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, - BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> - R_SYSTEM_SCICKCR_SCICKSEL_Pos); - - return R_BSP_SourceClockHzGet(scicksel) / clock_div; -} - -#endif - -/*******************************************************************************************************************//** - * Get unique ID for this device. - * - * @return A pointer to the unique identifier structure - **********************************************************************************************************************/ -__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) -{ -#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 - - return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); -#else - - return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; -#endif -} - -/*******************************************************************************************************************//** - * Disables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheDisable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2 - - /* Writeback and flush cache when disabling - * MREF_INTERNAL_12 */ - if (R_CACHE->CCAWTA_b.WT) - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk; - } - else - { - R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; - } - - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #else - - /* Disable the C-Cache. */ - R_CACHE->CCACTL = 0U; - #endif -#endif -} - -/*******************************************************************************************************************//** - * Enables the flash cache. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_FlashCacheEnable (void) -{ -#if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invali2025-07-29 the flash cache and wait until it is invali2025-07-29d. (See section 55.3.2.2 "Operation" of the Flash Cache - * in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; -#endif - -#ifdef R_CACHE - #if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1 - - /* Configure the C-Cache line size. */ - R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; - #else - - /* Check that no flush or writeback are ongoing before enabling - * MREF_INTERNAL_13 */ - FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); - #endif - - /* Enable the C-Cache. */ - R_CACHE->CCACTL = 1U; -#endif -} - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -#if (1 == BSP_CFG_ASSERT) - -/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ -void fsp_error_log(fsp_err_t err, const char * file, int32_t line); - -#endif - -/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will - * alert the user of the error. The user can override this default behavior by defining their own - * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. - */ -#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) - - #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_compiler_support.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_compiler_support.h deleted file mode 100644 index 39f752c3c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_compiler_support.h +++ /dev/null @@ -1,109 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_COMPILER_SUPPORT_H - #define BSP_COMPILER_SUPPORT_H - - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) - #include "arm_cmse.h" - #endif - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - #if defined(__ARMCC_VERSION) /* AC6 compiler */ - -/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load - * memory (ROM) is reserved unnecessarily. */ - #define BSP_UNINIT_SECTION_PREFIX ".bss" - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__GNUC__) /* GCC compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP ".heap" - #endif - #define BSP_DONT_REMOVE __attribute__((used)) - #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) - #define BSP_FORCE_INLINE __attribute__((always_inline)) - #elif defined(__ICCARM__) /* IAR compiler */ - #define BSP_UNINIT_SECTION_PREFIX - #ifndef BSP_SECTION_HEAP - #define BSP_SECTION_HEAP "HEAP" - #endif - #define BSP_DONT_REMOVE __root - #define BSP_ATTRIBUTE_STACKLESS __stackless - #define BSP_FORCE_INLINE _Pragma("inline=forced") - #endif - - #ifndef BSP_SECTION_STACK - #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" - #endif - #ifndef BSP_SECTION_FLASH_GAP - #define BSP_SECTION_FLASH_GAP - #endif - #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" - #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" - #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" - #define BSP_SECTION_ROM_REGISTERS ".rom_registers" - #define BSP_SECTION_ID_CODE ".id_code" - -/* Compiler neutral macros. */ - #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) - - #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) - - #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED - - #define BSP_WEAK_REFERENCE __attribute__((weak)) - -/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ - #define BSP_STACK_ALIGNMENT (8) - -/*********************************************************************************************************************** - * TrustZone definitions - **********************************************************************************************************************/ - #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) - #if defined(__ICCARM__) /* IAR compiler */ - #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call - #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry - #else - #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) - #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) - #endif - #else - #define BSP_CMSE_NONSECURE_CALL - #define BSP_CMSE_NONSECURE_ENTRY - #endif - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/** @} (end of addtogroup BSP_MCU) */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_delay.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_delay.h deleted file mode 100644 index 94a13ccff..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_delay.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_DELAY_H -#define BSP_DELAY_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "bsp_compiler_support.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* The number of cycles required per software delay loop. */ -#ifndef BSP_DELAY_LOOP_CYCLES - #if defined(RENESAS_CORTEX_M85) - -/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for - * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in - * this case. */ - #if defined(__ICCARM__) - #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) - #else - #define BSP_DELAY_LOOP_CYCLES (1) - #endif - #else - #define BSP_DELAY_LOOP_CYCLES (4) - #endif -#endif - -/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle - * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures - * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count - * of 0. */ -#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) - -/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ -typedef enum -{ - BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds - BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds - BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds -} bsp_delay_units_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_elc.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_elc.h deleted file mode 100644 index 9a2207791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_elc.h +++ /dev/null @@ -1,378 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_ELC_H -#define BSP_ELC_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU_RA6M5 - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* UNCRUSTIFY-OFF */ - -/** Sources of event signals to be linked to other peripherals or the CPU - * @note This list is device specific. - * */ -typedef enum e_elc_event_ra6m5 -{ - ELC_EVENT_NONE = (0x0), // Link disabled - ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 - ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 - ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 - ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 - ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 - ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 - ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 - ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 - ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 - ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 - ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 - ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 - ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 - ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 - ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 - ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 - ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end - ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end - ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end - ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end - ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end - ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end - ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end - ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end - ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete - ELC_EVENT_DTC_END = (0x02A), // DTC transfer end - ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error - ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode - ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt - ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt - ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt - ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt - ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop - ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry - ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt - ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A - ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B - ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt - ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A - ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt - ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A - ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B - ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt - ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A - ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B - ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt - ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A - ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B - ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt - ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A - ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt - ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt - ELC_EVENT_CAN_GLERR = (0x05A), // Global error - ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 - ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 - ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 - ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 - ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 - ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 - ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 - ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 - ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt - ELC_EVENT_CAN0_CHERR = (0x064), // Channel error - ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt - ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request - ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt - ELC_EVENT_CAN1_CHERR = (0x068), // Channel error - ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt - ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request - ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x073), // Receive data full - ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x075), // Transmit end - ELC_EVENT_IIC0_ERI = (0x076), // Transfer error - ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x078), // Receive data full - ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x080), // Transfer error - ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request - ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full - ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt - ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt - ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt - ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow - ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow - ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow - ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow - ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow - ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch - ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt - ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x180), // Receive data full - ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x182), // Transmit end - ELC_EVENT_SCI0_ERI = (0x183), // Receive error - ELC_EVENT_SCI0_AM = (0x184), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x186), // Receive data full - ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x188), // Transmit end - ELC_EVENT_SCI1_ERI = (0x189), // Receive error - ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI2_ERI = (0x18F), // Receive error - ELC_EVENT_SCI3_RXI = (0x192), // Receive data full - ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x194), // Transmit end - ELC_EVENT_SCI3_ERI = (0x195), // Receive error - ELC_EVENT_SCI3_AM = (0x196), // Address match event - ELC_EVENT_SCI4_RXI = (0x198), // Receive data full - ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI4_ERI = (0x19B), // Receive error - ELC_EVENT_SCI4_AM = (0x19C), // Address match event - ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI5_AM = (0x1A2), // Address match event - ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI6_AM = (0x1A8), // Address match event - ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI7_AM = (0x1AE), // Address match event - ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error - ELC_EVENT_SCI8_AM = (0x1B4), // Address match event - ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error - ELC_EVENT_SCI9_AM = (0x1BA), // Address match event - ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 - ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 - ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 - ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 - ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 - ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 - ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 - ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 - ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle - ELC_EVENT_SPI0_ERI = (0x1C7), // Error - ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle - ELC_EVENT_SPI1_ERI = (0x1CC), // Error - ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event - ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error - ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error - ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error - ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt - ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt - ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt -} elc_event_t; - -#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) - -#define ELC_PERIPHERAL_NUM (19U) -#define BSP_OVERRIDE_ELC_PERIPHERAL_T -/** Possible peripherals to be linked to event signals - * @note This list is device specific. - * */ -typedef enum e_elc_peripheral -{ - ELC_PERIPHERAL_GPT_A = (0), - ELC_PERIPHERAL_GPT_B = (1), - ELC_PERIPHERAL_GPT_C = (2), - ELC_PERIPHERAL_GPT_D = (3), - ELC_PERIPHERAL_GPT_E = (4), - ELC_PERIPHERAL_GPT_F = (5), - ELC_PERIPHERAL_GPT_G = (6), - ELC_PERIPHERAL_GPT_H = (7), - ELC_PERIPHERAL_ADC0 = (8), - ELC_PERIPHERAL_ADC0_B = (9), - ELC_PERIPHERAL_ADC1 = (10), - ELC_PERIPHERAL_ADC1_B = (11), - ELC_PERIPHERAL_DAC0 = (12), - ELC_PERIPHERAL_DAC1 = (13), - ELC_PERIPHERAL_IOPORT1 = (14), - ELC_PERIPHERAL_IOPORT2 = (15), - ELC_PERIPHERAL_IOPORT3 = (16), - ELC_PERIPHERAL_IOPORT4 = (17), - ELC_PERIPHERAL_CTSU = (18) -} elc_peripheral_t; - -/** Positions of event link set registers (ELSRs) available on this MCU */ -#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) - -/* UNCRUSTIFY-ON */ -/** @} (end addtogroup BSP_MCU_RA6M5) */ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_exceptions.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_exceptions.h deleted file mode 100644 index f388be329..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_exceptions.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_EXCEPTIONS_H - #define BSP_EXCEPTIONS_H - - #ifdef __cplusplus -extern "C" { - #endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ -typedef enum IRQn -{ - Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ - HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ - MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ - SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSV_IRQn = -2, /* 14 Pendable request for system service */ - SysTick_IRQn = -1, /* 15 System Tick Timer */ -} IRQn_Type; - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_feature.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_feature.h deleted file mode 100644 index 29f6b43f1..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_feature.h +++ /dev/null @@ -1,588 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_FEATURE_H -#define BSP_FEATURE_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include "bsp_peripheral.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ -#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) -#if (BSP_CFG_XTAL_HZ >= (20000000)) - #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (16000000)) - #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#elif (BSP_CFG_XTAL_HZ >= (8000000)) - #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#else - #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) -#endif - -// *UNCRUSTIFY-OFF* - -#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. -#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. -#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. -#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available. -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0xFFFFUL) // Create the mask for the valid calibration data provided by TSCDR. -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. -#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FFUL) // Mask of available channels in ADC unit 0. -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007UL) // Mask of available channels in ADC unit 1. -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. - -#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. -#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. - -#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. -#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. -#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. -#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. - -#define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. -#define BSP_FEATURE_BSP_FLASH_CACHE (1UL) // Flash cache is present. -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. -#define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. -#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. -#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1UL) // Indicates there is a separate clock for the CEC. -#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. -#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. -#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. -#define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. -#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. -#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. -#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0UL) // Indicates there is a separate clock for the I3C. -#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. -#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. -#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. -#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. -#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. -#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. -#define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. -#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. -#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. -#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. -#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. -#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. -#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. -#define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. -#define BSP_FEATURE_BSP_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. -#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. -#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. -#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. -#define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. -#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. -#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. -#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. -#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. -#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. -#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. -#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. - -#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. -#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. -#define BSP_FEATURE_CANFD_LITE (0UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. -#define BSP_FEATURE_CANFD_NUM_CHANNELS (2UL) // Number of CANFD channels per CANFD peripheral instance. -#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. - -#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. -#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. -#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. -#define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. -#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. -#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. -#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. -#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. -#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. -#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. -#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. -#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. -#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. -#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. -#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. -#define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. -#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. -#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. -#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. -#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. -#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. -#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. -#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. -#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (24000000UL) // Maximum input frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000UL) // Minimum output frequency for PLL unit 1. -#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. -#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. -#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (200000000UL) // PLL VCO maximum frequency. -#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. -#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. -#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. -#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. -#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. -#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. -#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. -#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. - -#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. -#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. -#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. -#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. - -#define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. -#define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA (1UL) // RSA support is available. -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1UL) // RSA support with key-wrapping is available. - -#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. -#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. - -#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. -#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. -#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. -#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. -#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. - -#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) -#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. - -#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. -#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. - -#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. -#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. - -#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. - -#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. - -#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. - -#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. - -#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1UL) // Number of available ethernet PHYs. -#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. -#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. - -#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. -#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. -#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. -#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. -#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. -#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. -#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). -#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). -#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). -#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. - -#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) -#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. -#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. -#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. -#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. -#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. - -#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. -#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. -#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. -#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). -#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). -#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x03FFUL) // Mask of channels that support event count input (has GTUPSR register). -#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. -#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. -#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. -#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. -#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. -#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x03FFUL) // Mask of channels that support dead time control. -#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. -#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. -#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. -#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. -#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. -#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. -#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. -#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. - -#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) -#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. -#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. -#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. -#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. -#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. -#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. -#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. -#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. -#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. -#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. -#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FF0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. - -#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. -#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. -#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. -#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. - -#define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. -#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. - -#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) -#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. -#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. - -#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. -#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. -#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. -#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. -#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. -#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. -#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. -#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. -#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. -#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. -#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. -#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. -#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. -#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. -#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. -#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. -#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. -#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. -#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. - -#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) -#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. -#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. -#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. -#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. -#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. -#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. -#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. -#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. -#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. -#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. -#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. - -#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. - -#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000UL) // Start address of the CS0 memory mapped region for OSPI. -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000UL) // Start address of the CS1 memory mapped region for OSPI. - -#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) -#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. -#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. -#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. - -#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. - -#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. -#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. -#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RISP_E11A. -#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. -#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. -#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. -#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. -#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. -#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. -#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. -#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. - -#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) -#define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. -#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. -#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. -#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. -#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. -#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. - -#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x03F9UL) // Mask of channels with data compare match (DCCR) available. -#define BSP_FEATURE_SCI_CHANNELS (0x03FFUL) // Mask of available SCI channels. -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. -#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. -#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. -#define BSP_FEATURE_SCI_LIN_CHANNELS (0x06UL) // Mask of channels that can support LIN. -#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. -#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x06UL) // List of channels that do not support ABCSE functionality. -#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9UL) // Mask of channels which support CTS external pins. -#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x03F9UL) // Mask of channels which support the UART FIFO. -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. -#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. - -#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. -#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. - -#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. - -#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) -#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. - -#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. -#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. -#define BSP_FEATURE_SPI_MAX_CHANNEL (2UL) // Number of available SPI channels. -#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. - -#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. - -#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. - -#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. - -#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. - -#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) -#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. -#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. - -#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. - -#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) -#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. -#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. -#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. -#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. - -#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) -#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. -#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. - -#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) -#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. -#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. - -#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) -#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. -#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. -#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. -#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. -#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. -#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. -#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. -#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. -#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. -#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. -#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. -#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. -#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_group_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_group_irq.h deleted file mode 100644 index 5aede0736..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_group_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GROUP_IRQ_H -#define BSP_GROUP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#ifndef BSP_OVERRIDE_GROUP_IRQ_T - -/** Which interrupts can have callbacks registered. */ -typedef enum e_bsp_grp_irq -{ - BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred - BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred - BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt - BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt - BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt - BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected - BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt - BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error - BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error - BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error - BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error - BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error - BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error - BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error -} bsp_grp_irq_t; - -#endif - -/* Callback type. */ -typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_group_interrupt_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_guard.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_guard.h deleted file mode 100644 index 9bf7d90b7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_guard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_GUARD_H -#define BSP_GUARD_H - -#include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * - * @{ - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD -BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUp2025-07-29CallbackSet(bsp_clock_up2025-07-29_callback_t p_callback, - bsp_clock_up2025-07-29_callback_args_t * p_callback_memory); - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_io.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_io.h deleted file mode 100644 index 418c75380..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_io.h +++ /dev/null @@ -1,465 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @defgroup BSP_IO BSP I/O access - * @ingroup RENESAS_COMMON - * @brief This module provides basic read/write access to port pins. - * - * @{ - **********************************************************************************************************************/ - -#ifndef BSP_IO_H -#define BSP_IO_H - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) -#define BSP_IO_PRV_8BIT_MASK (0xFF) -#define BSP_IO_PWPR_B0WI_OFFSET (7U) -#define BSP_IO_PWPR_PFSWE_OFFSET (6U) -#define BSP_IO_PFS_PDR_OUTPUT (4U) -#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Levels that can be set and read for individual pins */ -typedef enum e_bsp_io_level -{ - BSP_IO_LEVEL_LOW = 0, ///< Low - BSP_IO_LEVEL_HIGH ///< High -} bsp_io_level_t; - -/** Direction of individual pins */ -typedef enum e_bsp_io_dir -{ - BSP_IO_DIRECTION_INPUT = 0, ///< Input - BSP_IO_DIRECTION_OUTPUT ///< Output -} bsp_io_direction_t; - -/** Superset list of all possible IO ports. */ -typedef enum e_bsp_io_port -{ - BSP_IO_PORT_00 = 0x0000, ///< IO port 0 - BSP_IO_PORT_01 = 0x0100, ///< IO port 1 - BSP_IO_PORT_02 = 0x0200, ///< IO port 2 - BSP_IO_PORT_03 = 0x0300, ///< IO port 3 - BSP_IO_PORT_04 = 0x0400, ///< IO port 4 - BSP_IO_PORT_05 = 0x0500, ///< IO port 5 - BSP_IO_PORT_06 = 0x0600, ///< IO port 6 - BSP_IO_PORT_07 = 0x0700, ///< IO port 7 - BSP_IO_PORT_08 = 0x0800, ///< IO port 8 - BSP_IO_PORT_09 = 0x0900, ///< IO port 9 - BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 - BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 - BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 - BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 - BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 -} bsp_io_port_t; - -/** Superset list of all possible IO port pins. */ -typedef enum e_bsp_io_port_pin_t -{ - BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 - BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port -} bsp_io_port_pin_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern volatile uint32_t g_protect_pfswe_counter; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Read the current input level of the pin. - * - * @param[in] pin The pin - * - * @retval Current input level - **********************************************************************************************************************/ -__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) -{ - /* Read pin level. */ - return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; -} - -/*******************************************************************************************************************//** - * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS - * protection using R_BSP_PinAccessEnable() before calling this function. - * - * @param[in] pin The pin - * @param[in] level The level - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) -{ - /* Clear PMR, ASEL, ISEL and PODR bits. */ - uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; - pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; - - /* Set output level and pin direction to output. */ - uint32_t lvl = ((uint32_t) level | pfs_bits); -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); -#endif -} - -/*******************************************************************************************************************//** - * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling - * this function. - * - * @param[in] pin The pin - * @param[in] cfg Configuration for the pin (PmnPFS register setting) - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) -{ - /* Configure a pin. */ -#if (3U == BSP_FEATURE_IOPORT_VERSION) - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; -#else - R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; -#endif -} - -/*******************************************************************************************************************//** - * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur - * via multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessEnable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** If this is first entry then allow writing of PFS. */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled - #endif - } - - /** Increment the protect counter */ - g_protect_pfswe_counter++; - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/*******************************************************************************************************************//** - * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via - * multiple threads or an ISR re-entering this code. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_PinAccessDisable (void) -{ -#if BSP_CFG_PFS_PROTECT - - /** Get the current state of interrupts */ - FSP_CRITICAL_SECTION_DEFINE; - FSP_CRITICAL_SECTION_ENTER; - - /** Is it safe to disable PFS register? */ - if (0 != g_protect_pfswe_counter) - { - /* Decrement the protect counter */ - g_protect_pfswe_counter--; - } - - /** Is it safe to disable writing of PFS? */ - if (0 == g_protect_pfswe_counter) - { - #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) - R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled - R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled - #else - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled - #endif - } - - /** Restore the interrupt state */ - FSP_CRITICAL_SECTION_EXIT; -#endif -} - -/** @} (end addtogroup BSP_IO) */ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_irq.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_irq.h deleted file mode 100644 index ad971f32e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_irq.h +++ /dev/null @@ -1,238 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/** @} (end addtogroup BSP_MCU) */ - -#ifndef BSP_IRQ_H -#define BSP_IRQ_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ -extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @brief Sets the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @param[in] p_context ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - gp_renesas_isr_context[irq] = p_context; -} - -/*******************************************************************************************************************//** - * @brief Finds the ISR context associated with the requested IRQ. - * - * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this - * function. - * @return ISR context for IRQ. - **********************************************************************************************************************/ -__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) -{ - /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of - * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ - return gp_renesas_isr_context[irq]; -} - -#if BSP_CFG_INLINE_IRQ_FUNCTIONS - - #if BSP_FEATURE_ICU_HAS_IELSR - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit - * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) -{ - /* Clear the IR bit in the selected IELSR register. */ - R_ICU->IELSR_b[irq].IR = 0U; - - /* Read back the IELSR register to ensure that the IR bit is cleared. - * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ - FSP_REGISTER_READ(R_ICU->IELSR[irq]); -} - - #endif - -/*******************************************************************************************************************//** - * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) -{ - #if BSP_FEATURE_ICU_HAS_IELSR - - /* Clear the IR bit in the selected IELSR register. */ - R_BSP_IrqStatusClear(irq); - - /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ - __DMB(); - #endif - - /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context. - * - * @param[in] irq The IRQ to configure. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions - * every time a priority is configured in the NVIC. */ - #if (4U == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (33 == __CORTEX_M) - NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); - #elif (23 == __CORTEX_M) - NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); - #else - NVIC_SetPriority(irq, priority); - #endif - - /* Store the context. The context is recovered in the ISR. */ - R_FSP_IsrContextSet(irq, p_context); -} - -/*******************************************************************************************************************//** - * Enable the IRQ in the NVIC (Without clearing the pending bit). - * - * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex - * Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) -{ - /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions - * every time an interrupt is enabled in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - - __COMPILER_BARRIER(); - NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - __COMPILER_BARRIER(); -} - -/*******************************************************************************************************************//** - * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. - * - * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed - * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) -{ - /* Clear pending interrupts in the ICU and NVIC. */ - R_BSP_IrqClearPending(irq); - - /* Enable the IRQ in the NVIC. */ - R_BSP_IrqEnableNoClear(irq); -} - -/*******************************************************************************************************************//** - * Disables interrupts in the NVIC. - * - * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are - * only those for the Cortex Processor Exceptions Numbers. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) -{ - /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system - * exceptions every time an interrupt is cleared in the NVIC. */ - uint32_t _irq = (uint32_t) irq; - NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); - - __DSB(); - __ISB(); -} - -/*******************************************************************************************************************//** - * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. - * - * @param[in] irq Interrupt number. - * @param[in] priority NVIC priority of the interrupt - * @param[in] p_context The interrupt context is a pointer to data required in the ISR. - * - * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. - **********************************************************************************************************************/ -__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) -{ - R_BSP_IrqCfg(irq, priority, p_context); - R_BSP_IrqEnable(irq); -} - -#else - #if BSP_FEATURE_ICU_HAS_IELSR -void R_BSP_IrqStatusClear(IRQn_Type irq); - - #endif -void R_BSP_IrqClearPending(IRQn_Type irq); -void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); -void R_BSP_IrqEnableNoClear(IRQn_Type const irq); -void R_BSP_IrqEnable(IRQn_Type const irq); -void R_BSP_IrqDisable(IRQn_Type const irq); -void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); - -#endif - -/*******************************************************************************************************************//** - * @internal - * @addtogroup BSP_MCU_PRV Internal BSP Documentation - * @ingroup RENESAS_INTERNAL - * @{ - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_irq_cfg(void); // Used internally by BSP - -/** @} (end addtogroup BSP_MCU_PRV) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_macl.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_macl.h deleted file mode 100644 index 416228d5c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_macl.h +++ /dev/null @@ -1,164 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_MACL -#define RENESAS_MACL - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -#include -#include "bsp_api.h" - -#if BSP_FEATURE_MACL_SUPPORTED - #if __has_include("arm_math_types.h") - -/* Ignore certain math warnings in ARM CMSIS DSP headers */ - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wsign-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-conversion" - #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" - #elif defined(__GNUC__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wfloat-conversion" - #endif - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_suppress=Pe223 - #endif - - #include "arm_math_types.h" - #include "dsp/basic_math_functions.h" - #include "dsp/matrix_functions.h" - #include "dsp/filtering_functions.h" - #include "dsp/support_functions.h" - #include "dsp/fast_math_functions.h" - - #if defined(__IAR_SYSTEMS_ICC__) - #pragma diag_default=Pe223 - #endif - #if defined(__ARMCC_VERSION) - #pragma clang diagnostic pop - #elif defined(__GNUC__) - #pragma GCC diagnostic pop - #endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MACL - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Common macro used by MACL */ - #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) - #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) - - #define BSP_MACL_SHIFT_SIGN (0x80) - #define BSP_MACL_SHIFT_1_BIT (1U) - #define BSP_MACL_SHIFT_30_BIT (30U) - #define BSP_MACL_SHIFT_31_BIT (31U) - #define BSP_MACL_SHIFT_32_BIT (32U) - - #define BSP_MACL_32_BIT (32U) - - #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 - #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 - - #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 - #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 - - #define BSP_MACL_CLEAR_MULR_REG (0x0U) - - #define BSP_MACL_POSITIVE_NUM (0U) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); -void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, - const arm_matrix_instance_q31 * p_src_b, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); -void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, - q31_t scale_fract, - int32_t shift, - arm_matrix_instance_q31 * p_dst); -void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); -void R_BSP_MaclConvQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); -arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst, - uint32_t first_idx, - uint32_t num_points); - -void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - uint32_t block_size); - -void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, - uint32_t src_a_len, - const q31_t * p_src_b, - uint32_t src_b_len, - q31_t * p_dst); - -void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, - const q31_t * p_src, - q31_t * p_dst, - q31_t * p_scratch_in, - uint32_t block_size); - -void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, - const q31_t * p_src, - q31_t * p_ref, - q31_t * p_out, - q31_t * p_err, - uint32_t block_size); - -void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); - -/******************************************************************************************************************//** - * @} (end addtogroup BSP_MACL) - **********************************************************************************************************************/ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - - #endif -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_api.h deleted file mode 100644 index 344e96aeb..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_api.h +++ /dev/null @@ -1,56 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MCU_API_H -#define BSP_MCU_API_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -typedef struct st_bsp_event_info -{ - IRQn_Type irq; - elc_event_t event; -} bsp_event_info_t; - -typedef enum e_bsp_clocks_octaclk_div -{ - BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 - BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 - BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 - BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 - BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 - BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 - BSP_CLOCKS_OCTACLK_DIV_5 ///< Divide OCTA source clock by 5 -} bsp_clocks_octaclk_div_t; - -typedef enum e_bsp_clocks_source -{ - BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. - BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. - BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. - BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. - BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. - BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. - BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. -} bsp_clocks_source_t; - -typedef struct st_bsp_octaclk_settings -{ - bsp_clocks_source_t source_clock; ///< OCTACLK source clock - bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider -} bsp_octaclk_settings_t; - -void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); -void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); -fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); -void R_BSP_OctaclkUp2025-07-29(bsp_octaclk_settings_t * p_octaclk_setting); -void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_pn_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 5fa7c22e2..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BH3CFP - #define BSP_MCU_FEATURE_SET ('B') - #define BSP_ROM_SIZE_BYTES (2097152) - #define BSP_RAM_SIZE_BYTES (524288) - #define BSP_DATA_FLASH_SIZE_BYTES (8192) - #define BSP_PACKAGE_LQFP - #define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_family_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_family_cfg.h deleted file mode 100644 index a4c302306..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,394 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - - #include "bsp_mcu_device_pn_cfg.h" - #include "bsp_mcu_device_cfg.h" - #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" - #include "bsp_clock_cfg.h" - #define BSP_MCU_GROUP_RA6M5 (1) - #define BSP_LOCO_HZ (32768) - #define BSP_MOCO_HZ (8000000) - #define BSP_SUB_CLOCK_HZ (32768) - #if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (16000000) - #elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - - #define BSP_CFG_FLL_ENABLE (0) - - #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) - #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) - - #if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (0) - #endif - - /* TrustZone Settings */ - #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) - #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) - #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - - /* CMSIS TrustZone Settings */ - #define SCB_CSR_AIRCR_INIT (1) - #define SCB_AIRCR_BFHFNMINS_VAL (0) - #define SCB_AIRCR_SYSRESETREQS_VAL (1) - #define SCB_AIRCR_PRIS_VAL (0) - #define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL - #define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL - #define FPU_FPCCR_TS_VAL (1U) -#endif - #define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL - #define FPU_FPCCR_CLRONRET_VAL (1) -#endif - - /* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE - #define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - - /* Type 1 Peripheral Security Attribution */ - - /* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - - /* Type 2 Peripheral Security Attribution */ - - /* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - - /* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR - /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ -#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) -#define BSP_TZ_CFG_LVDSAR (0U) -#else -#define BSP_TZ_CFG_LVDSAR (3U) -#endif -#endif - - /* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif - /* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - - /* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFE0E402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - - /* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - - /* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - - /* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - - /* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - - /* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - - /* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - - /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED - #define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - - /* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - - /* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ - #define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - - /* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR - #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - - /* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA - /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ - #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - - /* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA - #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif - /* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB - #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - - /* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK - #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - - - #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) - #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) - #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) - #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) - #define OFS_SEQ5 (1 << 28) | (1 << 30) - #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - - /* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) -#else - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - - #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - - /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ - #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - - /* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL - #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - - /* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 - #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif - /* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 - #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif - /* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 - #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif - /* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 - #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif - /* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 - #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif - /* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 - #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif - /* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 - #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif - /* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 - #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif - /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 - #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif - /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 - #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif - /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 - #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif - /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 - #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif - /* Security Attribution for Bank Select Register */ -#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL - #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT - #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_info.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_info.h deleted file mode 100644 index 53c1844b3..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mcu_info.h +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup BSP_MCU - * @defgroup BSP_MCU_RA6M5 RA6M5 - * @includedoc config_bsp_ra6m5_fsp.html - * @{ - **********************************************************************************************************************/ - -/** @} (end defgroup BSP_MCU_RA6M5) */ - -#ifndef BSP_MCU_INFO_H -#define BSP_MCU_INFO_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* BSP MCU Specific Includes. */ -#include "bsp_elc.h" -#include "bsp_feature.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -typedef elc_event_t bsp_interrupt_event_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mmf.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mmf.h deleted file mode 100644 index 9b7f1b143..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_mmf.h +++ /dev/null @@ -1,141 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MMF_H -#define BSP_MMF_H - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ -#include "bsp_api.h" - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ -#define MEMORY_MIRROR_REG_KEY (0xDBU) -#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes -#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) - -/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ -#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Enum for state of Memory Mirror Function. */ -typedef enum e_mmf_state -{ - MEMORY_MIRROR_DISABLED = 0, - MEMORY_MIRROR_ENABLED = 1, -} mmf_state_t; - -/** Status instance of Memory Mirror Function. */ -typedef struct st_mmf_status -{ - mmf_state_t mmf_state; // Current state of Memory Mirror Region. - uint32_t mmf_cur_addr; // Current address in register MMSFR. -} mmf_status_t; - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Get the current status of Memory Mirror. - * - * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. - * - * @retval FSP_SUCCESS MMF status retrieved successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. - * - * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that variable for storing the status of MMF was provided. */ - if (NULL == p_mmf_status) - { - return FSP_ERR_ASSERTION; - } - #endif - - p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; - p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(p_mmf_status); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/*******************************************************************************************************************//** - * Set address for MMF region. - * - * @param[in] addr Address of memory region to be mirrored into MMF region. - * - * @retval FSP_SUCCESS Address is set successfully. - * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. - * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. - * - * This function sets the memory address to be mirrored by MMF. - **********************************************************************************************************************/ -__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) -{ -#if BSP_FEATURE_BSP_MMF_SUPPORTED - #if BSP_CFG_PARAM_CHECKING_ENABLE - - /* Ensure that requested address is in supported range and must align with 128 */ - if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) - { - return FSP_ERR_INVALID_ADDRESS; - } - #endif - - /* If MMF is enabled, disable MMF before updating the address register. - * For disabling MMF, write 0xDB00 to register MMEN. */ - if (1U == R_MMF->MMEN_b.EN) - { - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); - } - - R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); - - /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into - * MMF region. */ - R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); - - return FSP_SUCCESS; -#else - FSP_PARAMETER_NOT_USED(addr); - - return FSP_ERR_UNSUPPORTED; -#endif -} - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif - -/** @} (end addtogroup BSP_MCU) */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_module_stop.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_module_stop.h deleted file mode 100644 index d7312cbe8..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_module_stop.h +++ /dev/null @@ -1,371 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_MODULE_H -#define BSP_MODULE_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TZ_HAS_TRUSTZONE - -/* MSTPCRA is located in R_MSTP for Star devices. */ - #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) -#else - -/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ - #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) -#endif - -/*******************************************************************************************************************//** - * Cancels the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= \ - (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/*******************************************************************************************************************//** - * Enables the module stop state. - * - * @param ip fsp_ip_t enum value for the module to be stopped - * @param channel The channel. Use channel 0 for modules without channels. - **********************************************************************************************************************/ -#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ - BSP_DELAY_UNITS_MICROSECONDS); \ - FSP_CRITICAL_SECTION_EXIT;} -#else - #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} -#endif - -/** @} (end addtogroup BSP_MCU) */ - -#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD - #if !BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) - #else - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ - channel) ? (1U << 5U) : (1U << 6U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - - #if BSP_MCU_GROUP_RA2A2 - -/* RA2A2 has a combination of AGT and AGTW. - * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) - * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) - * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) - * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) - */ - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ - ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - ? (3U - channel) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ - ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ - : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ - ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 2U) \ - : (10U - channel + \ - BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ - 4U))))); - - #else - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #if BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #else - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); - #endif - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t -#else - #if (2U == BSP_FEATURE_ELC_VERSION) - #if BSP_MCU_GROUP_RA6T2 - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #elif BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ - (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #endif - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t - #else - #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) - #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ - channel) ? (1U << (3U - channel)) : (1U << \ - (15U - \ - (channel - 4U)))); - #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE - #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); - #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t - #endif -#endif - -#define BSP_MSTP_REG_FSP_IP_EXTRA(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_EXTRA(channel) (1U << (16U)); - -#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA -#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t - -#if BSP_FEATURE_CGC_REGISTER_SET_B - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t -#else - #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); -#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB -#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t -#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC -#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD -#if BSP_MCU_GROUP_NEPTUNE - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); -#else - #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#endif -#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t -#if (BSP_PERIPHERAL_DAC8_PRESENT) - #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD - #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t -#endif -#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); -#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t -#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t -#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) - #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t - #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA - #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); - #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_pin_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_pin_cfg.h deleted file mode 100644 index a76ce7dea..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_pin_cfg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_PIN_CFG_H_ -#define BSP_PIN_CFG_H_ -#include "r_ioport.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - - -extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFP.pincfg */ - -void BSP_PinConfigSecurityInit(); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif /* BSP_PIN_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_register_protection.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_register_protection.h deleted file mode 100644 index ca4b64c20..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_register_protection.h +++ /dev/null @@ -1,60 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_REGISTER_PROTECTION_H -#define BSP_REGISTER_PROTECTION_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/** The different types of registers that can be protected. */ -typedef enum e_bsp_reg_protect -{ - /** Enables writing to the registers related to the clock generation circuit. */ - BSP_REG_PROTECT_CGC = 0, - - /** Enables writing to the registers related to operating modes, low power consumption, and battery backup - * function. */ - BSP_REG_PROTECT_OM_LPC_BATT, - - /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, - * LVD2CR1, LVD2SR. */ - BSP_REG_PROTECT_LVD, - - /** Enables writing to the registers related to the security function. */ - BSP_REG_PROTECT_SAR, -} bsp_reg_protect_t; - -/** @} (end addtogroup BSP_MCU) */ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -/* Public functions defined in bsp.h */ -void bsp_register_protect_open(void); // Used internally by BSP - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_sdram.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_sdram.h deleted file mode 100644 index 5ba56a638..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SDRAM_H -#define BSP_SDRAM_H - -#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_SdramInit(bool init_memory); -void R_BSP_SdramSelfRefreshEnable(void); -void R_BSP_SdramSelfRefreshDisable(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER -#endif -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_security.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_security.h deleted file mode 100644 index 3ceb51f92..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_security.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef BSP_SECURITY_H -#define BSP_SECURITY_H - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ -void R_BSP_NonSecureEnter(void); - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_tfu.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_tfu.h deleted file mode 100644 index 98b09caee..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/bsp_tfu.h +++ /dev/null @@ -1,218 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef RENESAS_TFU -#define RENESAS_TFU - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* Mathematical Functions includes. */ -#ifdef __cplusplus - #include -#else - #include -#endif - -/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -#if BSP_FEATURE_TFU_SUPPORTED - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - - #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f - - #ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) - -/* No form of inline is available, it happens only when -std=c89, gnu89 and - * above are OK */ - #warning \ - "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ - -/* gnu89 semantics of inline and extern inline are essentially the exact - * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) - #endif - #endif - #elif __ICCARM__ - #define BSP_TFU_INLINE - #else - #error "Compiler not supported!" - #endif - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Inline Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Calculates sine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Sine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __sinf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - return R_TFU->SCDT1; -} - -/*******************************************************************************************************************//** - * Calculates cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * - * @retval Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __cosf (float angle) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read cos from R_TFU->SCDT1 */ - return R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates sine and cosine of the given angle. - * @param[in] angle The value of an angle in radian. - * @param[out] sin Sine value of an angle. - * @param[out] cos Cosine value of an angle. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) -{ - /* Set the angle to R_TFU->SCDT1 */ - R_TFU->SCDT1 = angle; - - /* Read sin from R_TFU->SCDT1 */ - *sin = R_TFU->SCDT1; - - /* Read sin from R_TFU->SCDT1 */ - *cos = R_TFU->SCDT0; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-Axis cordinate value. - * @param[in] x_cord X-Axis cordinate value. - * - * @retval Arc tangent for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) -{ - /* Set X-cordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-cordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - return R_TFU->ATDT1; -} - -/*******************************************************************************************************************//** - * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * - * @retval Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - -/*******************************************************************************************************************//** - * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. - * @param[in] y_cord Y-cordinate value. - * @param[in] x_cord X-cordinate value. - * @param[out] atan2 Arc tangent for given values. - * @param[out] hypot Hypotenuse for given values. - **********************************************************************************************************************/ - #if __ICCARM__ - #pragma inline = forced - #endif -BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) -{ - /* Set X-coordinate to R_TFU->ATDT0 */ - R_TFU->ATDT0 = x_cord; - - /* set Y-coordinate to R_TFU->ATDT1 */ - R_TFU->ATDT1 = y_cord; - - /* Read arctan(y/x) from R_TFU->ATDT1 */ - *atan2 = R_TFU->ATDT1; - - /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ - *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; -} - - #if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) - #endif - -/*********************************************************************************************************************** - * Exported global functions (to be accessed by other files) - **********************************************************************************************************************/ - -#endif - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif /* RENESAS_TFU */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_common_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_common_api.h deleted file mode 100644 index 0d2a71791..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_common_api.h +++ /dev/null @@ -1,380 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_COMMON_API_H -#define FSP_COMMON_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include -#include - -/* Includes FSP version macros. */ -#include "fsp_version.h" - -/*******************************************************************************************************************//** - * @ingroup RENESAS_COMMON - * @defgroup RENESAS_ERROR_CODES Common Error Codes - * All FSP modules share these common error codes. - * @{ - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing - * about using this implementation is that it does not take any extra RAM or ROM. */ - -#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) - -/** Determine if a C++ compiler is being used. - * If so, ensure that standard C is used to process the API information. */ -#if defined(__cplusplus) - #define FSP_CPP_HEADER extern "C" { - #define FSP_CPP_FOOTER } -#else - #define FSP_CPP_HEADER - #define FSP_CPP_FOOTER -#endif - -/** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically - * defined on the Secure side. */ -#define FSP_SECURE_ARGUMENT (NULL) - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Common error codes */ -typedef enum e_fsp_err -{ - FSP_SUCCESS = 0, - - FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed - FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location - FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter - FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist - FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode - FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API - FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open - FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy - FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h - FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked - FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP - FSP_ERR_OVERFLOW = 12, ///< Hardware overflow - FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow - FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration - FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result - FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason - FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met - FSP_ERR_ABORTED = 18, ///< An operation was aborted - FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled - FSP_ERR_TIMEOUT = 20, ///< Timeout error - FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied - FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied - FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation - FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed - FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed - FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made - FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition - FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU - FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state - FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed - FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed - FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete - FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found - FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback - FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer - FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed - - /* Start of RTOS only error codes */ - FSP_ERR_INTERNAL = 100, ///< Internal error - FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted - - /* Start of UART specific */ - FSP_ERR_FRAMING = 200, ///< Framing error occurs - FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects - FSP_ERR_PARITY = 202, ///< Parity error occurs - FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow - FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue - FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer - FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer - - /* Start of SPI specific */ - FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. - FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. - FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. - FSP_ERR_SPI_PARITY = 303, ///< Parity error. - FSP_ERR_OVERRUN = 304, ///< Overrun error. - - /* Start of CGC Specific */ - FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. - FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. - FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off - FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off - FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled - FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set - FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active - FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit - FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled - FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out - FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode - - /* Start of FLASH Specific */ - FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. - FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state - FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz - FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory - FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed - - /* Start of CAC Specific */ - FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate - - /* Start of IIRFA Specific */ - FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. - - /* Start of GLCD Specific */ - FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock - FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter - FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter - FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found - FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter - FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer - FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register up2025-07-29 - FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry - FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting - FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter - - /* Start of JPEG Specific */ - FSP_ERR_JPEG_ERR = 1100, ///< JPEG error - FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. - FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. - FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. - FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. - FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. - FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. - FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. - FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. - FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. - FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) - FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. - FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. - FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. - FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. - FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough - FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU - - /* Start of touch panel framework specific */ - FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed - - /* Start of IIRFA specific */ - FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected - FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected - - /* Start of IP specific */ - FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device - FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device - FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device - - /* Start of USB specific */ - FSP_ERR_USB_FAILED = 1500, - FSP_ERR_USB_BUSY = 1501, - FSP_ERR_USB_SIZE_SHORT = 1502, - FSP_ERR_USB_SIZE_OVER = 1503, - FSP_ERR_USB_NOT_OPEN = 1504, - FSP_ERR_USB_NOT_SUSPEND = 1505, - FSP_ERR_USB_PARAMETER = 1506, - - /* Start of Message framework specific */ - FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool - FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool - FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid - FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid - FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many - FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found - FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue - FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue - FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal - FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released - - /* Start of 2DG Driver specific */ - FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization - FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering - FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering - - /* Start of ETHER Driver specific */ - FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. - FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation - FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled - FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty - FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable - FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication - FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. - - /* Start of ETHER_PHY Driver specific */ - FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. - FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation - - /* Start of BYTEQ library specific */ - FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data - FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue - - /* Start of CTSU Driver specific */ - FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. - FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. - FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. - FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. - FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. - FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. - FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. - FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. - FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. - FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. - FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. - FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. - FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. - FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. - FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. - FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. - FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. - - /* Start of SDMMC specific */ - FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. - FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. - FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. - FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. - FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. - FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. - FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. - - /* Start of FX_IO specific */ - FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. - FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. - - /* Start of CAN specific */ - FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. - FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. - FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. - FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. - FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. - FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. - FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. - FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. - - /* Start of SF_WIFI Specific */ - FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. - FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. - FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed - FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode - FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. - FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. - FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point - FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error - FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter - FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters - FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value - FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result - FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow - FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured - FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure - FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure - FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error - - /* Start of SF_CELLULAR Specific */ - FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. - FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. - FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed - FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is upto2025-07-29 - FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed - FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. - FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. - FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed - - /* Start of SF_BLE specific */ - FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed - FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed - FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed - FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled - FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled - - /* Start of SF_BLE_ABS specific */ - FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. - FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. - - /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ - FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function - FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy - FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty - FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index - FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry - FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed - FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened - FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized - FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred - FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter - FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented - FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified - FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred - FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid - FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state - FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened - FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. - FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher - FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed - FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input 2025-07-29 is illegal. - FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. - - /* Start of Crypto RSIP specific (0x10100) */ - FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy - FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return - FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error - FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal - FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed - - /* Start of SF_CRYPTO specific */ - FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened - FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error - FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key - FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold - FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. - FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. - FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. - - /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. - * Refer to sf_cryoto_err.h for Crypto error codes. - */ - - /* Start of Sensor specific */ - FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. - FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. - FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. - - /* Start of COMMS specific */ - FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. -} fsp_err_t; - -/** @} */ - -/*********************************************************************************************************************** - * Function prototypes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_features.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_features.h deleted file mode 100644 index dd54197d7..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_features.h +++ /dev/null @@ -1,297 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_FEATURES_H -#define FSP_FEATURES_H - -/*********************************************************************************************************************** - * Includes , "Project Includes" - **********************************************************************************************************************/ - -/* C99 includes. */ -#include -#include -#include -#include - -/* Different compiler support. */ -#include "fsp_common_api.h" -#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup BSP_MCU - * @{ - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Available modules. */ -typedef enum e_fsp_ip -{ - FSP_IP_CFLASH = 0, ///< Code Flash - FSP_IP_DFLASH = 1, ///< Data Flash - FSP_IP_RAM = 2, ///< RAM - FSP_IP_LVD = 3, ///< Low Voltage Detection - FSP_IP_CGC = 3, ///< Clock Generation Circuit - FSP_IP_LPM = 3, ///< Low Power Modes - FSP_IP_FCU = 4, ///< Flash Control Unit - FSP_IP_ICU = 6, ///< Interrupt Control Unit - FSP_IP_DMAC = 7, ///< DMA Controller - FSP_IP_DTC = 8, ///< Data Transfer Controller - FSP_IP_IOPORT = 9, ///< I/O Ports - FSP_IP_PFS = 10, ///< Pin Function Select - FSP_IP_ELC = 11, ///< Event Link Controller - FSP_IP_MPU = 13, ///< Memory Protection Unit - FSP_IP_MSTP = 14, ///< Module Stop - FSP_IP_MMF = 15, ///< Memory Mirror Function - FSP_IP_KEY = 16, ///< Key Interrupt Function - FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit - FSP_IP_DOC = 18, ///< Data Operation Circuit - FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator - FSP_IP_SCI = 20, ///< Serial Communications Interface - FSP_IP_IIC = 21, ///< I2C Bus Interface - FSP_IP_SPI = 22, ///< Serial Peripheral Interface - FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit - FSP_IP_SCE = 24, ///< Secure Cryptographic Engine - FSP_IP_SLCDC = 25, ///< Segment LCD Controller - FSP_IP_AES = 26, ///< Advanced Encryption Standard - FSP_IP_TRNG = 27, ///< True Random Number Generator - FSP_IP_FCACHE = 30, ///< Flash Cache - FSP_IP_SRAM = 31, ///< SRAM - FSP_IP_ADC = 32, ///< A/D Converter - FSP_IP_DAC = 33, ///< 12-Bit D/A Converter - FSP_IP_TSN = 34, ///< Temperature Sensor - FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit - FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator - FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator - FSP_IP_OPAMP = 38, ///< Operational Amplifier - FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter - FSP_IP_RTC = 40, ///< Real Time Clock - FSP_IP_WDT = 41, ///< Watch Dog Timer - FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer - FSP_IP_GPT = 43, ///< General PWM Timer - FSP_IP_POEG = 44, ///< Port Output Enable for GPT - FSP_IP_OPS = 45, ///< Output Phase Switch - FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer - FSP_IP_CAN = 48, ///< Controller Area Network - FSP_IP_IRDA = 49, ///< Infrared Data Association - FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface - FSP_IP_USBFS = 51, ///< USB Full Speed - FSP_IP_SDHI = 52, ///< SD/MMC Host Interface - FSP_IP_SRC = 53, ///< Sampling Rate Converter - FSP_IP_SSI = 54, ///< Serial Sound Interface - FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface - FSP_IP_ETHER = 64, ///< Ethernet MAC Controller - FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller - FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller - FSP_IP_PDC = 66, ///< Parallel Data Capture Unit - FSP_IP_GLCDC = 67, ///< Graphics LCD Controller - FSP_IP_DRW = 68, ///< 2D Drawing Engine - FSP_IP_JPEG = 69, ///< JPEG - FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter - FSP_IP_USBHS = 71, ///< USB High Speed - FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface - FSP_IP_CEC = 73, ///< HDMI CEC - FSP_IP_TFU = 74, ///< Trigonometric Function Unit - FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator - FSP_IP_CANFD = 76, ///< CAN-FD - FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT - FSP_IP_SAU = 78, ///< Serial Array Unit - FSP_IP_IICA = 79, ///< Serial Interface IICA - FSP_IP_UARTA = 80, ///< Serial Interface UARTA - FSP_IP_TAU = 81, ///< Timer Array Unit - FSP_IP_TML = 82, ///< 32-bit Interval Timer - FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator - FSP_IP_USBCC = 84, ///< USB Type-C Controller -} fsp_ip_t; - -/** Signals that can be mapped to an interrupt. */ -typedef enum e_fsp_signal -{ - FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH - FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH - FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END - FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B - FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A - FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B - FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ - FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ - FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A - FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B - FSP_SIGNAL_AGT_INT, ///< AGT INT - FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR - FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END - FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW - FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR - FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX - FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX - FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX - FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX - FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP - FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST - FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 - FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 - FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD - FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT - FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT - FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT - FSP_SIGNAL_CTSU_END = 0, ///< CTSU END - FSP_SIGNAL_CTSU_READ, ///< CTSU READ - FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE - FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI - FSP_SIGNAL_DALI_CLI, ///< DALI CLI - FSP_SIGNAL_DALI_SDI, ///< DALI SDI - FSP_SIGNAL_DALI_BPI, ///< DALI BPI - FSP_SIGNAL_DALI_FEI, ///< DALI FEI - FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI - FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT - FSP_SIGNAL_DOC_INT = 0, ///< DOC INT - FSP_SIGNAL_DRW_INT = 0, ///< DRW INT - FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE - FSP_SIGNAL_DTC_END, ///< DTC END - FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT - FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 - FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 - FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS - FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT - FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT - FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL - FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE - FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL - FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE - FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL - FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE - FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL - FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE - FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL - FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE - FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL - FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE - FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR - FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI - FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT - FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 - FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 - FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A - FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B - FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C - FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D - FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E - FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F - FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW - FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW - FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A - FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B - FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE - FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 - FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 - FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 - FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 - FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 - FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 - FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 - FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 - FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 - FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 - FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 - FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 - FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 - FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 - FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 - FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 - FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL - FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI - FSP_SIGNAL_IIC_RXI, ///< IIC RXI - FSP_SIGNAL_IIC_TEI, ///< IIC TEI - FSP_SIGNAL_IIC_TXI, ///< IIC TXI - FSP_SIGNAL_IIC_WUI, ///< IIC WUI - FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 - FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 - FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 - FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 - FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B - FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C - FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D - FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E - FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW - FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI - FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI - FSP_SIGNAL_KEY_INT = 0, ///< KEY INT - FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END - FSP_SIGNAL_PDC_INT, ///< PDC INT - FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY - FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT - FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT - FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM - FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD - FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY - FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY - FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY - FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG - FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY - FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 - FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 - FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK - FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY - FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 - FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 - FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 - FSP_SIGNAL_SCI_AM = 0, ///< SCI AM - FSP_SIGNAL_SCI_ERI, ///< SCI ERI - FSP_SIGNAL_SCI_RXI, ///< SCI RXI - FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI - FSP_SIGNAL_SCI_TEI, ///< SCI TEI - FSP_SIGNAL_SCI_TXI, ///< SCI TXI - FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI - FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND - FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND - FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS - FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD - FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ - FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO - FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI - FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE - FSP_SIGNAL_SPI_RXI, ///< SPI RXI - FSP_SIGNAL_SPI_TEI, ///< SPI TEI - FSP_SIGNAL_SPI_TXI, ///< SPI TXI - FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END - FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY - FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL - FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW - FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW - FSP_SIGNAL_SSI_INT = 0, ///< SSI INT - FSP_SIGNAL_SSI_RXI, ///< SSI RXI - FSP_SIGNAL_SSI_TXI, ///< SSI TXI - FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI - FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ - FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 - FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 - FSP_SIGNAL_USB_INT, ///< USB INT - FSP_SIGNAL_USB_RESUME, ///< USB RESUME - FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME - FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW - FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A - FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B - FSP_SIGNAL_ULPT_INT, ///< ULPT INT -} fsp_signal_t; - -typedef void (* fsp_vector_t)(void); - -/** @} (end addtogroup BSP_MCU) */ - -/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_version.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_version.h deleted file mode 100644 index 54b5c25ed..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/fsp_version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#ifndef FSP_VERSION_H - #define FSP_VERSION_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ - #include "bsp_api.h" - -/*******************************************************************************************************************//** - * @addtogroup RENESAS_COMMON - * @{ - **********************************************************************************************************************/ - - #ifdef __cplusplus -extern "C" { - #endif - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** FSP pack major version. */ - #define FSP_VERSION_MAJOR (5U) - -/** FSP pack minor version. */ - #define FSP_VERSION_MINOR (8U) - -/** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) - -/** FSP pack version build number (currently unused). */ - #define FSP_VERSION_BUILD (0U) - -/** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.8.0") - -/** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.8.0") - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** FSP Pack version structure */ -typedef union st_fsp_pack_version -{ - /** Version id */ - uint32_t version_id; - - /** - * Code version parameters, little endian order. - */ - struct version_id_b_s - { - uint8_t build; ///< Build version of FSP Pack - uint8_t patch; ///< Patch version of FSP Pack - uint8_t minor; ///< Minor version of FSP Pack - uint8_t major; ///< Major version of FSP Pack - } version_id_b; -} fsp_pack_version_t; - -/** @} */ - - #ifdef __cplusplus -} - #endif - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/instance/r_ioport.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/instance/r_ioport.h deleted file mode 100644 index 14abb229e..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/instance/r_ioport.h +++ /dev/null @@ -1,522 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @addtogroup IOPORT - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_H -#define R_IOPORT_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -#include "r_ioport_api.h" -#if __has_include("r_ioport_cfg.h") - #include "r_ioport_cfg.h" -#endif - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ -typedef struct st_ioport_instance_ctrl -{ - uint32_t open; - void const * p_context; -} ioport_instance_ctrl_t; - -/* This typedef is here temporarily. See SWFLEX-144 for details. */ -/** Superset list of all possible IO port pins. */ -typedef enum e_ioport_port_pin_t -{ - IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 - IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 - IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 - IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 - IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 - IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 - IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 - IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 - IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 - IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 - IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 - IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 - IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 - IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 - IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 - IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 - - IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 - IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 - IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 - IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 - IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 - IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 - IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 - IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 - IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 - IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 - IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 - IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 - IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 - IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 - IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 - IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 - - IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 - IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 - IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 - IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 - IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 - IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 - IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 - IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 - IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 - IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 - IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 - IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 - IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 - IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 - IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 - IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 - - IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 - IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 - IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 - IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 - IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 - IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 - IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 - IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 - IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 - IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 - IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 - IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 - IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 - IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 - IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 - IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 - - IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 - IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 - IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 - IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 - IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 - IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 - IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 - IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 - IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 - IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 - IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 - IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 - IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 - IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 - IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 - IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 - - IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 - IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 - IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 - IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 - IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 - IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 - IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 - IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 - IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 - IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 - IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 - IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 - IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 - IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 - IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 - IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 - - IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 - IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 - IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 - IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 - IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 - IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 - IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 - IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 - IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 - IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 - IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 - IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 - IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 - IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 - IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 - IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 - - IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 - IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 - IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 - IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 - IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 - IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 - IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 - IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 - IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 - IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 - IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 - IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 - IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 - IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 - IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 - IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 - - IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 - IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 - IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 - IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 - IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 - IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 - IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 - IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 - IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 - IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 - IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 - IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 - IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 - IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 - IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 - IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 - - IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 - IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 - IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 - IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 - IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 - IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 - IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 - IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 - IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 - IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 - IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 - IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 - IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 - IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 - IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 - IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 - - IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 - IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 - IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 - IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 - IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 - IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 - IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 - IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 - IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 - IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 - IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 - IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 - IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 - IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 - IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 - IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 - - IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 - IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 - IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 - IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 - IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 - IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 - IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 - IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 - IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 - IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 - IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 - IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 - IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 - IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 - IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 - IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 - - IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 - IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 - IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 - IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 - IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 - IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 - IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 - IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 - IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 - IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 - IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 - IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 - IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 - IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 - IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 - IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 - - IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 - IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 - IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 - IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 - IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 - IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 - IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 - IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 - IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 - IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 - IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 - IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 - IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 - IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 - IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 - IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 - - IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 - IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 - IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 - IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 - IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 - IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 - IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 - IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 - IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 - IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 - IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 - IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 - IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 - IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 - IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 - IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 -} ioport_port_pin_t; - -#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - #endif - - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an UARTA peripheral pin */ - IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; -#endif - -#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; -#endif - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const ioport_api_t g_ioport_on_ioport; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ - -fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); -fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); -fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); -fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); -fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); -fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); -fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); -fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t direction_values, - ioport_size_t mask); -fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); -fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, - bsp_io_port_t port, - ioport_size_t event_data, - ioport_size_t mask_value); -fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); -fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_IOPORT_H diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/periph/bsp_peripheral.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/periph/bsp_peripheral.h deleted file mode 100644 index bcaaf823c..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/periph/bsp_peripheral.h +++ /dev/null @@ -1,211 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * - * AUTOGENERATED FILE. DO NOT EDIT. - * - **********************************************************************************************************************/ - -#ifndef BSP_PERIPHERAL_H -#define BSP_PERIPHERAL_H - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -// *UNCRUSTIFY-OFF* - -#define BSP_PERIPHERAL_ACMP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) -#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) -#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_PRESENT (1) -#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ADC_B_PRESENT (0) -#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ADC_D_PRESENT (0) -#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AGT_PRESENT (1) -#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) -#define BSP_PERIPHERAL_AGTW_PRESENT (0) -#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_AMI_PRESENT (0) -#define BSP_PERIPHERAL_ANALOG_PRESENT (1) -#define BSP_PERIPHERAL_BUS_PRESENT (1) -#define BSP_PERIPHERAL_CAC_PRESENT (1) -#define BSP_PERIPHERAL_CACHE_PRESENT (1) -#define BSP_PERIPHERAL_CAN_PRESENT (0) -#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_CANFD_PRESENT (1) -#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_CEC_PRESENT (1) -#define BSP_PERIPHERAL_CEU_PRESENT (0) -#define BSP_PERIPHERAL_CGC_PRESENT (1) -#define BSP_PERIPHERAL_CPSCU_PRESENT (1) -#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) -#define BSP_PERIPHERAL_CRC_PRESENT (1) -#define BSP_PERIPHERAL_CTSU_PRESENT (1) -#define BSP_PERIPHERAL_DAC_PRESENT (1) -#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DAC_B_PRESENT (0) -#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC8_PRESENT (0) -#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_DAC12_PRESENT (1) -#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_DEBUG_PRESENT (1) -#define BSP_PERIPHERAL_DMA_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) -#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) -#define BSP_PERIPHERAL_DOC_PRESENT (1) -#define BSP_PERIPHERAL_DOC_B_PRESENT (0) -#define BSP_PERIPHERAL_DPHYCNT_PRESENT (0) -#define BSP_PERIPHERAL_DRW_PRESENT (0) -#define BSP_PERIPHERAL_DSILINK_PRESENT (0) -#define BSP_PERIPHERAL_DTC_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_PRESENT (1) -#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_ECCMB_PRESENT (1) -#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ELC_PRESENT (1) -#define BSP_PERIPHERAL_ELC_B_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) -#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) -#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_FACI_PRESENT (1) -#define BSP_PERIPHERAL_FCACHE_PRESENT (1) -#define BSP_PERIPHERAL_FLAD_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) -#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) -#define BSP_PERIPHERAL_GLCDC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_PRESENT (1) -#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) -#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) -#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) -#define BSP_PERIPHERAL_I3C_PRESENT (0) -#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ICU_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) -#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) -#define BSP_PERIPHERAL_IIC_PRESENT (1) -#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) -#define BSP_PERIPHERAL_IIC_B_PRESENT (0) -#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) -#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) -#define BSP_PERIPHERAL_IICA_PRESENT (0) -#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IIRFA_PRESENT (0) -#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_IPC_PRESENT (0) -#define BSP_PERIPHERAL_IRDA_PRESENT (0) -#define BSP_PERIPHERAL_IRTC_PRESENT (0) -#define BSP_PERIPHERAL_IWDT_PRESENT (1) -#define BSP_PERIPHERAL_JPEG_PRESENT (0) -#define BSP_PERIPHERAL_KINT_PRESENT (0) -#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_MACL_PRESENT (0) -#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) -#define BSP_PERIPHERAL_MMF_PRESENT (0) -#define BSP_PERIPHERAL_MPU_PRESENT (1) -#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_MRMS_PRESENT (0) -#define BSP_PERIPHERAL_MRRGE_PRESENT (0) -#define BSP_PERIPHERAL_MSTP_PRESENT (1) -#define BSP_PERIPHERAL_OCD_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_PRESENT (0) -#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_OSPI_PRESENT (1) -#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) -#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) -#define BSP_PERIPHERAL_PDC_PRESENT (0) -#define BSP_PERIPHERAL_PFS_PRESENT (1) -#define BSP_PERIPHERAL_PFS_B_PRESENT (0) -#define BSP_PERIPHERAL_PMISC_PRESENT (0) -#define BSP_PERIPHERAL_PORGA_PRESENT (0) -#define BSP_PERIPHERAL_PORT_PRESENT (1) -#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) -#define BSP_PERIPHERAL_PSCU_PRESENT (1) -#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) -#define BSP_PERIPHERAL_QSPI_PRESENT (1) -#define BSP_PERIPHERAL_RADIO_PRESENT (0) -#define BSP_PERIPHERAL_RSIP_PRESENT (1) -#define BSP_PERIPHERAL_RTC_PRESENT (1) -#define BSP_PERIPHERAL_RTC_C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_PRESENT (0) -#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) -#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) -#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) -#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SCI_PRESENT (1) -#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) -#define BSP_PERIPHERAL_SCI_B_PRESENT (0) -#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) -#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SDHI_PRESENT (1) -#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SLCDC_PRESENT (0) -#define BSP_PERIPHERAL_SPI_PRESENT (1) -#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) -#define BSP_PERIPHERAL_SPI_B_PRESENT (0) -#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_SPMON_PRESENT (0) -#define BSP_PERIPHERAL_SRAM_PRESENT (1) -#define BSP_PERIPHERAL_SRC_PRESENT (0) -#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) -#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_PRESENT (1) -#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) -#define BSP_PERIPHERAL_TAU_PRESENT (0) -#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TFU_PRESENT (0) -#define BSP_PERIPHERAL_TML_PRESENT (0) -#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_TRNG_PRESENT (0) -#define BSP_PERIPHERAL_TSD_PRESENT (1) -#define BSP_PERIPHERAL_TSN_PRESENT (1) -#define BSP_PERIPHERAL_TZF_PRESENT (1) -#define BSP_PERIPHERAL_UARTA_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) -#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_ULPT_PRESENT (0) -#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) -#define BSP_PERIPHERAL_USB_PRESENT (1) -#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) -#define BSP_PERIPHERAL_USB_FS_PRESENT (1) -#define BSP_PERIPHERAL_USB_HS_PRESENT (1) -#define BSP_PERIPHERAL_USBCC_PRESENT (0) -#define BSP_PERIPHERAL_WDT_PRESENT (1) -#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) - -// *UNCRUSTIFY-ON* - -#endif diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_api.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_api.h deleted file mode 100644 index dcb104b06..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_api.h +++ /dev/null @@ -1,192 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_SYSTEM_INTERFACES - * @defgroup IOPORT_API I/O Port Interface - * @brief Interface for accessing I/O ports and configuring I/O functionality. - * - * @section IOPORT_API_SUMMARY Summary - * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. - * Port and pin direction can be changed. - * - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_IOPORT_API_H -#define R_IOPORT_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common error codes and definitions. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ -#ifndef BSP_OVERRIDE_IOPORT_SIZE_T - -/** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size -#endif - -/** Pin identifier and pin configuration value */ -typedef struct st_ioport_pin_cfg -{ - uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure - bsp_io_port_pin_t pin; ///< Pin identifier -} ioport_pin_cfg_t; - -/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ -typedef struct st_ioport_cfg -{ - uint16_t number_of_pins; ///< Number of pins for which there is configuration data - ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data - const void * p_extend; ///< Pointer to hardware extend configuration -} ioport_cfg_t; - -/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - */ -typedef void ioport_ctrl_t; - -/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ -typedef struct st_ioport_api -{ - /** Initialize internal driver data and initial pin configurations. Called during startup. Do - * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of - * multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Close the API. - * - * @param[in] p_ctrl Pointer to control structure. - **/ - fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); - - /** Configure multiple pins. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration data array. - */ - fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); - - /** Configure settings for an individual pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] cfg Configuration options for the pin. - */ - fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); - - /** Read the event input data of the specified pin and return the level. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_event Pointer to return the event data. - */ - fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); - - /** Write pin event data. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin event data is to be written to. - * @param[in] pin_value Level to be written to pin output event. - */ - fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); - - /** Read level of a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be read. - * @param[in] p_pin_value Pointer to return the pin level. - */ - fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); - - /** Write specified level to a pin. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] pin Pin to be written to. - * @param[in] level State to be written to the pin. - */ - fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); - - /** Set the direction of one or more pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port. - * @param[in] mask Mask controlling which pins on the port are to be configured. - */ - fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, - ioport_size_t mask); - - /** Read captured event data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_event_data Pointer to return the event data. - */ - fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); - - /** Write event output data for a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port event data will be written to. - * @param[in] event_data Data to be written as event data to specified port. - * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. - * being written to port. - */ - fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, - ioport_size_t mask_value); - - /** Read states of pins on the specified port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be read. - * @param[in] p_port_value Pointer to return the port value. - */ - fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); - - /** Write to multiple pins on a port. - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] port Port to be written to. - * @param[in] value Value to be written to the port. - * @param[in] mask Mask controlling which pins on the port are written to. - */ - fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); -} ioport_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_ioport_instance -{ - ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - ioport_api_t const * p_api; ///< Pointer to the API structure for this instance -} ioport_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end defgroup IOPORT_API) - **********************************************************************************************************************/ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_cfg.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_cfg.h deleted file mode 100644 index d2688bf5b..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/r_ioport_cfg.h +++ /dev/null @@ -1,13 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#ifdef __cplusplus -} -#endif -#endif /* R_IOPORT_CFG_H_ */ diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/renesas.h b/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/renesas.h deleted file mode 100644 index 41098a054..000000000 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/thirdparty/ra6m5bh/renesas.h +++ /dev/null @@ -1,154 +0,0 @@ -/* -* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/* Ensure Renesas MCU variation definitions are included to ensure MCU - * specific register variations are handled correctly. */ -#ifndef BSP_FEATURE_H - #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." -#endif - -/** @addtogroup Renesas - * @{ - */ - -/** @addtogroup RA - * @{ - */ - -#ifndef RA_H - #define RA_H - - #ifdef __cplusplus -extern "C" { - #endif - - #include "cmsis_compiler.h" - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - - #if BSP_MCU_GROUP_RA0E1 - #include "R7FA0E107.h" - #elif BSP_MCU_GROUP_RA2A1 - #include "R7FA2A1AB.h" - #elif BSP_MCU_GROUP_RA2A2 - #include "R7FA2A2AD.h" - #elif BSP_MCU_GROUP_RA2E1 - #include "R7FA2E1A9.h" - #elif BSP_MCU_GROUP_RA2E2 - #include "R7FA2E2A7.h" - #elif BSP_MCU_GROUP_RA2E3 - #include "R7FA2E307.h" - #elif BSP_MCU_GROUP_RA2L1 - #include "R7FA2L1AB.h" - #elif BSP_MCU_GROUP_RA4E1 - #include "R7FA4E10D.h" - #elif BSP_MCU_GROUP_RA4E2 - #include "R7FA4E2B9.h" - #elif BSP_MCU_GROUP_RA4M1 - #include "R7FA4M1AB.h" - #elif BSP_MCU_GROUP_RA4M2 - #include "R7FA4M2AD.h" - #elif BSP_MCU_GROUP_RA4M3 - #include "R7FA4M3AF.h" - #elif BSP_MCU_GROUP_RA4T1 - #include "R7FA4T1BB.h" - #elif BSP_MCU_GROUP_RA4W1 - #include "R7FA4W1AD.h" - #elif BSP_MCU_GROUP_RA4L1 - #include "R7FA4L1BD.h" - #elif BSP_MCU_GROUP_RA6E1 - #include "R7FA6E10F.h" - #elif BSP_MCU_GROUP_RA6E2 - #include "R7FA6E2BB.h" - #elif BSP_MCU_GROUP_RA6M1 - #include "R7FA6M1AD.h" - #elif BSP_MCU_GROUP_RA6M2 - #include "R7FA6M2AF.h" - #elif BSP_MCU_GROUP_RA6M3 - #include "R7FA6M3AH.h" - #elif BSP_MCU_GROUP_RA6M4 - #include "R7FA6M4AF.h" - #elif BSP_MCU_GROUP_RA6M5 - #include "R7FA6M5BH.h" - #elif BSP_MCU_GROUP_RA6T1 - #include "R7FA6T1AD.h" - #elif BSP_MCU_GROUP_RA6T2 - #include "R7FA6T2BD.h" - #elif BSP_MCU_GROUP_RA6T3 - #include "R7FA6T3BB.h" - #elif BSP_MCU_GROUP_RA8M1 - #include "R7FA8M1AH.h" - #elif BSP_MCU_GROUP_RA8D1 - #include "R7FA8D1BH.h" - #elif BSP_MCU_GROUP_RA8T1 - #include "R7FA8T1AH.h" - #elif BSP_MCU_GROUP_RA8E1 - #include "R7FA8E1AF.h" - #else - #if __has_include("renesas_internal.h") - #include "renesas_internal.h" - #else - #warning "Unsupported MCU" - #endif - #endif - -/* - * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB - * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 - * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: - * - * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | - * |-----------|------------|------------------------| - * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | - * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | - * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | - * - * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ - * - * IAR is currently the only toolchain producing the correct __ARM_ARCH value. - * - *- See https://github.com/ARM-software/CMSIS_6/issues/159 - */ - #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 - #undef __ARM_ARCH - #define __ARM_ARCH 801 - #endif - - #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M4 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) - #define RENESAS_CORTEX_M23 - #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M33 - #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) - #define RENESAS_CORTEX_M85 - #else - #warning Unsupported Architecture - #endif - - #ifdef __cplusplus -} - #endif - -#endif /* RA_H */ - -/** @} */ /* End of group RA */ - -/** @} */ /* End of group Renesas */ From aa55671ff67d866b77ffb85c7d3f76c300c3db4c Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 8 Oct 2025 12:59:49 +0200 Subject: [PATCH 5/8] Finished system library for RA6M5 MCUs --- .../system/src/renesas/ra6m5ag/init_clock.c | 778 +++++++++++++++++- .../system/src/renesas/ra6m5ah/init_clock.c | 778 +++++++++++++++++- .../system/src/renesas/ra6m5bf/init_clock.c | 778 +++++++++++++++++- .../system/src/renesas/ra6m5bg/init_clock.c | 778 +++++++++++++++++- .../system/src/renesas/ra6m5bh/init_clock.c | 778 +++++++++++++++++- 5 files changed, 3885 insertions(+), 5 deletions(-) diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c index d919219af..912765272 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c @@ -42,7 +42,783 @@ #include "core_header.h" #include "mcu.h" +extern void * __Vectors[]; + +typedef struct +{ + uint32_t ICLK_Frequency; // System clock frequency in Hz + uint32_t PCLKA_Frequency; // PCLKA clock frequency in Hz + uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz + uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz + uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz +} SYSTEM_ClocksTypeDef; + +static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) + +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) + +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#define BSP_IO_PWPR_PFSWE_OFFSET (6) + +// ----------------------------------------------------------------------------------------- + +/*********************************************************************** + * ID Code Configuration for On-Chip Flash Protection + * This section places the user-defined 128-bit ID code into a special + * memory section. These values can be used to lock/unlock the flash. + * + * If BSP_FEATURE_BSP_OSIS_PADDING is enabled, each 32-bit word is + * followed by 0xFFFFFFFF as padding. + ***********************************************************************/ + +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) +#define BSP_DONT_REMOVE __attribute__((used)) + +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" + +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE 1 +#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1 +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +/** ID code values (4 x 32-bit, optionally padded) */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION(BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 1 + #endif + + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 2 + #endif + + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 3 + #endif + + BSP_CFG_ID_CODE_LONG_4 +}; + +#endif // BSP_FEATURE_FLASH_SUPPORTS_ID_CODE + +/*********************************************************************** + * Option Function Select (OFS) Settings + ***********************************************************************/ +#define OFS_SEQ1 (0xA001A001 | (1 << 1) | (3 << 2)) +#define OFS_SEQ2 ((15 << 4) | (3 << 8) | (3 << 10)) +#define OFS_SEQ3 ((1 << 12) | (1 << 14) | (1 << 17)) +#define OFS_SEQ4 ((3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)) +#define OFS_SEQ5 ((1 << 28) | (1 << 30)) + +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/*********************************************************************** + * OFS1 Configuration - HOCO Frequency and other boot options + ***********************************************************************/ +#define HOCO_ENABLE (VALUE_SYSTEM_HOCOCR & 0x1) +#define HOCO_FREQ (VALUE_SYSTEM_HOCOCR2 & 0x3) + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) // TODO HOCO options +#define BSP_CFG_HOCO_FREQUENCY (HOCO_FREQ) // TODO HOCO options +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) + +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/*********************************************************************** + * MPU Configuration + ***********************************************************************/ +#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) + +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) + +/* MPU Control Register value based on the configuration above */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE << 0) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*********************************************************************** + * ROM Register Table (stored in a dedicated memory section) + ***********************************************************************/ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION(BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, // OFS0 register value + (uint32_t) BSP_ROM_REG_OFS1_SETTING, // OFS1 register value (with HOCO frequency) + +#if __MPU_PRESENT + // PC0 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + + // PC1 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + + // MPU Region 0 + ((uint32_t)(BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU)), + ((uint32_t)((BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U)), + + // MPU Region 1 + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + + // MPU Region 2 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Region 3 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Control Register + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +#endif +}; +// ----------------------------------------------------------------------------------------- + +/** + * @brief Sets the system clock based on user preferences. + * + * Configures the system clock source, frequency and dividers according to + * preferences stored internally by the library. This function is called during + * system initialization and is not intended for direct use by application code. + * + * @return None + * + * @note This function is `static` and only available within this source file. + */ +static void system_clock_configuration(); + +// ----------------------------------------------------------------------------------------- + +/** + * @brief Gets the system clock values. + * + * Calculates configured clock frequency for system clocks which are used by different + * MCU modules. + * + * @return None + */ +void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { + uint32_t prescaler, source_clock; + + // Get the frequency of main clock. + SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; + + // Get the source frequency for all clocks. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000000 ) >> 24 ]; + source_clock = SYSTEM_Clocks->ICLK_Frequency * prescaler; + + // Get PCLKA clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->PCLKA_Frequency = source_clock / prescaler; + + // Get PCLKB clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x700 ) >> 8 ]; + SYSTEM_Clocks->PCLKB_Frequency = source_clock / prescaler; + + // Get PCLKC clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x70 ) >> 4 ]; + SYSTEM_Clocks->PCLKC_Frequency = source_clock / prescaler; + + // Get PCLKD clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7 ) ]; + SYSTEM_Clocks->PCLKD_Frequency = source_clock / prescaler; + + // Get FCLK clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; +} + +/** + * @brief Initializes the microcontroller system. + * + * Performs essential setup, including clock configuration and core-level + * initialization. This function should be called once at startup before + * using any other peripherals or system services. + * + * @return None + */ void SystemInit(void) { + // Set-up FPU settings + SCB->CPACR |= ((3UL << (10*2)) | (3UL << (11*2))); + SCB->VTOR = (uint32_t) &__Vectors; + + // Lock VBTCR1 register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + + // BSP clock init start + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + // Flash cache disable + R_FCACHE->FCACHEE = 0U; + + // Clock setting + system_clock_configuration(); + + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + // Enable flash cache + R_FCACHE->FCACHEE = 1U; + + // Disable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 0; + + // Setup NMI interrupt + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + // Setup start address + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + // Setup end address + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. + * NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + // Enable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 1U; + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + + // Pin config + R_PMISC->PWPR = 0; // Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; // Set PFSWE bit - writing to PFS register enabled + + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } + } +} + +// ----------------------------------------------------------------------------------------- + +static void system_clock_configuration() { + // Unlock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + + // Disable cache before modifying SOPCCR or OPCCR + R_FCACHE->FCACHEE = 0U; + + R_SYSTEM->OPCCR = VALUE_SYSTEM_OPCCR; + + if ( !( VALUE_SYSTEM_MOSCCR & R_SYSTEM_MOSCCR_MOSTP_Msk ) ) { + // Main oscillator selected + R_SYSTEM->MOSCCR_b.MOSTP = 1; // Stop XTAL + R_SYSTEM->MOMCR = VALUE_SYSTEM_MOMCR; + R_SYSTEM->MOSCWTCR = VALUE_SYSTEM_MOSCWTCR; + R_SYSTEM->MOSCCR_b.MOSTP = 0; // Start XTAL + uint8_t check = R_SYSTEM->MOSCCR; // Read MOSTP + + while ( !( R_SYSTEM->OSCSF_b.MOSCSF ) ) { + // Wait for XTAL to stabilize + } + } + + if ( !( VALUE_SYSTEM_SOSCCR & R_SYSTEM_SOSCCR_SOSTP_Msk ) ) { + R_SYSTEM->SOSCCR_b.SOSTP = 1; // Stop SOSC + R_SYSTEM->SOMCR = VALUE_SYSTEM_SOMCR; + R_SYSTEM->SOSCCR_b.SOSTP = 0; // Start SOSC + } + + if ( !( VALUE_SYSTEM_HOCOCR & R_SYSTEM_HOCOCR_HCSTP_Msk ) ) { + if( 0x2 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 20MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x263; + } else if ( 0x1 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 18MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x226; + } else if ( 0x0 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 16MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x1E9; + } + + R_SYSTEM->FLLCR1_b.FLLEN = 0x1; + + R_SYSTEM->HOCOCR2 = VALUE_SYSTEM_HOCOCR2; + R_SYSTEM->HOCOWTCR = VALUE_SYSTEM_HOCOWTCR; + R_SYSTEM->HOCOCR_b.HCSTP = 0; // Start HOCO + + while ( !( R_SYSTEM->OSCSF_b.HOCOSF ) ) { + // Wait for HOCO to stabilize + } + } + + if ( !( VALUE_SYSTEM_PLLCR & R_SYSTEM_PLLCR_PLLSTP_Msk ) ) { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + R_SYSTEM->PLLCCR = VALUE_SYSTEM_PLLCCR; + R_SYSTEM->PLLCR_b.PLLSTP = 0; // PLL is operating + + while ( !( R_SYSTEM->OSCSF_b.PLLSF ) ) { + // Wait for PLL to stabilize + } + } else { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + } + + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; + + R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; + + Delay_1ms(); + + R_SYSTEM->SCKSCR = VALUE_SYSTEM_SCKSCR; + + Delay_1ms(); + + if ( 150000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 3; // 3 waits + } else if ( 100000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 2; // 2 waits + } else if ( 50000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 1; // 1 wait + } else { + R_FCACHE->FLWT = 0; // 0 waits + } + + R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { + R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); + R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out + } -} \ No newline at end of file + // Lock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +} diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c index d919219af..912765272 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c @@ -42,7 +42,783 @@ #include "core_header.h" #include "mcu.h" +extern void * __Vectors[]; + +typedef struct +{ + uint32_t ICLK_Frequency; // System clock frequency in Hz + uint32_t PCLKA_Frequency; // PCLKA clock frequency in Hz + uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz + uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz + uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz +} SYSTEM_ClocksTypeDef; + +static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) + +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) + +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#define BSP_IO_PWPR_PFSWE_OFFSET (6) + +// ----------------------------------------------------------------------------------------- + +/*********************************************************************** + * ID Code Configuration for On-Chip Flash Protection + * This section places the user-defined 128-bit ID code into a special + * memory section. These values can be used to lock/unlock the flash. + * + * If BSP_FEATURE_BSP_OSIS_PADDING is enabled, each 32-bit word is + * followed by 0xFFFFFFFF as padding. + ***********************************************************************/ + +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) +#define BSP_DONT_REMOVE __attribute__((used)) + +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" + +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE 1 +#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1 +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +/** ID code values (4 x 32-bit, optionally padded) */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION(BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 1 + #endif + + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 2 + #endif + + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 3 + #endif + + BSP_CFG_ID_CODE_LONG_4 +}; + +#endif // BSP_FEATURE_FLASH_SUPPORTS_ID_CODE + +/*********************************************************************** + * Option Function Select (OFS) Settings + ***********************************************************************/ +#define OFS_SEQ1 (0xA001A001 | (1 << 1) | (3 << 2)) +#define OFS_SEQ2 ((15 << 4) | (3 << 8) | (3 << 10)) +#define OFS_SEQ3 ((1 << 12) | (1 << 14) | (1 << 17)) +#define OFS_SEQ4 ((3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)) +#define OFS_SEQ5 ((1 << 28) | (1 << 30)) + +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/*********************************************************************** + * OFS1 Configuration - HOCO Frequency and other boot options + ***********************************************************************/ +#define HOCO_ENABLE (VALUE_SYSTEM_HOCOCR & 0x1) +#define HOCO_FREQ (VALUE_SYSTEM_HOCOCR2 & 0x3) + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) // TODO HOCO options +#define BSP_CFG_HOCO_FREQUENCY (HOCO_FREQ) // TODO HOCO options +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) + +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/*********************************************************************** + * MPU Configuration + ***********************************************************************/ +#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) + +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) + +/* MPU Control Register value based on the configuration above */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE << 0) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*********************************************************************** + * ROM Register Table (stored in a dedicated memory section) + ***********************************************************************/ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION(BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, // OFS0 register value + (uint32_t) BSP_ROM_REG_OFS1_SETTING, // OFS1 register value (with HOCO frequency) + +#if __MPU_PRESENT + // PC0 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + + // PC1 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + + // MPU Region 0 + ((uint32_t)(BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU)), + ((uint32_t)((BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U)), + + // MPU Region 1 + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + + // MPU Region 2 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Region 3 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Control Register + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +#endif +}; +// ----------------------------------------------------------------------------------------- + +/** + * @brief Sets the system clock based on user preferences. + * + * Configures the system clock source, frequency and dividers according to + * preferences stored internally by the library. This function is called during + * system initialization and is not intended for direct use by application code. + * + * @return None + * + * @note This function is `static` and only available within this source file. + */ +static void system_clock_configuration(); + +// ----------------------------------------------------------------------------------------- + +/** + * @brief Gets the system clock values. + * + * Calculates configured clock frequency for system clocks which are used by different + * MCU modules. + * + * @return None + */ +void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { + uint32_t prescaler, source_clock; + + // Get the frequency of main clock. + SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; + + // Get the source frequency for all clocks. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000000 ) >> 24 ]; + source_clock = SYSTEM_Clocks->ICLK_Frequency * prescaler; + + // Get PCLKA clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->PCLKA_Frequency = source_clock / prescaler; + + // Get PCLKB clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x700 ) >> 8 ]; + SYSTEM_Clocks->PCLKB_Frequency = source_clock / prescaler; + + // Get PCLKC clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x70 ) >> 4 ]; + SYSTEM_Clocks->PCLKC_Frequency = source_clock / prescaler; + + // Get PCLKD clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7 ) ]; + SYSTEM_Clocks->PCLKD_Frequency = source_clock / prescaler; + + // Get FCLK clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; +} + +/** + * @brief Initializes the microcontroller system. + * + * Performs essential setup, including clock configuration and core-level + * initialization. This function should be called once at startup before + * using any other peripherals or system services. + * + * @return None + */ void SystemInit(void) { + // Set-up FPU settings + SCB->CPACR |= ((3UL << (10*2)) | (3UL << (11*2))); + SCB->VTOR = (uint32_t) &__Vectors; + + // Lock VBTCR1 register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + + // BSP clock init start + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + // Flash cache disable + R_FCACHE->FCACHEE = 0U; + + // Clock setting + system_clock_configuration(); + + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + // Enable flash cache + R_FCACHE->FCACHEE = 1U; + + // Disable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 0; + + // Setup NMI interrupt + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + // Setup start address + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + // Setup end address + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. + * NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + // Enable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 1U; + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + + // Pin config + R_PMISC->PWPR = 0; // Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; // Set PFSWE bit - writing to PFS register enabled + + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } + } +} + +// ----------------------------------------------------------------------------------------- + +static void system_clock_configuration() { + // Unlock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + + // Disable cache before modifying SOPCCR or OPCCR + R_FCACHE->FCACHEE = 0U; + + R_SYSTEM->OPCCR = VALUE_SYSTEM_OPCCR; + + if ( !( VALUE_SYSTEM_MOSCCR & R_SYSTEM_MOSCCR_MOSTP_Msk ) ) { + // Main oscillator selected + R_SYSTEM->MOSCCR_b.MOSTP = 1; // Stop XTAL + R_SYSTEM->MOMCR = VALUE_SYSTEM_MOMCR; + R_SYSTEM->MOSCWTCR = VALUE_SYSTEM_MOSCWTCR; + R_SYSTEM->MOSCCR_b.MOSTP = 0; // Start XTAL + uint8_t check = R_SYSTEM->MOSCCR; // Read MOSTP + + while ( !( R_SYSTEM->OSCSF_b.MOSCSF ) ) { + // Wait for XTAL to stabilize + } + } + + if ( !( VALUE_SYSTEM_SOSCCR & R_SYSTEM_SOSCCR_SOSTP_Msk ) ) { + R_SYSTEM->SOSCCR_b.SOSTP = 1; // Stop SOSC + R_SYSTEM->SOMCR = VALUE_SYSTEM_SOMCR; + R_SYSTEM->SOSCCR_b.SOSTP = 0; // Start SOSC + } + + if ( !( VALUE_SYSTEM_HOCOCR & R_SYSTEM_HOCOCR_HCSTP_Msk ) ) { + if( 0x2 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 20MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x263; + } else if ( 0x1 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 18MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x226; + } else if ( 0x0 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 16MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x1E9; + } + + R_SYSTEM->FLLCR1_b.FLLEN = 0x1; + + R_SYSTEM->HOCOCR2 = VALUE_SYSTEM_HOCOCR2; + R_SYSTEM->HOCOWTCR = VALUE_SYSTEM_HOCOWTCR; + R_SYSTEM->HOCOCR_b.HCSTP = 0; // Start HOCO + + while ( !( R_SYSTEM->OSCSF_b.HOCOSF ) ) { + // Wait for HOCO to stabilize + } + } + + if ( !( VALUE_SYSTEM_PLLCR & R_SYSTEM_PLLCR_PLLSTP_Msk ) ) { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + R_SYSTEM->PLLCCR = VALUE_SYSTEM_PLLCCR; + R_SYSTEM->PLLCR_b.PLLSTP = 0; // PLL is operating + + while ( !( R_SYSTEM->OSCSF_b.PLLSF ) ) { + // Wait for PLL to stabilize + } + } else { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + } + + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; + + R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; + + Delay_1ms(); + + R_SYSTEM->SCKSCR = VALUE_SYSTEM_SCKSCR; + + Delay_1ms(); + + if ( 150000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 3; // 3 waits + } else if ( 100000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 2; // 2 waits + } else if ( 50000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 1; // 1 wait + } else { + R_FCACHE->FLWT = 0; // 0 waits + } + + R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { + R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); + R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out + } -} \ No newline at end of file + // Lock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +} diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c index d919219af..912765272 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c @@ -42,7 +42,783 @@ #include "core_header.h" #include "mcu.h" +extern void * __Vectors[]; + +typedef struct +{ + uint32_t ICLK_Frequency; // System clock frequency in Hz + uint32_t PCLKA_Frequency; // PCLKA clock frequency in Hz + uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz + uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz + uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz +} SYSTEM_ClocksTypeDef; + +static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) + +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) + +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#define BSP_IO_PWPR_PFSWE_OFFSET (6) + +// ----------------------------------------------------------------------------------------- + +/*********************************************************************** + * ID Code Configuration for On-Chip Flash Protection + * This section places the user-defined 128-bit ID code into a special + * memory section. These values can be used to lock/unlock the flash. + * + * If BSP_FEATURE_BSP_OSIS_PADDING is enabled, each 32-bit word is + * followed by 0xFFFFFFFF as padding. + ***********************************************************************/ + +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) +#define BSP_DONT_REMOVE __attribute__((used)) + +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" + +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE 1 +#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1 +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +/** ID code values (4 x 32-bit, optionally padded) */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION(BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 1 + #endif + + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 2 + #endif + + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 3 + #endif + + BSP_CFG_ID_CODE_LONG_4 +}; + +#endif // BSP_FEATURE_FLASH_SUPPORTS_ID_CODE + +/*********************************************************************** + * Option Function Select (OFS) Settings + ***********************************************************************/ +#define OFS_SEQ1 (0xA001A001 | (1 << 1) | (3 << 2)) +#define OFS_SEQ2 ((15 << 4) | (3 << 8) | (3 << 10)) +#define OFS_SEQ3 ((1 << 12) | (1 << 14) | (1 << 17)) +#define OFS_SEQ4 ((3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)) +#define OFS_SEQ5 ((1 << 28) | (1 << 30)) + +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/*********************************************************************** + * OFS1 Configuration - HOCO Frequency and other boot options + ***********************************************************************/ +#define HOCO_ENABLE (VALUE_SYSTEM_HOCOCR & 0x1) +#define HOCO_FREQ (VALUE_SYSTEM_HOCOCR2 & 0x3) + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) // TODO HOCO options +#define BSP_CFG_HOCO_FREQUENCY (HOCO_FREQ) // TODO HOCO options +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) + +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/*********************************************************************** + * MPU Configuration + ***********************************************************************/ +#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) + +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) + +/* MPU Control Register value based on the configuration above */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE << 0) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*********************************************************************** + * ROM Register Table (stored in a dedicated memory section) + ***********************************************************************/ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION(BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, // OFS0 register value + (uint32_t) BSP_ROM_REG_OFS1_SETTING, // OFS1 register value (with HOCO frequency) + +#if __MPU_PRESENT + // PC0 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + + // PC1 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + + // MPU Region 0 + ((uint32_t)(BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU)), + ((uint32_t)((BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U)), + + // MPU Region 1 + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + + // MPU Region 2 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Region 3 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Control Register + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +#endif +}; +// ----------------------------------------------------------------------------------------- + +/** + * @brief Sets the system clock based on user preferences. + * + * Configures the system clock source, frequency and dividers according to + * preferences stored internally by the library. This function is called during + * system initialization and is not intended for direct use by application code. + * + * @return None + * + * @note This function is `static` and only available within this source file. + */ +static void system_clock_configuration(); + +// ----------------------------------------------------------------------------------------- + +/** + * @brief Gets the system clock values. + * + * Calculates configured clock frequency for system clocks which are used by different + * MCU modules. + * + * @return None + */ +void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { + uint32_t prescaler, source_clock; + + // Get the frequency of main clock. + SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; + + // Get the source frequency for all clocks. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000000 ) >> 24 ]; + source_clock = SYSTEM_Clocks->ICLK_Frequency * prescaler; + + // Get PCLKA clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->PCLKA_Frequency = source_clock / prescaler; + + // Get PCLKB clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x700 ) >> 8 ]; + SYSTEM_Clocks->PCLKB_Frequency = source_clock / prescaler; + + // Get PCLKC clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x70 ) >> 4 ]; + SYSTEM_Clocks->PCLKC_Frequency = source_clock / prescaler; + + // Get PCLKD clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7 ) ]; + SYSTEM_Clocks->PCLKD_Frequency = source_clock / prescaler; + + // Get FCLK clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; +} + +/** + * @brief Initializes the microcontroller system. + * + * Performs essential setup, including clock configuration and core-level + * initialization. This function should be called once at startup before + * using any other peripherals or system services. + * + * @return None + */ void SystemInit(void) { + // Set-up FPU settings + SCB->CPACR |= ((3UL << (10*2)) | (3UL << (11*2))); + SCB->VTOR = (uint32_t) &__Vectors; + + // Lock VBTCR1 register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + + // BSP clock init start + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + // Flash cache disable + R_FCACHE->FCACHEE = 0U; + + // Clock setting + system_clock_configuration(); + + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + // Enable flash cache + R_FCACHE->FCACHEE = 1U; + + // Disable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 0; + + // Setup NMI interrupt + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + // Setup start address + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + // Setup end address + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. + * NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + // Enable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 1U; + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + + // Pin config + R_PMISC->PWPR = 0; // Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; // Set PFSWE bit - writing to PFS register enabled + + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } + } +} + +// ----------------------------------------------------------------------------------------- + +static void system_clock_configuration() { + // Unlock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + + // Disable cache before modifying SOPCCR or OPCCR + R_FCACHE->FCACHEE = 0U; + + R_SYSTEM->OPCCR = VALUE_SYSTEM_OPCCR; + + if ( !( VALUE_SYSTEM_MOSCCR & R_SYSTEM_MOSCCR_MOSTP_Msk ) ) { + // Main oscillator selected + R_SYSTEM->MOSCCR_b.MOSTP = 1; // Stop XTAL + R_SYSTEM->MOMCR = VALUE_SYSTEM_MOMCR; + R_SYSTEM->MOSCWTCR = VALUE_SYSTEM_MOSCWTCR; + R_SYSTEM->MOSCCR_b.MOSTP = 0; // Start XTAL + uint8_t check = R_SYSTEM->MOSCCR; // Read MOSTP + + while ( !( R_SYSTEM->OSCSF_b.MOSCSF ) ) { + // Wait for XTAL to stabilize + } + } + + if ( !( VALUE_SYSTEM_SOSCCR & R_SYSTEM_SOSCCR_SOSTP_Msk ) ) { + R_SYSTEM->SOSCCR_b.SOSTP = 1; // Stop SOSC + R_SYSTEM->SOMCR = VALUE_SYSTEM_SOMCR; + R_SYSTEM->SOSCCR_b.SOSTP = 0; // Start SOSC + } + + if ( !( VALUE_SYSTEM_HOCOCR & R_SYSTEM_HOCOCR_HCSTP_Msk ) ) { + if( 0x2 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 20MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x263; + } else if ( 0x1 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 18MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x226; + } else if ( 0x0 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 16MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x1E9; + } + + R_SYSTEM->FLLCR1_b.FLLEN = 0x1; + + R_SYSTEM->HOCOCR2 = VALUE_SYSTEM_HOCOCR2; + R_SYSTEM->HOCOWTCR = VALUE_SYSTEM_HOCOWTCR; + R_SYSTEM->HOCOCR_b.HCSTP = 0; // Start HOCO + + while ( !( R_SYSTEM->OSCSF_b.HOCOSF ) ) { + // Wait for HOCO to stabilize + } + } + + if ( !( VALUE_SYSTEM_PLLCR & R_SYSTEM_PLLCR_PLLSTP_Msk ) ) { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + R_SYSTEM->PLLCCR = VALUE_SYSTEM_PLLCCR; + R_SYSTEM->PLLCR_b.PLLSTP = 0; // PLL is operating + + while ( !( R_SYSTEM->OSCSF_b.PLLSF ) ) { + // Wait for PLL to stabilize + } + } else { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + } + + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; + + R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; + + Delay_1ms(); + + R_SYSTEM->SCKSCR = VALUE_SYSTEM_SCKSCR; + + Delay_1ms(); + + if ( 150000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 3; // 3 waits + } else if ( 100000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 2; // 2 waits + } else if ( 50000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 1; // 1 wait + } else { + R_FCACHE->FLWT = 0; // 0 waits + } + + R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { + R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); + R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out + } -} \ No newline at end of file + // Lock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +} diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c index d919219af..912765272 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c @@ -42,7 +42,783 @@ #include "core_header.h" #include "mcu.h" +extern void * __Vectors[]; + +typedef struct +{ + uint32_t ICLK_Frequency; // System clock frequency in Hz + uint32_t PCLKA_Frequency; // PCLKA clock frequency in Hz + uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz + uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz + uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz +} SYSTEM_ClocksTypeDef; + +static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) + +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) + +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#define BSP_IO_PWPR_PFSWE_OFFSET (6) + +// ----------------------------------------------------------------------------------------- + +/*********************************************************************** + * ID Code Configuration for On-Chip Flash Protection + * This section places the user-defined 128-bit ID code into a special + * memory section. These values can be used to lock/unlock the flash. + * + * If BSP_FEATURE_BSP_OSIS_PADDING is enabled, each 32-bit word is + * followed by 0xFFFFFFFF as padding. + ***********************************************************************/ + +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) +#define BSP_DONT_REMOVE __attribute__((used)) + +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" + +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE 1 +#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1 +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +/** ID code values (4 x 32-bit, optionally padded) */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION(BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 1 + #endif + + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 2 + #endif + + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 3 + #endif + + BSP_CFG_ID_CODE_LONG_4 +}; + +#endif // BSP_FEATURE_FLASH_SUPPORTS_ID_CODE + +/*********************************************************************** + * Option Function Select (OFS) Settings + ***********************************************************************/ +#define OFS_SEQ1 (0xA001A001 | (1 << 1) | (3 << 2)) +#define OFS_SEQ2 ((15 << 4) | (3 << 8) | (3 << 10)) +#define OFS_SEQ3 ((1 << 12) | (1 << 14) | (1 << 17)) +#define OFS_SEQ4 ((3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)) +#define OFS_SEQ5 ((1 << 28) | (1 << 30)) + +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/*********************************************************************** + * OFS1 Configuration - HOCO Frequency and other boot options + ***********************************************************************/ +#define HOCO_ENABLE (VALUE_SYSTEM_HOCOCR & 0x1) +#define HOCO_FREQ (VALUE_SYSTEM_HOCOCR2 & 0x3) + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) // TODO HOCO options +#define BSP_CFG_HOCO_FREQUENCY (HOCO_FREQ) // TODO HOCO options +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) + +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/*********************************************************************** + * MPU Configuration + ***********************************************************************/ +#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) + +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) + +/* MPU Control Register value based on the configuration above */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE << 0) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*********************************************************************** + * ROM Register Table (stored in a dedicated memory section) + ***********************************************************************/ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION(BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, // OFS0 register value + (uint32_t) BSP_ROM_REG_OFS1_SETTING, // OFS1 register value (with HOCO frequency) + +#if __MPU_PRESENT + // PC0 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + + // PC1 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + + // MPU Region 0 + ((uint32_t)(BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU)), + ((uint32_t)((BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U)), + + // MPU Region 1 + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + + // MPU Region 2 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Region 3 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Control Register + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +#endif +}; +// ----------------------------------------------------------------------------------------- + +/** + * @brief Sets the system clock based on user preferences. + * + * Configures the system clock source, frequency and dividers according to + * preferences stored internally by the library. This function is called during + * system initialization and is not intended for direct use by application code. + * + * @return None + * + * @note This function is `static` and only available within this source file. + */ +static void system_clock_configuration(); + +// ----------------------------------------------------------------------------------------- + +/** + * @brief Gets the system clock values. + * + * Calculates configured clock frequency for system clocks which are used by different + * MCU modules. + * + * @return None + */ +void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { + uint32_t prescaler, source_clock; + + // Get the frequency of main clock. + SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; + + // Get the source frequency for all clocks. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000000 ) >> 24 ]; + source_clock = SYSTEM_Clocks->ICLK_Frequency * prescaler; + + // Get PCLKA clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->PCLKA_Frequency = source_clock / prescaler; + + // Get PCLKB clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x700 ) >> 8 ]; + SYSTEM_Clocks->PCLKB_Frequency = source_clock / prescaler; + + // Get PCLKC clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x70 ) >> 4 ]; + SYSTEM_Clocks->PCLKC_Frequency = source_clock / prescaler; + + // Get PCLKD clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7 ) ]; + SYSTEM_Clocks->PCLKD_Frequency = source_clock / prescaler; + + // Get FCLK clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; +} + +/** + * @brief Initializes the microcontroller system. + * + * Performs essential setup, including clock configuration and core-level + * initialization. This function should be called once at startup before + * using any other peripherals or system services. + * + * @return None + */ void SystemInit(void) { + // Set-up FPU settings + SCB->CPACR |= ((3UL << (10*2)) | (3UL << (11*2))); + SCB->VTOR = (uint32_t) &__Vectors; + + // Lock VBTCR1 register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + + // BSP clock init start + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + // Flash cache disable + R_FCACHE->FCACHEE = 0U; + + // Clock setting + system_clock_configuration(); + + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + // Enable flash cache + R_FCACHE->FCACHEE = 1U; + + // Disable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 0; + + // Setup NMI interrupt + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + // Setup start address + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + // Setup end address + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. + * NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + // Enable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 1U; + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + + // Pin config + R_PMISC->PWPR = 0; // Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; // Set PFSWE bit - writing to PFS register enabled + + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } + } +} + +// ----------------------------------------------------------------------------------------- + +static void system_clock_configuration() { + // Unlock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + + // Disable cache before modifying SOPCCR or OPCCR + R_FCACHE->FCACHEE = 0U; + + R_SYSTEM->OPCCR = VALUE_SYSTEM_OPCCR; + + if ( !( VALUE_SYSTEM_MOSCCR & R_SYSTEM_MOSCCR_MOSTP_Msk ) ) { + // Main oscillator selected + R_SYSTEM->MOSCCR_b.MOSTP = 1; // Stop XTAL + R_SYSTEM->MOMCR = VALUE_SYSTEM_MOMCR; + R_SYSTEM->MOSCWTCR = VALUE_SYSTEM_MOSCWTCR; + R_SYSTEM->MOSCCR_b.MOSTP = 0; // Start XTAL + uint8_t check = R_SYSTEM->MOSCCR; // Read MOSTP + + while ( !( R_SYSTEM->OSCSF_b.MOSCSF ) ) { + // Wait for XTAL to stabilize + } + } + + if ( !( VALUE_SYSTEM_SOSCCR & R_SYSTEM_SOSCCR_SOSTP_Msk ) ) { + R_SYSTEM->SOSCCR_b.SOSTP = 1; // Stop SOSC + R_SYSTEM->SOMCR = VALUE_SYSTEM_SOMCR; + R_SYSTEM->SOSCCR_b.SOSTP = 0; // Start SOSC + } + + if ( !( VALUE_SYSTEM_HOCOCR & R_SYSTEM_HOCOCR_HCSTP_Msk ) ) { + if( 0x2 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 20MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x263; + } else if ( 0x1 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 18MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x226; + } else if ( 0x0 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 16MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x1E9; + } + + R_SYSTEM->FLLCR1_b.FLLEN = 0x1; + + R_SYSTEM->HOCOCR2 = VALUE_SYSTEM_HOCOCR2; + R_SYSTEM->HOCOWTCR = VALUE_SYSTEM_HOCOWTCR; + R_SYSTEM->HOCOCR_b.HCSTP = 0; // Start HOCO + + while ( !( R_SYSTEM->OSCSF_b.HOCOSF ) ) { + // Wait for HOCO to stabilize + } + } + + if ( !( VALUE_SYSTEM_PLLCR & R_SYSTEM_PLLCR_PLLSTP_Msk ) ) { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + R_SYSTEM->PLLCCR = VALUE_SYSTEM_PLLCCR; + R_SYSTEM->PLLCR_b.PLLSTP = 0; // PLL is operating + + while ( !( R_SYSTEM->OSCSF_b.PLLSF ) ) { + // Wait for PLL to stabilize + } + } else { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + } + + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; + + R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; + + Delay_1ms(); + + R_SYSTEM->SCKSCR = VALUE_SYSTEM_SCKSCR; + + Delay_1ms(); + + if ( 150000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 3; // 3 waits + } else if ( 100000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 2; // 2 waits + } else if ( 50000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 1; // 1 wait + } else { + R_FCACHE->FLWT = 0; // 0 waits + } + + R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { + R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); + R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out + } -} \ No newline at end of file + // Lock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +} diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c index d919219af..912765272 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c @@ -42,7 +42,783 @@ #include "core_header.h" #include "mcu.h" +extern void * __Vectors[]; + +typedef struct +{ + uint32_t ICLK_Frequency; // System clock frequency in Hz + uint32_t PCLKA_Frequency; // PCLKA clock frequency in Hz + uint32_t PCLKB_Frequency; // PCLKB clock frequency in Hz + uint32_t PCLKC_Frequency; // PCLKC clock frequency in Hz + uint32_t PCLKD_Frequency; // PCLKD clock frequency in Hz + uint32_t FCLK_Frequency; // Flash interface clock frequency in Hz +} SYSTEM_ClocksTypeDef; + +static uint8_t ClockPrescTable[ 7 ] = { 1, 2, 4, 8, 16, 32, 64 }; + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES) +#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) + +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) + +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +typedef elc_event_t bsp_interrupt_event_t; + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#define BSP_IO_PWPR_PFSWE_OFFSET (6) + +// ----------------------------------------------------------------------------------------- + +/*********************************************************************** + * ID Code Configuration for On-Chip Flash Protection + * This section places the user-defined 128-bit ID code into a special + * memory section. These values can be used to lock/unlock the flash. + * + * If BSP_FEATURE_BSP_OSIS_PADDING is enabled, each 32-bit word is + * followed by 0xFFFFFFFF as padding. + ***********************************************************************/ + +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) +#define BSP_DONT_REMOVE __attribute__((used)) + +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" + +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE 1 +#if BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1 +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +/** ID code values (4 x 32-bit, optionally padded) */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION(BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 1 + #endif + + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 2 + #endif + + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, // Padding after ID code 3 + #endif + + BSP_CFG_ID_CODE_LONG_4 +}; + +#endif // BSP_FEATURE_FLASH_SUPPORTS_ID_CODE + +/*********************************************************************** + * Option Function Select (OFS) Settings + ***********************************************************************/ +#define OFS_SEQ1 (0xA001A001 | (1 << 1) | (3 << 2)) +#define OFS_SEQ2 ((15 << 4) | (3 << 8) | (3 << 10)) +#define OFS_SEQ3 ((1 << 12) | (1 << 14) | (1 << 17)) +#define OFS_SEQ4 ((3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)) +#define OFS_SEQ5 ((1 << 28) | (1 << 30)) + +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/*********************************************************************** + * OFS1 Configuration - HOCO Frequency and other boot options + ***********************************************************************/ +#define HOCO_ENABLE (VALUE_SYSTEM_HOCOCR & 0x1) +#define HOCO_FREQ (VALUE_SYSTEM_HOCOCR2 & 0x3) + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) // TODO HOCO options +#define BSP_CFG_HOCO_FREQUENCY (HOCO_FREQ) // TODO HOCO options +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) + +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/*********************************************************************** + * MPU Configuration + ***********************************************************************/ +#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) + +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) + +/* MPU Control Register value based on the configuration above */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE << 0) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*********************************************************************** + * ROM Register Table (stored in a dedicated memory section) + ***********************************************************************/ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION(BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, // OFS0 register value + (uint32_t) BSP_ROM_REG_OFS1_SETTING, // OFS1 register value (with HOCO frequency) + +#if __MPU_PRESENT + // PC0 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + + // PC1 settings + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + + // MPU Region 0 + ((uint32_t)(BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU)), + ((uint32_t)((BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U)), + + // MPU Region 1 + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + + // MPU Region 2 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Region 3 + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + + // MPU Control Register + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +#endif +}; +// ----------------------------------------------------------------------------------------- + +/** + * @brief Sets the system clock based on user preferences. + * + * Configures the system clock source, frequency and dividers according to + * preferences stored internally by the library. This function is called during + * system initialization and is not intended for direct use by application code. + * + * @return None + * + * @note This function is `static` and only available within this source file. + */ +static void system_clock_configuration(); + +// ----------------------------------------------------------------------------------------- + +/** + * @brief Gets the system clock values. + * + * Calculates configured clock frequency for system clocks which are used by different + * MCU modules. + * + * @return None + */ +void SYSTEM_GetClocksFrequency( SYSTEM_ClocksTypeDef * SYSTEM_Clocks ) { + uint32_t prescaler, source_clock; + + // Get the frequency of main clock. + SYSTEM_Clocks->ICLK_Frequency = FOSC_KHZ_VALUE * 1000; + + // Get the source frequency for all clocks. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000000 ) >> 24 ]; + source_clock = SYSTEM_Clocks->ICLK_Frequency * prescaler; + + // Get PCLKA clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->PCLKA_Frequency = source_clock / prescaler; + + // Get PCLKB clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x700 ) >> 8 ]; + SYSTEM_Clocks->PCLKB_Frequency = source_clock / prescaler; + + // Get PCLKC clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x70 ) >> 4 ]; + SYSTEM_Clocks->PCLKC_Frequency = source_clock / prescaler; + + // Get PCLKD clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7 ) ]; + SYSTEM_Clocks->PCLKD_Frequency = source_clock / prescaler; + + // Get FCLK clock frequency. + prescaler = ClockPrescTable[ ( VALUE_SYSTEM_SCKDIVCR & 0x7000 ) >> 12 ]; + SYSTEM_Clocks->FCLK_Frequency = source_clock / prescaler; +} + +/** + * @brief Initializes the microcontroller system. + * + * Performs essential setup, including clock configuration and core-level + * initialization. This function should be called once at startup before + * using any other peripherals or system services. + * + * @return None + */ void SystemInit(void) { + // Set-up FPU settings + SCB->CPACR |= ((3UL << (10*2)) | (3UL << (11*2))); + SCB->VTOR = (uint32_t) &__Vectors; + + // Lock VBTCR1 register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + + // BSP clock init start + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + // Flash cache disable + R_FCACHE->FCACHEE = 0U; + + // Clock setting + system_clock_configuration(); + + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + // Enable flash cache + R_FCACHE->FCACHEE = 1U; + + // Disable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 0; + + // Setup NMI interrupt + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + // Setup start address + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + // Setup end address + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. + * NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + // Enable MSP monitoring + R_MPU_SPMON->SP[0].CTL = 1U; + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + + // Pin config + R_PMISC->PWPR = 0; // Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; // Set PFSWE bit - writing to PFS register enabled + + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } + } +} + +// ----------------------------------------------------------------------------------------- + +static void system_clock_configuration() { + // Unlock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + + // Disable cache before modifying SOPCCR or OPCCR + R_FCACHE->FCACHEE = 0U; + + R_SYSTEM->OPCCR = VALUE_SYSTEM_OPCCR; + + if ( !( VALUE_SYSTEM_MOSCCR & R_SYSTEM_MOSCCR_MOSTP_Msk ) ) { + // Main oscillator selected + R_SYSTEM->MOSCCR_b.MOSTP = 1; // Stop XTAL + R_SYSTEM->MOMCR = VALUE_SYSTEM_MOMCR; + R_SYSTEM->MOSCWTCR = VALUE_SYSTEM_MOSCWTCR; + R_SYSTEM->MOSCCR_b.MOSTP = 0; // Start XTAL + uint8_t check = R_SYSTEM->MOSCCR; // Read MOSTP + + while ( !( R_SYSTEM->OSCSF_b.MOSCSF ) ) { + // Wait for XTAL to stabilize + } + } + + if ( !( VALUE_SYSTEM_SOSCCR & R_SYSTEM_SOSCCR_SOSTP_Msk ) ) { + R_SYSTEM->SOSCCR_b.SOSTP = 1; // Stop SOSC + R_SYSTEM->SOMCR = VALUE_SYSTEM_SOMCR; + R_SYSTEM->SOSCCR_b.SOSTP = 0; // Start SOSC + } + + if ( !( VALUE_SYSTEM_HOCOCR & R_SYSTEM_HOCOCR_HCSTP_Msk ) ) { + if( 0x2 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 20MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x263; + } else if ( 0x1 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 18MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x226; + } else if ( 0x0 == ( VALUE_SYSTEM_HOCOCR2 & 0x3 ) ) // 16MHz + { + R_SYSTEM->FLLCR2_b.FLLCNTL = 0x1E9; + } + + R_SYSTEM->FLLCR1_b.FLLEN = 0x1; + + R_SYSTEM->HOCOCR2 = VALUE_SYSTEM_HOCOCR2; + R_SYSTEM->HOCOWTCR = VALUE_SYSTEM_HOCOWTCR; + R_SYSTEM->HOCOCR_b.HCSTP = 0; // Start HOCO + + while ( !( R_SYSTEM->OSCSF_b.HOCOSF ) ) { + // Wait for HOCO to stabilize + } + } + + if ( !( VALUE_SYSTEM_PLLCR & R_SYSTEM_PLLCR_PLLSTP_Msk ) ) { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + R_SYSTEM->PLLCCR = VALUE_SYSTEM_PLLCCR; + R_SYSTEM->PLLCR_b.PLLSTP = 0; // PLL is operating + + while ( !( R_SYSTEM->OSCSF_b.PLLSF ) ) { + // Wait for PLL to stabilize + } + } else { + R_SYSTEM->PLLCR_b.PLLSTP = 1; // PLL is stopped + } + + R_SYSTEM->LOCOCR = VALUE_SYSTEM_LOCOCR; + + R_SYSTEM->MOCOCR = VALUE_SYSTEM_MOCOCR; + + Delay_1ms(); + + R_SYSTEM->SCKSCR = VALUE_SYSTEM_SCKSCR; + + Delay_1ms(); + + if ( 150000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 3; // 3 waits + } else if ( 100000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 2; // 2 waits + } else if ( 50000 < FOSC_KHZ_VALUE ) { + R_FCACHE->FLWT = 1; // 1 wait + } else { + R_FCACHE->FLWT = 0; // 0 waits + } + + R_SYSTEM->SCKDIVCR = VALUE_SYSTEM_SCKDIVCR; + + if ( VALUE_SYSTEM_CKOCR & R_SYSTEM_CKOCR_CKOEN_Msk ) { + R_SYSTEM->CKOCR = VALUE_SYSTEM_CKOCR & ( R_SYSTEM_CKOCR_CKODIV_Msk | R_SYSTEM_CKOCR_CKOSEL_Msk ); + R_SYSTEM->CKOCR_b.CKOEN = 1; // Enable clock out + } -} \ No newline at end of file + // Lock write protection register + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +} From 59570b86795a9ab672df0d133b85eb23b6dcdd43 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Wed, 8 Oct 2025 14:19:23 +0200 Subject: [PATCH 6/8] Updated json files for RA6M5 MCUs --- ARM/gcc_clang/def/R7FA6M5AG2CBG.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AG2CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AG3CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AG3CFB.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AG3CFC.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AG3CFP.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH2CBG.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH2CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH3CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH3CFB.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH3CFC.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5AH3CFP.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF2CBG.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF2CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF3CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF3CFB.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF3CFC.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BF3CFP.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG2CBG.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG2CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG3CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG3CFB.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG3CFC.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BG3CFP.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH2CBG.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH2CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH3CBM.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH3CFB.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH3CFC.json | 24 ++++++++++++------------ ARM/gcc_clang/def/R7FA6M5BH3CFP.json | 24 ++++++++++++------------ 30 files changed, 360 insertions(+), 360 deletions(-) diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json index ee137e824..5533257d5 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBG.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG2CBG", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json index 98b54161f..9e8f41ea5 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG2CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG2CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json index 5c34b93c7..66d769039 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json index af8dfded2..9f77bbc9c 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFB.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CFB", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json index 98a6205d1..4813ffd73 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFC.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CFC", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json index ef9cfc75a..43586ee56 100644 --- a/ARM/gcc_clang/def/R7FA6M5AG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AG3CFP.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AG3CFP", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json index 226dbbc15..2ee6cf8cb 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBG.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH2CBG", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json index 120d0fcd5..5f7e06563 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH2CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH2CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json index 6aed564eb..60f10186c 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH3CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json index 41bdc5f99..13e515bb9 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFB.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH3CFB", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json index f0faa4cee..a99fb1f08 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFC.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH3CFC", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json index ad2fccd19..d7654607e 100644 --- a/ARM/gcc_clang/def/R7FA6M5AH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5AH3CFP.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5AH3CFP", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json index e833cc17f..98f2c0291 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBG.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF2CBG", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json index 367da58d5..c2e06d4ed 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF2CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF2CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json index 84e9f0522..0a96fd0d3 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF3CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json index b66c79525..8294a9914 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFB.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF3CFB", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json index 89189f287..144b79fc9 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFC.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF3CFC", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json index 7232aff04..870bed9d1 100644 --- a/ARM/gcc_clang/def/R7FA6M5BF3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BF3CFP.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BF3CFP", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json index 551e43253..3951c769f 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBG.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG2CBG", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json index 25e56e689..448578b4b 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG2CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG2CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json index afcc9be5b..02a53de20 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG3CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json index e1e4513a0..1c0a89a8e 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFB.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG3CFB", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json index 285e7737a..eec4235fc 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFC.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG3CFC", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json index 4a089b7c0..bcae755c9 100644 --- a/ARM/gcc_clang/def/R7FA6M5BG3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BG3CFP.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BG3CFP", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json index 81f0dfd15..884e6cda2 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBG.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBG.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH2CBG", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json index 84d2001e9..5c5f1b597 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH2CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH2CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH2CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json index 120b7f18f..dfd5ed617 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CBM.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CBM.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CBM", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json index 5f7d25a25..286e5914a 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFB.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFB.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CFB", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json index da214187d..1300659f1 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFC.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFC.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CFC", - "clock": "1" + "clock": "200" } \ No newline at end of file diff --git a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json index 667b08174..5e32f3312 100644 --- a/ARM/gcc_clang/def/R7FA6M5BH3CFP.json +++ b/ARM/gcc_clang/def/R7FA6M5BH3CFP.json @@ -6,7 +6,7 @@ "fields": [ { "hidden": false, - "init": "2", + "init": "1", "key": "PCKD", "label": "Peripheral Module Clock D (PCLKD) Select", "mask": "7", @@ -191,7 +191,7 @@ }, { "hidden": false, - "init": "2000000", + "init": "0", "key": "ICK", "label": "System Clock (ICLK) Select", "mask": "7000000", @@ -273,7 +273,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "5", "key": "CKSEL", "label": "Clock Source Select", "mask": "7", @@ -314,7 +314,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "PLIDIV", "label": "PLL Input Frequency Division Ratio Select", "mask": "3", @@ -335,7 +335,7 @@ }, { "hidden": false, - "init": "0", + "init": "10", "key": "PLSRCSEL", "label": "PLL Clock Source Select", "mask": "10", @@ -352,7 +352,7 @@ }, { "hidden": false, - "init": "1300", + "init": "2700", "key": "PLLMUL", "label": "PLL Frequency Multiplication Factor Select", "mask": "3f00", @@ -533,7 +533,7 @@ "fields": [ { "hidden": false, - "init": "1", + "init": "0", "key": "PLLSTP", "label": "PLL Stop Control", "mask": "1", @@ -686,7 +686,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "MCSTP", "label": "MOCO Stop", "mask": "1", @@ -848,7 +848,7 @@ "fields": [ { "hidden": false, - "init": "5", + "init": "9", "key": "MSTS", "label": "Main Clock Oscillator Wait Time Setting", "mask": "f", @@ -997,7 +997,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "SOSTP", "label": "Sub Clock Oscillator Stop", "mask": "1", @@ -1047,7 +1047,7 @@ "fields": [ { "hidden": false, - "init": "0", + "init": "1", "key": "LCSTP", "label": "LOCO Stop", "mask": "1", @@ -1070,5 +1070,5 @@ "core": "M33EF", "delay_src_path": "delays/m33ef/__lib_delays.c", "mcu": "R7FA6M5BH3CFP", - "clock": "1" + "clock": "200" } \ No newline at end of file From 9b4f49ea5d569453f7b6d9e333e141503c265337 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 9 Oct 2025 12:09:59 +0200 Subject: [PATCH 7/8] Fixed cmake for all ra6m5 packs --- ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake | 2 +- ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake index f34d323e8..6857c6113 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5ag.cmake @@ -2,6 +2,6 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AG2CBG$|^R7FA6M5AG2CBM$|^R7FA6M5AG3CBM$|^R7FA6M5 set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) list(APPEND local_list_include system/src/${vendor}/ra6m5ag/init_clock.c) - list(APPEND local_dir_install system/src/renesas/ra6m5ag/thirdparty/ra6m5ag) + list(APPEND local_dir_install system/src/${vendor}/ra6m5ag/thirdparty/ra6m5ag) set(${thirdpartyInstall} ra6m5ag/thirdparty/ra6m5ag PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake index e80f9b4b3..118e9d553 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5ah.cmake @@ -2,6 +2,6 @@ if(${MCU_NAME} MATCHES "^R7FA6M5AH2CBG$|^R7FA6M5AH2CBM$|^R7FA6M5AH3CBM$|^R7FA6M5 set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) list(APPEND local_list_include system/src/${vendor}/ra6m5ah/init_clock.c) - list(APPEND local_dir_install system/src/renesas/ra6m5ah/thirdparty/ra6m5ah) + list(APPEND local_dir_install system/src/${vendor}/ra6m5ah/thirdparty/ra6m5ah) set(${thirdpartyInstall} ra6m5ah/thirdparty/ra6m5ah PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake index 7b4c7e18d..527ba30db 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bf.cmake @@ -2,6 +2,6 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BF2CBG$|^R7FA6M5BF2CBM$|^R7FA6M5BF3CBM$|^R7FA6M5 set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) list(APPEND local_list_include system/src/${vendor}/ra6m5bf/init_clock.c) - list(APPEND local_dir_install system/src/renesas/ra6m5bf/thirdparty/ra6m5bf) + list(APPEND local_dir_install system/src/${vendor}/ra6m5bf/thirdparty/ra6m5bf) set(${thirdpartyInstall} ra6m5bf/thirdparty/ra6m5bf PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake index 587d09548..7d2a47697 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bg.cmake @@ -2,6 +2,6 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BG2CBG$|^R7FA6M5BG2CBM$|^R7FA6M5BG3CBM$|^R7FA6M5 set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) list(APPEND local_list_include system/src/${vendor}/ra6m5bg/init_clock.c) - list(APPEND local_dir_install system/src/renesas/ra6m5bg/thirdparty/ra6m5bg) + list(APPEND local_dir_install system/src/${vendor}/ra6m5bg/thirdparty/ra6m5bg) set(${thirdpartyInstall} ra6m5bg/thirdparty/ra6m5bg PARENT_SCOPE) endif() diff --git a/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake b/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake index b3790c992..61420daf4 100644 --- a/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake +++ b/ARM/gcc_clang/cmake/renesas/ra6m5bh.cmake @@ -2,6 +2,6 @@ if(${MCU_NAME} MATCHES "^R7FA6M5BH2CBG$|^R7FA6M5BH2CBM$|^R7FA6M5BH3CBM$|^R7FA6M5 set(${linkerScript} linker_scripts/${vendor}/${TOOLCHAIN_ID}/${mcu_match}.ld PARENT_SCOPE) set(${startupFile} startup/${vendor}/${mcu_match}.c PARENT_SCOPE) list(APPEND local_list_include system/src/${vendor}/ra6m5bh/init_clock.c) - list(APPEND local_dir_install system/src/renesas/ra6m5bh/thirdparty/ra6m5bh) + list(APPEND local_dir_install system/src/${vendor}/ra6m5bh/thirdparty/ra6m5bh) set(${thirdpartyInstall} ra6m5bh/thirdparty/ra6m5bh PARENT_SCOPE) endif() From b6295f0c201d9c25b289d5617a9341f65ee3c608 Mon Sep 17 00:00:00 2001 From: IvanRuzavin Date: Thu, 9 Oct 2025 15:40:39 +0200 Subject: [PATCH 8/8] Fixed elc_event structures --- .../system/src/renesas/ra6m5ag/init_clock.c | 570 ++++++++---------- .../system/src/renesas/ra6m5ah/init_clock.c | 570 ++++++++---------- .../system/src/renesas/ra6m5bf/init_clock.c | 570 ++++++++---------- .../system/src/renesas/ra6m5bg/init_clock.c | 570 ++++++++---------- .../system/src/renesas/ra6m5bh/init_clock.c | 570 ++++++++---------- 5 files changed, 1315 insertions(+), 1535 deletions(-) diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c index 912765272..355e14004 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ag/init_clock.c @@ -77,7 +77,7 @@ extern void (* __init_array_end[])(void); #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) #define BSP_WEAK_REFERENCE __attribute__((weak)) -typedef enum e_elc_event_ra6m3 +typedef enum e_elc_event_ra6m5 { ELC_EVENT_NONE = (0x0), // Link disabled ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 @@ -106,6 +106,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt @@ -119,313 +120,268 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch - ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt - ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt - ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt - ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt - ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt - ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x063), // Receive data full - ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x065), // Transmit end - ELC_EVENT_IIC0_ERI = (0x066), // Transfer error - ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x068), // Receive data full - ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x070), // Transfer error - ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x073), // Receive data full - ELC_EVENT_SSI0_INT = (0x075), // Error interrupt - ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use - ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_INT = (0x079), // Error interrupt - ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty - ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full - ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow - ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow - ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end - ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt - ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt - ELC_EVENT_PDC_INT = (0x081), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x085), // Key interrupt - ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt - ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt - ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt - ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt - ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt - ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow - ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A - ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow - ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A - ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow - ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A - ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow - ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A - ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow - ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A - ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow - ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A - ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow - ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A - ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A - ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow - ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A - ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B - ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C - ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D - ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E - ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F - ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow - ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow - ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A - ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B - ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C - ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D - ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E - ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F - ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow - ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow - ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A - ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B - ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C - ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D - ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E - ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F - ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow - ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow - ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A - ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B - ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C - ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D - ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E - ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F - ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow - ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 + ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 + ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 + ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt - ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt - ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt - ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt - ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection - ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection - ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection - ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection - ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection - ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection - ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection - ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection - ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection - ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection - ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection - ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection - ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x174), // Receive data full - ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x176), // Transmit end - ELC_EVENT_SCI0_ERI = (0x177), // Receive error - ELC_EVENT_SCI0_AM = (0x178), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full - ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end - ELC_EVENT_SCI1_ERI = (0x17D), // Receive error - ELC_EVENT_SCI1_AM = (0x17E), // Address match event - ELC_EVENT_SCI2_RXI = (0x180), // Receive data full - ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x182), // Transmit end - ELC_EVENT_SCI2_ERI = (0x183), // Receive error - ELC_EVENT_SCI2_AM = (0x184), // Address match event - ELC_EVENT_SCI3_RXI = (0x186), // Receive data full - ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x188), // Transmit end - ELC_EVENT_SCI3_ERI = (0x189), // Receive error - ELC_EVENT_SCI3_AM = (0x18A), // Address match event - ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI4_ERI = (0x18F), // Receive error - ELC_EVENT_SCI4_AM = (0x190), // Address match event - ELC_EVENT_SCI5_RXI = (0x192), // Receive data full - ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x194), // Transmit end - ELC_EVENT_SCI5_ERI = (0x195), // Receive error - ELC_EVENT_SCI5_AM = (0x196), // Address match event - ELC_EVENT_SCI6_RXI = (0x198), // Receive data full - ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI6_ERI = (0x19B), // Receive error - ELC_EVENT_SCI6_AM = (0x19C), // Address match event - ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI7_AM = (0x1A2), // Address match event - ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI8_AM = (0x1A8), // Address match event - ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI9_AM = (0x1AE), // Address match event - ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle - ELC_EVENT_SPI0_ERI = (0x1BF), // Error - ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle - ELC_EVENT_SPI1_ERI = (0x1C4), // Error - ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event - ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt - ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request - ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access - ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access - ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect - ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request - ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line - ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow - ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow - ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt - ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt - ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection } elc_event_t; typedef elc_event_t bsp_interrupt_event_t; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c index 912765272..355e14004 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5ah/init_clock.c @@ -77,7 +77,7 @@ extern void (* __init_array_end[])(void); #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) #define BSP_WEAK_REFERENCE __attribute__((weak)) -typedef enum e_elc_event_ra6m3 +typedef enum e_elc_event_ra6m5 { ELC_EVENT_NONE = (0x0), // Link disabled ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 @@ -106,6 +106,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt @@ -119,313 +120,268 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch - ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt - ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt - ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt - ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt - ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt - ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x063), // Receive data full - ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x065), // Transmit end - ELC_EVENT_IIC0_ERI = (0x066), // Transfer error - ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x068), // Receive data full - ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x070), // Transfer error - ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x073), // Receive data full - ELC_EVENT_SSI0_INT = (0x075), // Error interrupt - ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use - ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_INT = (0x079), // Error interrupt - ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty - ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full - ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow - ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow - ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end - ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt - ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt - ELC_EVENT_PDC_INT = (0x081), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x085), // Key interrupt - ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt - ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt - ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt - ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt - ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt - ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow - ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A - ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow - ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A - ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow - ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A - ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow - ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A - ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow - ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A - ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow - ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A - ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow - ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A - ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A - ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow - ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A - ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B - ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C - ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D - ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E - ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F - ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow - ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow - ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A - ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B - ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C - ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D - ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E - ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F - ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow - ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow - ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A - ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B - ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C - ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D - ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E - ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F - ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow - ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow - ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A - ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B - ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C - ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D - ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E - ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F - ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow - ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 + ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 + ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 + ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt - ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt - ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt - ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt - ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection - ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection - ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection - ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection - ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection - ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection - ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection - ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection - ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection - ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection - ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection - ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection - ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x174), // Receive data full - ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x176), // Transmit end - ELC_EVENT_SCI0_ERI = (0x177), // Receive error - ELC_EVENT_SCI0_AM = (0x178), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full - ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end - ELC_EVENT_SCI1_ERI = (0x17D), // Receive error - ELC_EVENT_SCI1_AM = (0x17E), // Address match event - ELC_EVENT_SCI2_RXI = (0x180), // Receive data full - ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x182), // Transmit end - ELC_EVENT_SCI2_ERI = (0x183), // Receive error - ELC_EVENT_SCI2_AM = (0x184), // Address match event - ELC_EVENT_SCI3_RXI = (0x186), // Receive data full - ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x188), // Transmit end - ELC_EVENT_SCI3_ERI = (0x189), // Receive error - ELC_EVENT_SCI3_AM = (0x18A), // Address match event - ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI4_ERI = (0x18F), // Receive error - ELC_EVENT_SCI4_AM = (0x190), // Address match event - ELC_EVENT_SCI5_RXI = (0x192), // Receive data full - ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x194), // Transmit end - ELC_EVENT_SCI5_ERI = (0x195), // Receive error - ELC_EVENT_SCI5_AM = (0x196), // Address match event - ELC_EVENT_SCI6_RXI = (0x198), // Receive data full - ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI6_ERI = (0x19B), // Receive error - ELC_EVENT_SCI6_AM = (0x19C), // Address match event - ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI7_AM = (0x1A2), // Address match event - ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI8_AM = (0x1A8), // Address match event - ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI9_AM = (0x1AE), // Address match event - ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle - ELC_EVENT_SPI0_ERI = (0x1BF), // Error - ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle - ELC_EVENT_SPI1_ERI = (0x1C4), // Error - ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event - ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt - ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request - ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access - ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access - ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect - ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request - ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line - ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow - ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow - ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt - ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt - ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection } elc_event_t; typedef elc_event_t bsp_interrupt_event_t; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c index 912765272..355e14004 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bf/init_clock.c @@ -77,7 +77,7 @@ extern void (* __init_array_end[])(void); #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) #define BSP_WEAK_REFERENCE __attribute__((weak)) -typedef enum e_elc_event_ra6m3 +typedef enum e_elc_event_ra6m5 { ELC_EVENT_NONE = (0x0), // Link disabled ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 @@ -106,6 +106,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt @@ -119,313 +120,268 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch - ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt - ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt - ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt - ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt - ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt - ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x063), // Receive data full - ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x065), // Transmit end - ELC_EVENT_IIC0_ERI = (0x066), // Transfer error - ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x068), // Receive data full - ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x070), // Transfer error - ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x073), // Receive data full - ELC_EVENT_SSI0_INT = (0x075), // Error interrupt - ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use - ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_INT = (0x079), // Error interrupt - ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty - ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full - ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow - ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow - ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end - ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt - ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt - ELC_EVENT_PDC_INT = (0x081), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x085), // Key interrupt - ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt - ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt - ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt - ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt - ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt - ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow - ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A - ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow - ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A - ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow - ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A - ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow - ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A - ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow - ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A - ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow - ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A - ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow - ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A - ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A - ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow - ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A - ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B - ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C - ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D - ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E - ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F - ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow - ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow - ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A - ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B - ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C - ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D - ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E - ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F - ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow - ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow - ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A - ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B - ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C - ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D - ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E - ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F - ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow - ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow - ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A - ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B - ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C - ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D - ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E - ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F - ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow - ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 + ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 + ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 + ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt - ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt - ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt - ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt - ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection - ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection - ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection - ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection - ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection - ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection - ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection - ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection - ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection - ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection - ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection - ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection - ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x174), // Receive data full - ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x176), // Transmit end - ELC_EVENT_SCI0_ERI = (0x177), // Receive error - ELC_EVENT_SCI0_AM = (0x178), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full - ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end - ELC_EVENT_SCI1_ERI = (0x17D), // Receive error - ELC_EVENT_SCI1_AM = (0x17E), // Address match event - ELC_EVENT_SCI2_RXI = (0x180), // Receive data full - ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x182), // Transmit end - ELC_EVENT_SCI2_ERI = (0x183), // Receive error - ELC_EVENT_SCI2_AM = (0x184), // Address match event - ELC_EVENT_SCI3_RXI = (0x186), // Receive data full - ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x188), // Transmit end - ELC_EVENT_SCI3_ERI = (0x189), // Receive error - ELC_EVENT_SCI3_AM = (0x18A), // Address match event - ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI4_ERI = (0x18F), // Receive error - ELC_EVENT_SCI4_AM = (0x190), // Address match event - ELC_EVENT_SCI5_RXI = (0x192), // Receive data full - ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x194), // Transmit end - ELC_EVENT_SCI5_ERI = (0x195), // Receive error - ELC_EVENT_SCI5_AM = (0x196), // Address match event - ELC_EVENT_SCI6_RXI = (0x198), // Receive data full - ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI6_ERI = (0x19B), // Receive error - ELC_EVENT_SCI6_AM = (0x19C), // Address match event - ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI7_AM = (0x1A2), // Address match event - ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI8_AM = (0x1A8), // Address match event - ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI9_AM = (0x1AE), // Address match event - ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle - ELC_EVENT_SPI0_ERI = (0x1BF), // Error - ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle - ELC_EVENT_SPI1_ERI = (0x1C4), // Error - ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event - ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt - ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request - ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access - ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access - ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect - ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request - ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line - ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow - ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow - ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt - ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt - ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection } elc_event_t; typedef elc_event_t bsp_interrupt_event_t; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c index 912765272..355e14004 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bg/init_clock.c @@ -77,7 +77,7 @@ extern void (* __init_array_end[])(void); #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) #define BSP_WEAK_REFERENCE __attribute__((weak)) -typedef enum e_elc_event_ra6m3 +typedef enum e_elc_event_ra6m5 { ELC_EVENT_NONE = (0x0), // Link disabled ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 @@ -106,6 +106,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt @@ -119,313 +120,268 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch - ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt - ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt - ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt - ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt - ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt - ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x063), // Receive data full - ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x065), // Transmit end - ELC_EVENT_IIC0_ERI = (0x066), // Transfer error - ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x068), // Receive data full - ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x070), // Transfer error - ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x073), // Receive data full - ELC_EVENT_SSI0_INT = (0x075), // Error interrupt - ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use - ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_INT = (0x079), // Error interrupt - ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty - ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full - ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow - ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow - ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end - ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt - ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt - ELC_EVENT_PDC_INT = (0x081), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x085), // Key interrupt - ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt - ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt - ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt - ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt - ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt - ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow - ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A - ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow - ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A - ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow - ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A - ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow - ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A - ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow - ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A - ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow - ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A - ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow - ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A - ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A - ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow - ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A - ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B - ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C - ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D - ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E - ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F - ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow - ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow - ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A - ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B - ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C - ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D - ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E - ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F - ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow - ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow - ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A - ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B - ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C - ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D - ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E - ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F - ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow - ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow - ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A - ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B - ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C - ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D - ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E - ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F - ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow - ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 + ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 + ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 + ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt - ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt - ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt - ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt - ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection - ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection - ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection - ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection - ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection - ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection - ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection - ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection - ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection - ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection - ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection - ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection - ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x174), // Receive data full - ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x176), // Transmit end - ELC_EVENT_SCI0_ERI = (0x177), // Receive error - ELC_EVENT_SCI0_AM = (0x178), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full - ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end - ELC_EVENT_SCI1_ERI = (0x17D), // Receive error - ELC_EVENT_SCI1_AM = (0x17E), // Address match event - ELC_EVENT_SCI2_RXI = (0x180), // Receive data full - ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x182), // Transmit end - ELC_EVENT_SCI2_ERI = (0x183), // Receive error - ELC_EVENT_SCI2_AM = (0x184), // Address match event - ELC_EVENT_SCI3_RXI = (0x186), // Receive data full - ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x188), // Transmit end - ELC_EVENT_SCI3_ERI = (0x189), // Receive error - ELC_EVENT_SCI3_AM = (0x18A), // Address match event - ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI4_ERI = (0x18F), // Receive error - ELC_EVENT_SCI4_AM = (0x190), // Address match event - ELC_EVENT_SCI5_RXI = (0x192), // Receive data full - ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x194), // Transmit end - ELC_EVENT_SCI5_ERI = (0x195), // Receive error - ELC_EVENT_SCI5_AM = (0x196), // Address match event - ELC_EVENT_SCI6_RXI = (0x198), // Receive data full - ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI6_ERI = (0x19B), // Receive error - ELC_EVENT_SCI6_AM = (0x19C), // Address match event - ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI7_AM = (0x1A2), // Address match event - ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI8_AM = (0x1A8), // Address match event - ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI9_AM = (0x1AE), // Address match event - ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle - ELC_EVENT_SPI0_ERI = (0x1BF), // Error - ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle - ELC_EVENT_SPI1_ERI = (0x1C4), // Error - ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event - ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt - ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request - ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access - ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access - ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect - ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request - ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line - ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow - ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow - ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt - ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt - ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection } elc_event_t; typedef elc_event_t bsp_interrupt_event_t; diff --git a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c index 912765272..355e14004 100644 --- a/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c +++ b/ARM/gcc_clang/system/src/renesas/ra6m5bh/init_clock.c @@ -77,7 +77,7 @@ extern void (* __init_array_end[])(void); #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) #define BSP_WEAK_REFERENCE __attribute__((weak)) -typedef enum e_elc_event_ra6m3 +typedef enum e_elc_event_ra6m5 { ELC_EVENT_NONE = (0x0), // Link disabled ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 @@ -106,6 +106,7 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt @@ -119,313 +120,268 @@ typedef enum e_elc_event_ra6m3 ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B - ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow - ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow - ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt - ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt - ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt - ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation - ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B - ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt - ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt - ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match - ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch - ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation - ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B - ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt - ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt - ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match - ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch - ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt - ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt - ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt - ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt - ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt - ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt - ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 - ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 - ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt - ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt - ELC_EVENT_IIC0_RXI = (0x063), // Receive data full - ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty - ELC_EVENT_IIC0_TEI = (0x065), // Transmit end - ELC_EVENT_IIC0_ERI = (0x066), // Transfer error - ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt - ELC_EVENT_IIC1_RXI = (0x068), // Receive data full - ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty - ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end - ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error - ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full - ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty - ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end - ELC_EVENT_IIC2_ERI = (0x070), // Transfer error - ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty - ELC_EVENT_SSI0_RXI = (0x073), // Receive data full - ELC_EVENT_SSI0_INT = (0x075), // Error interrupt - ELC_EVENT_SSI1_TXI_RXI = (0x078), // DEPRECATED, do not use - ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty - ELC_EVENT_SSI1_INT = (0x079), // Error interrupt - ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty - ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full - ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow - ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow - ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end - ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt - ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt - ELC_EVENT_PDC_INT = (0x081), // Error interrupt - ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt - ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt - ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt - ELC_EVENT_KEY_INT = (0x085), // Key interrupt - ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt - ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt - ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt - ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt - ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt - ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt - ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt - ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt - ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt - ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt - ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt - ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt - ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt - ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt - ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event - ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event - ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event - ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event - ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 - ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 - ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt - ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt - ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt - ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt - ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A - ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B - ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C - ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D - ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E - ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F - ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow - ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow - ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A - ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B - ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A - ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B - ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C - ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D - ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E - ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F - ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow - ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow - ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A - ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B - ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A - ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B - ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C - ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D - ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E - ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F - ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow - ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow - ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A - ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B - ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A - ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B - ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C - ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D - ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E - ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F - ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow - ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow - ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A - ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B - ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A - ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B - ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C - ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D - ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E - ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F - ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow - ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow - ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A - ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B - ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A - ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B - ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C - ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D - ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E - ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F - ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow - ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow - ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A - ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B - ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A - ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B - ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C - ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D - ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E - ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F - ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow - ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow - ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A - ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B - ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A - ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B - ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C - ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D - ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E - ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F - ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow - ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow - ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A - ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B - ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A - ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B - ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C - ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D - ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E - ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F - ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow - ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow - ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A - ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B - ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C - ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D - ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E - ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F - ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow - ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow - ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A - ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B - ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C - ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D - ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E - ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F - ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow - ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow - ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A - ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B - ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C - ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D - ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E - ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F - ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow - ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow - ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A - ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B - ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C - ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D - ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E - ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F - ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow - ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow - ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A - ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B - ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C - ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D - ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E - ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F - ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow - ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // RX fifo DMA request 2 + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // RX fifo DMA request 3 + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // RX fifo DMA request 4 + ELC_EVENT_CAN_DMAREQ5 = (0x060), // RX fifo DMA request 5 + ELC_EVENT_CAN_DMAREQ6 = (0x061), // RX fifo DMA request 6 + ELC_EVENT_CAN_DMAREQ7 = (0x062), // RX fifo DMA request 7 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event - ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt - ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt - ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt - ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt - ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection - ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection - ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection - ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection - ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection - ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection - ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection - ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection - ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection - ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection - ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection - ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection - ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 - ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 - ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt - ELC_EVENT_SCI0_RXI = (0x174), // Receive data full - ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty - ELC_EVENT_SCI0_TEI = (0x176), // Transmit end - ELC_EVENT_SCI0_ERI = (0x177), // Receive error - ELC_EVENT_SCI0_AM = (0x178), // Address match event - ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error - ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full - ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty - ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end - ELC_EVENT_SCI1_ERI = (0x17D), // Receive error - ELC_EVENT_SCI1_AM = (0x17E), // Address match event - ELC_EVENT_SCI2_RXI = (0x180), // Receive data full - ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty - ELC_EVENT_SCI2_TEI = (0x182), // Transmit end - ELC_EVENT_SCI2_ERI = (0x183), // Receive error - ELC_EVENT_SCI2_AM = (0x184), // Address match event - ELC_EVENT_SCI3_RXI = (0x186), // Receive data full - ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty - ELC_EVENT_SCI3_TEI = (0x188), // Transmit end - ELC_EVENT_SCI3_ERI = (0x189), // Receive error - ELC_EVENT_SCI3_AM = (0x18A), // Address match event - ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full - ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty - ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end - ELC_EVENT_SCI4_ERI = (0x18F), // Receive error - ELC_EVENT_SCI4_AM = (0x190), // Address match event - ELC_EVENT_SCI5_RXI = (0x192), // Receive data full - ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty - ELC_EVENT_SCI5_TEI = (0x194), // Transmit end - ELC_EVENT_SCI5_ERI = (0x195), // Receive error - ELC_EVENT_SCI5_AM = (0x196), // Address match event - ELC_EVENT_SCI6_RXI = (0x198), // Receive data full - ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty - ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end - ELC_EVENT_SCI6_ERI = (0x19B), // Receive error - ELC_EVENT_SCI6_AM = (0x19C), // Address match event - ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full - ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty - ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end - ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error - ELC_EVENT_SCI7_AM = (0x1A2), // Address match event - ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full - ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty - ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end - ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error - ELC_EVENT_SCI8_AM = (0x1A8), // Address match event - ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full - ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty - ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end - ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error - ELC_EVENT_SCI9_AM = (0x1AE), // Address match event - ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full - ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty - ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle - ELC_EVENT_SPI0_ERI = (0x1BF), // Error - ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event - ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full - ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty - ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle - ELC_EVENT_SPI1_ERI = (0x1C4), // Error - ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event - ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt - ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access - ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access - ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect - ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request - ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access - ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access - ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect - ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request - ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line - ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow - ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow - ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt - ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt - ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_EVENT_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection } elc_event_t; typedef elc_event_t bsp_interrupt_event_t;